From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 7129 invoked by alias); 30 Jan 2006 12:16:06 -0000 Received: (qmail 7121 invoked by uid 22791); 30 Jan 2006 12:16:06 -0000 X-Spam-Check-By: sourceware.org Received: from ac-202-238-16-ind.acmet.com (HELO alice.acmet.com) (61.16.238.202) by sourceware.org (qpsmtpd/0.31) with ESMTP; Mon, 30 Jan 2006 12:16:04 +0000 Received: from [192.168.0.217] (localhost [127.0.0.1] (may be forged)) by alice.acmet.com (8.11.6/8.11.6) with ESMTP id k0UCIu300443; Mon, 30 Jan 2006 17:48:56 +0530 Subject: Resume from Breakpoint - Next Instruction Address or Target Address? From: Rishi Dixit Reply-To: dixit_rishi@acmet.com To: Mailing List Content-Type: multipart/mixed; boundary="=-wqyPKgx3KbIuwi3yIlrX" Message-Id: <1138623528.3621.173.camel@rishidixit> Mime-Version: 1.0 Date: Mon, 30 Jan 2006 20:16:00 -0000 X-IsSubscribed: yes Mailing-List: contact gdb-help@sourceware.org; run by ezmlm Precedence: bulk List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-owner@sourceware.org X-SW-Source: 2006-01/txt/msg00331.txt.bz2 --=-wqyPKgx3KbIuwi3yIlrX Content-Type: text/plain Content-Transfer-Encoding: 7bit Content-length: 1674 Hi, I am studying about breakpoint functionality in GDB. My study is local to the MIPS Simulator. While studying the GDB source, I was referring the handling of BREAK instruction. This handling checks for the presence of BREAK instruction in a delay slot and alters the Program Counter. However, this information is overwritten when the CPU registers are saved before triggering a Breakpoint exception. I suspected this would lead to a loss of information regarding the target address of jump/branch instruction. To confirm this, I made a test case and checked the GDB behavior. My assumption is that since the breakpoint is hit after the jump/branch instruction has been executed, the resume should be from the target address. However, it occurred that the GDB resumes from the instruction next to the breakpoint location, which in this case will be the instruction present next to the delay slot instruction. Studying the code, I found that the Program Counter must contain the current instruction address in order to ensure normal processing of breakpoints. If this is altered, the breakpoint functionality in GDB gets affected. However, this seems contrary to my assumption that the resume should be from the target address instead of the next instruction address. Is this assumption correct? Furthermore, I wasn't able to pinpoint any part of the code where the lost information about target address could be restored after the breakpoint has been handled. Please check my understanding. If the above described condition can be handled, please provide me with pointers in the source. The prepared test case is attached. Thanks in advance, Rishi Dixit --=-wqyPKgx3KbIuwi3yIlrX Content-Disposition: attachment; filename=delayslotbreak.s Content-Type: text/plain; name=delayslotbreak.s; charset=UTF-8 Content-Transfer-Encoding: 7bit Content-length: 414 .file 1 "delayslotbreak.c" .text .align 2 .globl main .globl stop .ent main main: .frame $fp,8,$31 # vars= 0, regs= 1/0, args= 0, gp= 0 .mask 0x40000000,-8 .fmask 0x00000000,0 j _target stop: # Execution is stopped here nop # This is the delay slot instruction lw $2,0 _target: # Execution should resume from here j $31 .end main .comm i,4,4 --=-wqyPKgx3KbIuwi3yIlrX--