From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 32222 invoked by alias); 19 Apr 2012 04:25:41 -0000 Received: (qmail 32205 invoked by uid 22791); 19 Apr 2012 04:25:37 -0000 X-SWARE-Spam-Status: No, hits=-1.9 required=5.0 tests=AWL,BAYES_00,KHOP_RCVD_UNTRUST,MSGID_MULTIPLE_AT,RCVD_IN_DNSWL_LOW X-Spam-Check-By: sourceware.org Received: from service87.mimecast.com (HELO service87.mimecast.com) (91.220.42.44) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Thu, 19 Apr 2012 04:25:23 +0000 Received: from cam-owa1.Emea.Arm.com (fw-tnat.cambridge.arm.com [217.140.96.21]) by service87.mimecast.com; Thu, 19 Apr 2012 05:25:21 +0100 Received: from shawin053 ([10.1.255.212]) by cam-owa1.Emea.Arm.com with Microsoft SMTPSVC(6.0.3790.0); Thu, 19 Apr 2012 04:48:19 +0100 From: "Terry Guo" To: , Cc: "Joey Ye" , "Matthew Gretton-Dann" , Subject: [RFC] Support ARMv7M FPU registers in GDB Date: Thu, 19 Apr 2012 04:25:00 -0000 Message-ID: <000401cd1ddf$432170f0$c96452d0$@guo@arm.com> MIME-Version: 1.0 X-MC-Unique: 112041905252105501 Content-Type: text/plain; charset=WINDOWS-1252 Content-Transfer-Encoding: quoted-printable X-IsSubscribed: yes Mailing-List: contact gdb-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-owner@sourceware.org X-SW-Source: 2012-04/txt/msg00149.txt.bz2 Hi, The ARM Cortex-M4 processor is based on ARMv7M architecture and enhanced by its DSP extension and Floating Point Unit. As more and more M4 based boards are emerging in the market, I would like to propose following solution for GDB to support the access of FPU registers. 1). I studied how the GDB support other Cortex-M core like Cortex-M3 and noticed that the GDB has to use "g_packet_guess" mechanism to maintain compatibility. I don't know why some gdb stubs return faked FPA registers and some don't. But as M4 board are all recently released board, so maybe it is time for M4 gdb stub to return a correct g packet: 16 core registers + xpsr register + 16 double precision FPU registers + fpscr register. Does this expectation make sense? Is it possible for gdb stub to do so? 2). The GDB is going to need a new target description file to describe M4 register layout. I propose arm-with-m-fpu.xml for its filename. For file content, it just includes another two existing xml files arm-m-profile.xml and arm-vfpv2.xml. 3). In function arm_gdbarch_init, I propose to add more checks where we check whether the target is cortex-m. At this point, once the gdb figures out the target is cortex-m4 from the ELF attributes, we then set the tdesc to tdesc_arm_with_m_fpu. 4). No need to describe the single precision FPU registers in XML file because the GDB will handle them as aliases of double precision format. 5). According to M4 Debug architecture, there is a pretty straight way for stub to access FPU registers in single precision format. But there is no direct way to access FPU registers in double precision format. So one more thing for GDB stub is that the stub needs to do more work to construct double precision register from two single precision registers. Is this proposal good enough? Please feel free to comment. And any of them are welcomed. BR, Terry