[applied patch] tweak MIPS sim pref/prefx instructions.

cgd
2002-02-28T07:01:27Z

the intent is obvious. verified that mips64-elf sim still compiles.

chris
===================================================================
2002-02-27 Chris Demetriou <cgd@broadcom.com>

* mips.igen (PREFX): Tweak instruction opcode fields (i.e.,
add a comma) so that it more closely match the MIPS ISA
documentation opcode partitioning.
(PREF): Put useful names on opcode fields, and include
instruction-printing string.

Index: mips.igen
===================================================================
RCS file: /cvs/src/src/sim/mips/mips.igen,v
retrieving revision 1.15
diff -u -r1.15 mips.igen
--- mips.igen 2002/02/28 02:57:34 1.15
+++ mips.igen 2002/02/28 06:57:29
@@ -2083,7 +2083,8 @@
}

-110011,5.RS,nnnnn,16.OFFSET:NORMAL:32::PREF
+110011,5.BASE,5.HINT,16.OFFSET:NORMAL:32::PREF
+"pref <HINT>, <OFFSET>(r )"
*mipsIV:
*mipsV:
*vr5000:
@@ -3974,7 +3975,7 @@
}

-010011,5.BASE,5.INDEX,5.HINT,00000001111:COP1X:32::PREFX
+010011,5.BASE,5.INDEX,5.HINT,00000,001111:COP1X:32::PREFX