From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 6614 invoked by alias); 14 May 2003 23:35:07 -0000 Mailing-List: contact gdb-patches-help@sources.redhat.com; run by ezmlm Precedence: bulk List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sources.redhat.com Received: (qmail 6341 invoked from network); 14 May 2003 23:34:57 -0000 Received: from unknown (HELO mms2.broadcom.com) (63.70.210.59) by sources.redhat.com with SMTP; 14 May 2003 23:34:57 -0000 Received: from 63.70.210.1 by mms2.broadcom.com with ESMTP (Broadcom SMTP Relay (MMS v5.5.2)); Wed, 14 May 2003 16:31:40 -0700 Received: from mail-sj1-5.sj.broadcom.com (mail-sj1-5.sj.broadcom.com [10.16.128.236]) by mon-irva-11.broadcom.com (8.9.1/8.9.1) with ESMTP id QAA11839; Wed, 14 May 2003 16:34:30 -0700 (PDT) Received: from dt-sj3-118.sj.broadcom.com (dt-sj3-118 [10.21.64.118]) by mail-sj1-5.sj.broadcom.com (8.12.9/8.12.9/SSF) with ESMTP id h4ENYnov024183; Wed, 14 May 2003 16:34:49 -0700 (PDT) Received: (from cgd@localhost) by dt-sj3-118.sj.broadcom.com ( 8.9.1/SJ8.9.1) id QAA26412; Wed, 14 May 2003 16:34:48 -0700 (PDT) To: kevinb@redhat.com cc: "Andrew Cagney" , gdb-patches@sources.redhat.com Subject: Re: [WIP/RFC] MIPS registers overhaul References: <1030510002453.ZM3880@localhost.localdomain> <3EBD6131.30209@redhat.com> <1030514220025.ZM10373@localhost.localdomain> From: cgd@broadcom.com Date: Wed, 14 May 2003 23:35:00 -0000 In-Reply-To: kevinb@redhat.com's message of "Wed, 14 May 2003 22:05:11 +0000 (UTC)" Message-ID: MIME-Version: 1.0 X-WSS-ID: 12DC0E56131218-01-01 Content-Type: text/plain Content-Transfer-Encoding: 7bit X-SW-Source: 2003-05/txt/msg00230.txt.bz2 At Wed, 14 May 2003 22:05:11 +0000 (UTC), "Kevin Buettner" wrote: > > ``info registers'' should always display the target's underlying > > register set. In the case of o32 running on a 64 bit ISA, the 64 bit > > registers should be displayed. > > Well, in this case the underlying register set really is only 32-bits > wide. Volume 1 of the MIPS64 Architecture (revision 1.00, dated > August 29, 2002) says: > > For compatibility with MIPS32 processors, the FR bit in the CP0 > Status register is used by a MIPS64 processor to configure the FPU > in a mode in which the FPRs are treated as 32 32-bit registers, > each of which is capable of storing only 32-bit data types. In > this mode, the double-precision floating point (type D) data type > is stored in even-odd pairs of FPRs, and the long-integer (type L) > and paired single (type PS) data types are not supported. > > Figure 2-8 in this manual shows that bits 32-63 (i.e, the high 32 bits) > are "UNPREDICTABLE" in this mode. Indeed. > We still *could* show these extra bits, but displaying the register in > this way would, most of the time, be next to useless. If the GDB user > really wants to see what the higher order bits are, then the raw_fN > names are useful. One possible thing to do is display the upper 32 bits *if* you know that Status:FR is set to 1. The Status:FR value is really the thing that determines how the bits are interpreted. Now, if o32, Status:FR *should* be 0. However, I don't know if for old binaries being debugged o64 will be detected properly (or, heck, even for new binaries 8-), and I also know people who've done Really Special Things with o32 and soft float and using library calls for all FP and using 64-bit floating point. 8-) In other words, the real arbiter of the unpredictability of those bits is Status:FR, so you should probably display them consistently with what it says (if you have Status... I forget 8-). I don't know enough about the remote protocol to know what one would expect from a 64-bit debug agent debugging a 32-bit program (on a 64-bit target). But i could imagine it could become ugly very quickly... 8-) cgd