Index: include/gdb/ChangeLog from Alexandre Oliva 2004-02-13 Michael Snyder * sim-sh.h: Add new sh2a banked registers. Index: include/gdb/sim-sh.h =================================================================== RCS file: /cvs/uberbaum/./include/gdb/sim-sh.h,v retrieving revision 1.2 diff -u -p -r1.2 sim-sh.h --- include/gdb/sim-sh.h 17 Jul 2002 18:43:26 -0000 1.2 +++ include/gdb/sim-sh.h 29 Jul 2004 05:48:50 -0000 @@ -1,5 +1,5 @@ /* This file defines the interface between the sh simulator and gdb. - Copyright (C) 2000, 2002 Free Software Foundation, Inc. + Copyright (C) 2000, 2002, 2004 Free Software Foundation, Inc. This file is part of GDB. @@ -129,8 +129,17 @@ enum SIM_SH_R4_BANK_REGNUM, SIM_SH_R5_BANK_REGNUM, SIM_SH_R6_BANK_REGNUM, - SIM_SH_R7_BANK_REGNUM - /* 100..127: room for expansion. */ + SIM_SH_R7_BANK_REGNUM, + /* 109..127: room for expansion. */ + SIM_SH_TBR_REGNUM, + SIM_SH_IBNR_REGNUM, + SIM_SH_IBCR_REGNUM, + SIM_SH_BANK_REGNUM, + SIM_SH_BANK_MACL_REGNUM, + SIM_SH_BANK_GBR_REGNUM, + SIM_SH_BANK_PR_REGNUM, + SIM_SH_BANK_IVN_REGNUM, + SIM_SH_BANK_MACH_REGNUM }; enum Index: sim/sh/ChangeLog from Alexandre Oliva Introduce SH2a support. 2004-02-13 Michael Snyder * interp.c (sim_fetch_register, sim_store_register): Revert overloading of tbr and ibnr onto ssr and spc. Implement proper handling of tbr and bank registers. 2004-02-12 Michael Snyder * gencode.c, interp.c: Revert the splitting of the jump table into two pieces. Instead, change it from char to short. 2004-02-11 Michael Snyder * gencode.c (op tab): Implement ldbank, stbank, and resbank. * interp.c (saved_state): Add ibnr and ibcr. Move bfd_mach to end of struct. Add regstack pointer. (IBNR, IBCR, BANKN, ME, SET_BANKN, SET_ME): New macros. (init_dsp): Allocate space for 512 register banks. (sim_store_register, sim_fetch_register): For now, overload tbr and ibnr onto ssr and spc. (trap): For now, use trap #13 and trap #14 to set ibnr and ibcr. 2004-02-05 Michael Snyder * gencode.c (op tab): Implement rtv/n, mulr, divs, and divu. 2004-01-30 Michael Snyder * gencode.c (op tab): Implement clips, clipu. * interp.c (union saved_state_type): Add BO, CS. 2004-01-29 Michael Snyder * gencode.c (op tab): Implement movmu, movml. (gensim_caselist): Add tokens for r15 and multiple regs. 2004-01-27 Michael Snyder * gencode.c (op tab): Implement nott, movrt, movu, long versions of mov. Add mov.l @-,R0. (gensim_caselist): Add defaults to switch statements. * interp.c (do_long_move_insn): New function. 2004-01-21 Michael Snyder * gencode.c (op tab): Implement movi20 and movi20s. Implement mov.b and mov.w with disp12. 2004-01-20 Michael Snyder * gencode.c (op tab): Implement mov.l with 12-bit displacement. 2004-01-16 Michael Snyder * gencode.c (op tab): Implement fmov.[sd] with 12-bit displacement. * gencode.c (op tab): Implement bset/bclr. 2004-01-15 Michael Snyder * gencode.c (op tab): Implement bit manipulation insns. Implement jsr/n. Turn on implementations of remaining 16-bit sh2a insns. * interp.c (do_blog_insn): Implement binary logic insns. 2004-01-14 Michael Snyder * gencode.c (conflict_warn, warn_conflicts): Temporary debugging. 2004-01-13 Michael Snyder * gencode.c: Move movx/movy insns into separate switch statement (thereby freeing space in the 8-bit opcode table). (filltable): Make index auto instead of static. (gensim_caselist): Generate default case here instead of in caller. (gensim): Generate two separate switch statements. Call gensim_caselist once for each (for movsxy_tab and for tab). * interp.c (init_dsp): Don't swap contents of sh_dsp_table any more. Instead use it directly in its own switch statement. 2004-01-09 Michael Snyder * interp.c (sim_load): Save the bfd machine code. (sim_create_inferior): Ditto. * gencode.c (op tab): If machine == sh2a, reject instructions that are disabled on that chip. * interp.c (union saved_state_type): Add tbr register. * gencode.c (op tab): Add some new sh2a insns. Index: sim/sh/gencode.c =================================================================== RCS file: /cvs/uberbaum/./sim/sh/gencode.c,v retrieving revision 1.28 diff -u -p -r1.28 gencode.c --- sim/sh/gencode.c 13 Feb 2004 00:01:19 -0000 1.28 +++ sim/sh/gencode.c 29 Jul 2004 05:48:52 -0000 @@ -98,6 +98,18 @@ op tab[] = "}", }, + { "", "n", "bit32 #imm3,@(disp12,)", "0011nnnni8*11001", + "/* 32-bit logical bit-manipulation instructions. */", + "int word2 = RIAT (nip);", + "i >>= 4; /* BOGUS: Using only three bits of 'i'. */", + "/* MSB of 'i' must be zero. */", + "if (i > 7)", + " RAISE_EXCEPTION (SIGILL);", + "MA (1);", + "do_blog_insn (1 << i, (word2 & 0xfff) + R[n], ", + " (word2 >> 12) & 0xf, memory, maskb);", + "SET_NIP (nip + 2); /* Consume 2 more bytes. */", + }, { "", "", "bra ", "1010i12.........", "SET_NIP (PC + 4 + (SEXT12 (i) * 2));", "cycles += 2;", @@ -131,6 +143,175 @@ op tab[] = "}", }, + { "", "m", "bld/st #, ", "10000111mmmmi4*1", + "/* MSB of 'i' is true for load, false for store. */", + "if (i <= 7)", + " if (T)", + " R[m] |= (1 << i);", + " else", + " R[m] &= ~(1 << i);", + "else", + " SET_SR_T ((R[m] & (1 << (i - 8))) != 0);", + }, + { "m", "m", "bset/clr #, ", "10000110mmmmi4*1", + "/* MSB of 'i' is true for set, false for clear. */", + "if (i <= 7)", + " R[m] &= ~(1 << i);", + "else", + " R[m] |= (1 << (i - 8));", + }, + { "n", "n", "clips.b ", "0100nnnn10010001", + "if (R[n] < -128 || R[n] > 127) {", + " L (n);", + " SET_SR_CS (1);", + " if (R[n] > 127)", + " R[n] = 127;", + " else if (R[n] < -128)", + " R[n] = -128;", + "}", + }, + { "n", "n", "clips.w ", "0100nnnn10010101", + "if (R[n] < -32768 || R[n] > 32767) {", + " L (n);", + " SET_SR_CS (1);", + " if (R[n] > 32767)", + " R[n] = 32767;", + " else if (R[n] < -32768)", + " R[n] = -32768;", + "}", + }, + { "n", "n", "clipu.b ", "0100nnnn10000001", + "if (R[n] < -256 || R[n] > 255) {", + " L (n);", + " SET_SR_CS (1);", + " R[n] = 255;", + "}", + }, + { "n", "n", "clipu.w ", "0100nnnn10000101", + "if (R[n] < -65536 || R[n] > 65535) {", + " L (n);", + " SET_SR_CS (1);", + " R[n] = 65535;", + "}", + }, + { "n", "0n", "divs R0,", "0100nnnn10010100", + "if (R0 == 0)", + " R[n] = 0x7fffffff;", + "else if (R0 == -1 && R[n] == 0x80000000)", + " R[n] = 0x7fffffff;", + "else R[n] /= R0;", + "L (n);", + }, + { "n", "0n", "divu R0,", "0100nnnn10000100", + "if (R0 == 0)", + " R[n] = 0xffffffff;", + "else (unsigned int) R[n] = (unsigned int) R[n] / (unsigned int) R0;", + "L (n);", + }, + { "n", "0n", "mulr R0,", "0100nnnn10000000", + "R[n] = (R[n] * R0) & 0xffffffff;", + "L (n);", + }, + { "0", "n", "ldbank @,R0", "0100nnnn11100101", + "int regn = (R[n] >> 2) & 0x1f;", + "int bankn = (R[n] >> 7) & 0x1ff;", + "if (regn > 19)", + " regn = 19; /* FIXME what should happen? */", + "R0 = saved_state.asregs.regstack[bankn].regs[regn];", + "L (0);", + }, + { "", "0n", "stbank R0,@", "0100nnnn11100001", + "int regn = (R[n] >> 2) & 0x1f;", + "int bankn = (R[n] >> 7) & 0x1ff;", + "if (regn > 19)", + " regn = 19; /* FIXME what should happen? */", + "saved_state.asregs.regstack[bankn].regs[regn] = R0;", + }, + { "", "", "resbank", "0000000001011011", + /* FIXME: cdef all */ + "int i;", + "if (BO) { /* Bank Overflow */", + /* FIXME: how do we know when to reset BO? */ + " for (i = 0; i <= 14; i++) {", + " R[i] = RLAT (R[15]);", + " MA (1);", + " R[15] += 4;", + " }", + " PR = RLAT (R[15]);", + " R[15] += 4;", + " MA (1);", + " GBR = RLAT (R[15]);", + " R[15] += 4;", + " MA (1);", + " MACH = RLAT (R[15]);", + " R[15] += 4;", + " MA (1);", + " MACL = RLAT (R[15]);", + " R[15] += 4;", + " MA (1);", + "}", + "else if (BANKN == 0) /* Bank Underflow */", + " RAISE_EXCEPTION (SIGILL);", /* FIXME: what exception? */ + "else {", + " SET_BANKN (BANKN - 1);", + " for (i = 0; i <= 14; i++)", + " R[i] = saved_state.asregs.regstack[BANKN].regs[i];", + " MACH = saved_state.asregs.regstack[BANKN].regs[15];", + " PR = saved_state.asregs.regstack[BANKN].regs[17];", + " GBR = saved_state.asregs.regstack[BANKN].regs[18];", + " MACL = saved_state.asregs.regstack[BANKN].regs[19];", + "}", + }, + { "f", "f-", "movml.l ,@-R15", "0100nnnn11110001", + "/* Push Rn...R0 (if n==15, push pr and R14...R0). */", + "do {", + " MA (1);", + " R[15] -= 4;", + " if (n == 15)", + " WLAT (R[15], PR);", + " else", + " WLAT (R[15], R[n]);", + "} while (n-- > 0);", + }, + { "f", "f+", "movml.l @R15+,", "0100nnnn11110101", + "/* Pop R0...Rn (if n==15, pop R0...R14 and pr). */", + "int i = 0;\n", + "do {", + " MA (1);", + " if (i == 15)", + " PR = RLAT (R[15]);", + " else", + " R[i] = RLAT (R[15]);", + " R[15] += 4;", + "} while (i++ < n);", + }, + { "f", "f-", "movmu.l ,@-R15", "0100nnnn11110000", + "/* Push pr, R14...Rn (if n==15, push pr). */", /* FIXME */ + "int i = 15;\n", + "do {", + " MA (1);", + " R[15] -= 4;", + " if (i == 15)", + " WLAT (R[15], PR);", + " else", + " WLAT (R[15], R[i]);", + "} while (i-- > n);", + }, + { "f", "f+", "movmu.l @R15+,", "0100nnnn11110100", + "/* Pop Rn...R14, pr (if n==15, pop pr). */", /* FIXME */ + "do {", + " MA (1);", + " if (n == 15)", + " PR = RLAT (R[15]);", + " else", + " R[n] = RLAT (R[15]);", + " R[15] += 4;", + "} while (n++ < 15);", + }, + { "", "", "nott", "0000000001101000", + "SET_SR_T (T == 0);", + }, + { "", "", "bt.s ", "10001101i8p1....", "if (T) {", " SET_NIP (PC + 4 + (SEXT (i) * 2));", @@ -297,6 +478,8 @@ op tab[] = "else", "{", " double fsum = 0;", + " if (saved_state.asregs.bfd_mach == bfd_mach_sh2a)", + " RAISE_EXCEPTION (SIGILL);", " /* FIXME: check for nans and infinities. */", " fsum += FR (v1+0) * FR (v2+0);", " fsum += FR (v1+1) * FR (v2+1);", @@ -386,6 +569,17 @@ op tab[] = " SET_FI (n, RLAT (R[m]));", "}", }, + /* sh2a */ + { "", "n", "fmov.s @(disp12,), ", "0011nnnnmmmm0001", + "/* and fmov.s , @(disp12,)", + " and mov.bwl , @(disp12,)", + " and mov.bwl @(disp12,),", + " and movu.bw @(disp12,),. */", + "int word2 = RIAT (nip);", + "SET_NIP (nip + 2); /* Consume 2 more bytes. */", + "MA (1);", + "do_long_move_insn (word2 & 0xf000, word2 & 0x0fff, m, n, &thislock);", + }, /* sh2e */ { "m", "m", "fmov.s @+,", "1111nnnnmmmm1001", /* sh4 */ @@ -465,6 +659,8 @@ op tab[] = { "", "", "frchg", "1111101111111101", "if (FPSCR_PR)", " RAISE_EXCEPTION (SIGILL);", + "else if (saved_state.asregs.bfd_mach == bfd_mach_sh2a)", + " RAISE_EXCEPTION (SIGILL);", "else", " SET_FPSCR (GET_FPSCR () ^ FPSCR_MASK_FR);", }, @@ -473,6 +669,8 @@ op tab[] = { "", "", "fsca", "1111eeee11111101", "if (FPSCR_PR)", " RAISE_EXCEPTION (SIGILL);", + "else if (saved_state.asregs.bfd_mach == bfd_mach_sh2a)", + " RAISE_EXCEPTION (SIGILL);", "else", " {", " SET_FR (n, fsca_s (FPUL, &sin));", @@ -494,6 +692,8 @@ op tab[] = { "", "", "fsrra ", "1111nnnn01111101", "if (FPSCR_PR)", " RAISE_EXCEPTION (SIGILL);", + "else if (saved_state.asregs.bfd_mach == bfd_mach_sh2a)", + " RAISE_EXCEPTION (SIGILL);", "else", " SET_FR (n, fsrra_s (FR (n)));", }, @@ -525,6 +725,8 @@ op tab[] = " RAISE_EXCEPTION (SIGILL);", "else", "{", + " if (saved_state.asregs.bfd_mach == bfd_mach_sh2a)", + " RAISE_EXCEPTION (SIGILL);", " /* FIXME not implemented. */", " printf (\"ftrv xmtrx, FV%d\\n\", v1);", "}", @@ -555,6 +757,18 @@ op tab[] = "cycles += 2;", "Delay_Slot (PC + 2);", }, + { "", "n", "jsr/n @", "0100nnnn01001011", + "PR = PH2T (PC + 2);", + "if (~doprofile)", + " gotcall (PR, R[n]);", + "SET_NIP (PT2H (R[n]));", + }, + { "", "", "jsr/n @@(,TBR)", "10000011i8p4....", + "PR = PH2T (PC + 2);", + "if (~doprofile)", + " gotcall (PR, i + TBR);", + "SET_NIP (PT2H (i + TBR));", + }, { "", "n", "ldc ,", "0100nnnnmmmm1110", "CREG (m) = R[n];", @@ -579,6 +793,12 @@ op tab[] = "else", " RAISE_EXCEPTION (SIGILL); /* user mode */", }, + { "", "n", "ldc ,TBR", "0100nnnn01001010", + "if (SR_MD)", /* FIXME? */ + " TBR = R[n]; /* priv mode */", + "else", + " RAISE_EXCEPTION (SIGILL); /* user mode */", + }, { "n", "n", "ldc.l @+,", "0100nnnnmmmm0111", "MA (1);", "CREG (m) = RLAT (R[n]);", @@ -673,6 +893,14 @@ op tab[] = { "n", "", "mov #,", "1110nnnni8*1....", "R[n] = SEXT (i);", }, + { "n", "", "movi20 #,", "0000nnnni8*10000", + "R[n] = ((i << 24) >> 12) | RIAT (nip);", + "SET_NIP (nip + 2); /* Consume 2 more bytes. */", + }, + { "n", "", "movi20s #,", "0000nnnni8*10001", + "R[n] = ((((i & 0xf0) << 24) >> 12) | RIAT (nip)) << 8;", + "SET_NIP (nip + 2); /* Consume 2 more bytes. */", + }, { "n", "m", "mov ,", "0110nnnnmmmm0011", "R[n] = R[m];", }, @@ -698,6 +926,12 @@ op tab[] = "R[m] += 1;", "L (n);", }, + { "0n", "n", "mov.b @-,R0", "0100nnnn11001011", + "MA (1);", + "R[n] -= 1;", + "R0 = RSBAT (R[n]);", + "L (0);", + }, { "", "mn", "mov.b ,@", "0010nnnnmmmm0000", "MA (1);", "WBAT (R[n], R[m]);", @@ -719,6 +953,11 @@ op tab[] = "R[n] -= 1;", "WBAT (R[n], R[m]);", }, + { "n", "n0", "mov.b R0,@+", "0100nnnn10001011", + "MA (1);", + "WBAT (R[n], R0);", + "R[n] += 1;", + }, { "n", "m", "mov.b @,", "0110nnnnmmmm0000", "MA (1);", "R[n] = RSBAT (R[m]);", @@ -751,6 +990,12 @@ op tab[] = "R[m] += 4;", "L (n);", }, + { "0n", "n", "mov.l @-,R0", "0100nnnn11101011", + "MA (1);", + "R[n] -= 4;", + "R0 = RLAT (R[n]);", + "L (0);", + }, { "n", "m", "mov.l @,", "0110nnnnmmmm0010", "MA (1);", "R[n] = RLAT (R[m]);", @@ -773,6 +1018,11 @@ op tab[] = "R[n] -= 4;", "WLAT (R[n], R[m]);", }, + { "n", "n0", "mov.l R0,@+", "0100nnnn10101011", + "MA (1) ;", + "WLAT (R[n], R0);", + "R[n] += 4;", + }, { "", "nm", "mov.l ,@", "0010nnnnmmmm0010", "MA (1);", "WLAT (R[n], R[m]);", @@ -804,6 +1054,12 @@ op tab[] = "R[m] += 2;", "L (n);", }, + { "0n", "n", "mov.w @-,R0", "0100nnnn11011011", + "MA (1);", + "R[n] -= 2;", + "R0 = RSWAT (R[n]);", + "L (0);", + }, { "n", "m", "mov.w @,", "0110nnnnmmmm0001", "MA (1);", "R[n] = RSWAT (R[m]);", @@ -826,6 +1082,11 @@ op tab[] = "R[n] -= 2;", "WWAT (R[n], R[m]);", }, + { "n", "0n", "mov.w R0,@+", "0100nnnn10011011", + "MA (1);", + "WWAT (R[n], R0);", + "R[n] += 2;", + }, { "", "nm", "mov.w ,@", "0010nnnnmmmm0001", "MA (1);", "WWAT (R[n], R[m]);", @@ -864,6 +1125,10 @@ op tab[] = "R[n] = T;", }, + { "", "", "movrt ", "0000nnnn00111001", + "R[n] = (T == 0);", + }, + { "0", "n", "movua.l @,R0", "0100nnnn10101001", "int regn = R[n];", "MA (1);", @@ -1014,6 +1279,14 @@ op tab[] = "cycles += 2;", "Delay_Slot (PC + 2);", }, + { "", "", "rts/n", "0000000001101011", + "SET_NIP (PT2H (PR));", + }, + { "0", "n", "rtv/n ", "0000nnnn01111011", + "R0 = R[n];", + "L (0);", + "SET_NIP (PT2H (PR));", + }, /* sh4a */ { "", "", "setdmx", "0000000010011000", @@ -1121,6 +1394,12 @@ op tab[] = "else", " RAISE_EXCEPTION (SIGILL); /* user mode */", }, + { "n", "", "stc TBR,", "0000nnnn01001010", + "if (SR_MD)", /* FIXME? */ + " R[n] = TBR; /* priv mode */", + "else", + " RAISE_EXCEPTION (SIGILL); /* user mode */", + }, { "n", "n", "stc.l ,@-", "0100nnnnmmmm0011", "MA (1);", "R[n] -= 4;", @@ -2267,6 +2546,58 @@ gengastab () static unsigned short table[1 << 16]; +static int warn_conflicts = 0; + +static void +conflict_warn (val, i) + int val; + int i; +{ + int ix, key; + int j = table[val]; + + fprintf (stderr, "Warning: opcode table conflict: 0x%04x (idx %d && %d)\n", + val, i, table[val]); + + for (ix = sizeof (tab) / sizeof (tab[0]); ix >= 0; ix--) + if (tab[ix].index == i || tab[ix].index == j) + { + key = ((tab[ix].code[0] - '0') << 3) + + ((tab[ix].code[1] - '0') << 2) + + ((tab[ix].code[2] - '0') << 1) + + ((tab[ix].code[3] - '0')); + + if (val >> 12 == key) + fprintf (stderr, " %s -- %s\n", tab[ix].code, tab[ix].name); + } + + for (ix = sizeof (movsxy_tab) / sizeof (movsxy_tab[0]); ix >= 0; ix--) + if (movsxy_tab[ix].index == i || movsxy_tab[ix].index == j) + { + key = ((movsxy_tab[ix].code[0] - '0') << 3) + + ((movsxy_tab[ix].code[1] - '0') << 2) + + ((movsxy_tab[ix].code[2] - '0') << 1) + + ((movsxy_tab[ix].code[3] - '0')); + + if (val >> 12 == key) + fprintf (stderr, " %s -- %s\n", + movsxy_tab[ix].code, movsxy_tab[ix].name); + } + + for (ix = sizeof (ppi_tab) / sizeof (ppi_tab[0]); ix >= 0; ix--) + if (ppi_tab[ix].index == i || ppi_tab[ix].index == j) + { + key = ((ppi_tab[ix].code[0] - '0') << 3) + + ((ppi_tab[ix].code[1] - '0') << 2) + + ((ppi_tab[ix].code[2] - '0') << 1) + + ((ppi_tab[ix].code[3] - '0')); + + if (val >> 12 == key) + fprintf (stderr, " %s -- %s\n", + ppi_tab[ix].code, ppi_tab[ix].name); + } +} + /* Take an opcode, expand all varying fields in it out and fill all the right entries in 'table' with the opcode index. */ @@ -2278,6 +2609,8 @@ expand_opcode (val, i, s) { if (*s == 0) { + if (warn_conflicts && table[val] != 0) + conflict_warn (val, i); table[val] = i; } else @@ -2599,6 +2932,12 @@ gensim_caselist (p) switch (s[1]) { + default: + fprintf (stderr, + "gensim_caselist: Unknown char '%c' in %s\n", + s[1], s); + exit (1); + break; case '4': printf ("f"); break; @@ -2615,6 +2954,14 @@ gensim_caselist (p) switch (s[3]) { + default: + fprintf (stderr, + "gensim_caselist: Unknown char '%c' in %s\n", + s[3], s); + exit (1); + break; + case '.': /* eg. "i12." */ + break; case '1': break; case '2': @@ -2646,6 +2993,25 @@ gensim_caselist (p) char *r; for (r = p->refs; *r; r++) { + if (*r == 'f') printf (" CREF (15);\n"); + if (*r == '-') + { + printf (" {\n"); + printf (" int i = n;\n"); + printf (" do {\n"); + printf (" CREF (i);\n"); + printf (" } while (i-- > 0);\n"); + printf (" }\n"); + } + if (*r == '+') + { + printf (" {\n"); + printf (" int i = n;\n"); + printf (" do {\n"); + printf (" CREF (i);\n"); + printf (" } while (i++ < 14);\n"); + printf (" }\n"); + } if (*r == '0') printf (" CREF (0);\n"); if (*r == '8') printf (" CREF (8);\n"); if (*r == '9') printf (" CREF (9);\n"); @@ -2669,6 +3035,25 @@ gensim_caselist (p) char *r; for (r = p->defs; *r; r++) { + if (*r == 'f') printf (" CDEF (15);\n"); + if (*r == '-') + { + printf (" {\n"); + printf (" int i = n;\n"); + printf (" do {\n"); + printf (" CDEF (i);\n"); + printf (" } while (i-- > 0);\n"); + printf (" }\n"); + } + if (*r == '+') + { + printf (" {\n"); + printf (" int i = n;\n"); + printf (" do {\n"); + printf (" CDEF (i);\n"); + printf (" } while (i++ < 14);\n"); + printf (" }\n"); + } if (*r == '0') printf(" CDEF (0);\n"); if (*r == 'n') printf(" CDEF (n);\n"); if (*r == 'm') printf(" CDEF (m);\n"); @@ -2757,6 +3142,9 @@ expand_ppi_code (val, i, s) break; case 'g': case 'z': + if (warn_conflicts && table[val] != 0) + conflict_warn (val, i); + /* The last four bits are disregarded for the switch table. */ table[val] = i; return; @@ -2992,6 +3380,10 @@ main (ac, av) /* Now generate the requested data. */ if (ac > 1) { + if (ac > 2 && strcmp (av[2], "-w") == 0) + { + warn_conflicts = 1; + } if (strcmp (av[1], "-t") == 0) { gengastab (); Index: sim/sh/interp.c =================================================================== RCS file: /cvs/uberbaum/./sim/sh/interp.c,v retrieving revision 1.15 diff -u -p -r1.15 interp.c --- sim/sh/interp.c 12 Feb 2004 19:32:12 -0000 1.15 +++ sim/sh/interp.c 29 Jul 2004 05:48:54 -0000 @@ -65,6 +65,11 @@ int sim_write (SIM_DESC sd, SIM_ADDR add for a quit. */ #define POLL_QUIT_INTERVAL 0x60000 +typedef struct +{ + int regs[20]; +} regstacktype; + typedef union { @@ -123,6 +128,9 @@ typedef union int dbr; /* debug base register */ int sgr; /* saved gr15 */ int ldst; /* load/store flag (boolean) */ + int tbr; + int ibcr; /* sh2a bank control register */ + int ibnr; /* sh2a bank number register */ } named; int i[16]; } cregs; @@ -152,6 +160,8 @@ typedef union unsigned char *ymem; unsigned char *xmem_offset; unsigned char *ymem_offset; + unsigned long bfd_mach; + regstacktype *regstack; } asregs; int asints[40]; @@ -191,6 +201,11 @@ static char *myname; #define GBR saved_state.asregs.cregs.named.gbr #define VBR saved_state.asregs.cregs.named.vbr #define DBR saved_state.asregs.cregs.named.dbr +#define TBR saved_state.asregs.cregs.named.tbr +#define IBCR saved_state.asregs.cregs.named.ibcr +#define IBNR saved_state.asregs.cregs.named.ibnr +#define BANKN (saved_state.asregs.cregs.named.ibnr & 0x1ff) +#define ME ((saved_state.asregs.cregs.named.ibnr >> 14) & 0x3) #define SSR saved_state.asregs.cregs.named.ssr #define SPC saved_state.asregs.cregs.named.spc #define SGR saved_state.asregs.cregs.named.sgr @@ -213,6 +228,8 @@ static char *myname; /* Manipulate SR */ +#define SR_MASK_BO (1 << 14) +#define SR_MASK_CS (1 << 13) #define SR_MASK_DMY (1 << 11) #define SR_MASK_DMX (1 << 10) #define SR_MASK_M (1 << 9) @@ -227,6 +244,8 @@ static char *myname; #define SR_MASK_RC 0x0fff0000 #define SR_RC_INCREMENT -0x00010000 +#define BO ((saved_state.asregs.cregs.named.sr & SR_MASK_BO) != 0) +#define CS ((saved_state.asregs.cregs.named.sr & SR_MASK_CS) != 0) #define M ((saved_state.asregs.cregs.named.sr & SR_MASK_M) != 0) #define Q ((saved_state.asregs.cregs.named.sr & SR_MASK_Q) != 0) #define S ((saved_state.asregs.cregs.named.sr & SR_MASK_S) != 0) @@ -249,6 +268,16 @@ do { \ saved_state.asregs.cregs.named.sr &= ~(BIT); \ } while (0) +#define SET_SR_BO(EXP) SET_SR_BIT ((EXP), SR_MASK_BO) +#define SET_SR_CS(EXP) SET_SR_BIT ((EXP), SR_MASK_CS) +#define SET_BANKN(EXP) \ +do { \ + IBNR = (IBNR & 0xfe00) | (EXP & 0x1f); \ +} while (0) +#define SET_ME(EXP) \ +do { \ + IBNR = (IBNR & 0x3fff) | ((EXP & 0x3) << 14); \ +} while (0) #define SET_SR_M(EXP) SET_SR_BIT ((EXP), SR_MASK_M) #define SET_SR_Q(EXP) SET_SR_BIT ((EXP), SR_MASK_Q) #define SET_SR_S(EXP) SET_SR_BIT ((EXP), SR_MASK_S) @@ -1181,6 +1210,12 @@ trap (i, regs, insn_ptr, memory, maskl, } break; + case 13: /* Set IBNR */ + IBNR = regs[0] & 0xffff; + break; + case 14: /* Set IBCR */ + IBCR = regs[0] & 0xffff; + break; case 0xc3: case 255: raise_exception (SIGTRAP); @@ -1445,6 +1480,140 @@ get_loop_bounds_ext (rs, re, memory, mem return loop; } +enum { + B_BCLR = 0, + B_BSET = 1, + B_BST = 2, + B_BLD = 3, + B_BAND = 4, + B_BOR = 5, + B_BXOR = 6, + B_BLDNOT = 11, + B_BANDNOT = 12, + B_BORNOT = 13, + + MOVB_RM = 0x0000, + MOVW_RM = 0x1000, + MOVL_RM = 0x2000, + FMOV_RM = 0x3000, + MOVB_MR = 0x4000, + MOVW_MR = 0x5000, + MOVL_MR = 0x6000, + FMOV_MR = 0x7000, + MOVU_BMR = 0x8000, + MOVU_WMR = 0x9000, +}; + +/* Do extended displacement move instructions. */ +void +do_long_move_insn (int op, int disp12, int m, int n, int *thatlock) +{ + int memstalls = 0; + int thislock = *thatlock; + int endianw = global_endianw; + int *R = &(saved_state.asregs.regs[0]); + unsigned char *memory = saved_state.asregs.memory; + int maskb = ~((saved_state.asregs.msize - 1) & ~0); + unsigned char *insn_ptr = PT2H (saved_state.asregs.pc); + + switch (op) { + case MOVB_RM: /* signed */ + WBAT (disp12 * 1 + R[n], R[m]); + break; + case MOVW_RM: + WWAT (disp12 * 2 + R[n], R[m]); + break; + case MOVL_RM: + WLAT (disp12 * 4 + R[n], R[m]); + break; + case FMOV_RM: /* floating point */ + if (FPSCR_SZ) + { + MA (1); + WDAT (R[n] + 8 * disp12, m); + } + else + WLAT (R[n] + 4 * disp12, FI (m)); + break; + case MOVB_MR: + R[n] = RSBAT (disp12 * 1 + R[m]); + L (n); + break; + case MOVW_MR: + R[n] = RSWAT (disp12 * 2 + R[m]); + L (n); + break; + case MOVL_MR: + R[n] = RLAT (disp12 * 4 + R[m]); + L (n); + break; + case FMOV_MR: + if (FPSCR_SZ) { + MA (1); + RDAT (R[m] + 8 * disp12, n); + } + else + SET_FI (n, RLAT (R[m] + 4 * disp12)); + break; + case MOVU_BMR: /* unsigned */ + R[n] = RBAT (disp12 * 1 + R[m]); + L (n); + break; + case MOVU_WMR: + R[n] = RWAT (disp12 * 2 + R[m]); + L (n); + break; + default: + RAISE_EXCEPTION (SIGINT); + exit (1); + } + saved_state.asregs.memstalls += memstalls; + *thatlock = thislock; +} + +/* Do binary logical bit-manipulation insns. */ +void +do_blog_insn (int imm, int addr, int binop, + unsigned char *memory, int maskb) +{ + int oldval = RBAT (addr); + + switch (binop) { + case B_BCLR: /* bclr.b */ + WBAT (addr, oldval & ~imm); + break; + case B_BSET: /* bset.b */ + WBAT (addr, oldval | imm); + break; + case B_BST: /* bst.b */ + if (T) + WBAT (addr, oldval | imm); + else + WBAT (addr, oldval & ~imm); + break; + case B_BLD: /* bld.b */ + SET_SR_T ((oldval & imm) != 0); + break; + case B_BAND: /* band.b */ + SET_SR_T (T && ((oldval & imm) != 0)); + break; + case B_BOR: /* bor.b */ + SET_SR_T (T || ((oldval & imm) != 0)); + break; + case B_BXOR: /* bxor.b */ + SET_SR_T (T ^ ((oldval & imm) != 0)); + break; + case B_BLDNOT: /* bldnot.b */ + SET_SR_T ((oldval & imm) == 0); + break; + case B_BANDNOT: /* bandnot.b */ + SET_SR_T (T && ((oldval & imm) == 0)); + break; + case B_BORNOT: /* bornot.b */ + SET_SR_T (T || ((oldval & imm) == 0)); + break; + } +} float fsca_s (int in, double (*f) (double)) { @@ -1642,6 +1811,10 @@ init_dsp (abfd) saved_state.asregs.yram_start = 1; } + if (saved_state.asregs.regstack == NULL) + saved_state.asregs.regstack = + calloc (512, sizeof *saved_state.asregs.regstack); + if (target_dsp != was_dsp) { int i, tmp; @@ -1741,7 +1914,7 @@ sim_resume (sd, step, siggnal) register int memstalls = 0; register int insts = 0; register int prevlock; - register int thislock; + int thislock; register unsigned int doprofile; register int pollcount = 0; /* endianw is used for every insn fetch, hence it makes sense to cache it. @@ -1940,6 +2113,15 @@ sim_read (sd, addr, buffer, size) return size; } +static int gdb_bank_number; +enum { + REGBANK_MACH = 15, + REGBANK_IVN = 16, + REGBANK_PR = 17, + REGBANK_GBR = 18, + REGBANK_MACL = 19 +}; + int sim_store_register (sd, rn, memory, length) SIM_DESC sd; @@ -2050,6 +2232,12 @@ sim_store_register (sd, rn, memory, leng case SIM_SH_R2_BANK0_REGNUM: case SIM_SH_R3_BANK0_REGNUM: case SIM_SH_R4_BANK0_REGNUM: case SIM_SH_R5_BANK0_REGNUM: case SIM_SH_R6_BANK0_REGNUM: case SIM_SH_R7_BANK0_REGNUM: + if (saved_state.asregs.bfd_mach == bfd_mach_sh2a) + { + rn -= SIM_SH_R0_BANK0_REGNUM; + saved_state.asregs.regstack[gdb_bank_number].regs[rn] = val; + } + else if (SR_MD && SR_RB) Rn_BANK (rn - SIM_SH_R0_BANK0_REGNUM) = val; else @@ -2059,6 +2247,12 @@ sim_store_register (sd, rn, memory, leng case SIM_SH_R2_BANK1_REGNUM: case SIM_SH_R3_BANK1_REGNUM: case SIM_SH_R4_BANK1_REGNUM: case SIM_SH_R5_BANK1_REGNUM: case SIM_SH_R6_BANK1_REGNUM: case SIM_SH_R7_BANK1_REGNUM: + if (saved_state.asregs.bfd_mach == bfd_mach_sh2a) + { + rn -= SIM_SH_R0_BANK1_REGNUM; + saved_state.asregs.regstack[gdb_bank_number].regs[rn + 8] = val; + } + else if (SR_MD && SR_RB) saved_state.asregs.regs[rn - SIM_SH_R0_BANK1_REGNUM] = val; else @@ -2070,6 +2264,35 @@ sim_store_register (sd, rn, memory, leng case SIM_SH_R6_BANK_REGNUM: case SIM_SH_R7_BANK_REGNUM: SET_Rn_BANK (rn - SIM_SH_R0_BANK_REGNUM, val); break; + case SIM_SH_TBR_REGNUM: + TBR = val; + break; + case SIM_SH_IBNR_REGNUM: + IBNR = val; + break; + case SIM_SH_IBCR_REGNUM: + IBCR = val; + break; + case SIM_SH_BANK_REGNUM: + /* This is a pseudo-register maintained just for gdb. + It tells us what register bank gdb would like to read/write. */ + gdb_bank_number = val; + break; + case SIM_SH_BANK_MACL_REGNUM: + saved_state.asregs.regstack[gdb_bank_number].regs[REGBANK_MACL] = val; + break; + case SIM_SH_BANK_GBR_REGNUM: + saved_state.asregs.regstack[gdb_bank_number].regs[REGBANK_GBR] = val; + break; + case SIM_SH_BANK_PR_REGNUM: + saved_state.asregs.regstack[gdb_bank_number].regs[REGBANK_PR] = val; + break; + case SIM_SH_BANK_IVN_REGNUM: + saved_state.asregs.regstack[gdb_bank_number].regs[REGBANK_IVN] = val; + break; + case SIM_SH_BANK_MACH_REGNUM: + saved_state.asregs.regstack[gdb_bank_number].regs[REGBANK_MACH] = val; + break; default: return 0; } @@ -2185,6 +2408,12 @@ sim_fetch_register (sd, rn, memory, leng case SIM_SH_R2_BANK0_REGNUM: case SIM_SH_R3_BANK0_REGNUM: case SIM_SH_R4_BANK0_REGNUM: case SIM_SH_R5_BANK0_REGNUM: case SIM_SH_R6_BANK0_REGNUM: case SIM_SH_R7_BANK0_REGNUM: + if (saved_state.asregs.bfd_mach == bfd_mach_sh2a) + { + rn -= SIM_SH_R0_BANK0_REGNUM; + val = saved_state.asregs.regstack[gdb_bank_number].regs[rn]; + } + else val = (SR_MD && SR_RB ? Rn_BANK (rn - SIM_SH_R0_BANK0_REGNUM) : saved_state.asregs.regs[rn - SIM_SH_R0_BANK0_REGNUM]); @@ -2193,6 +2422,12 @@ sim_fetch_register (sd, rn, memory, leng case SIM_SH_R2_BANK1_REGNUM: case SIM_SH_R3_BANK1_REGNUM: case SIM_SH_R4_BANK1_REGNUM: case SIM_SH_R5_BANK1_REGNUM: case SIM_SH_R6_BANK1_REGNUM: case SIM_SH_R7_BANK1_REGNUM: + if (saved_state.asregs.bfd_mach == bfd_mach_sh2a) + { + rn -= SIM_SH_R0_BANK1_REGNUM; + val = saved_state.asregs.regstack[gdb_bank_number].regs[rn + 8]; + } + else val = (! SR_MD || ! SR_RB ? Rn_BANK (rn - SIM_SH_R0_BANK1_REGNUM) : saved_state.asregs.regs[rn - SIM_SH_R0_BANK1_REGNUM]); @@ -2203,6 +2438,35 @@ sim_fetch_register (sd, rn, memory, leng case SIM_SH_R6_BANK_REGNUM: case SIM_SH_R7_BANK_REGNUM: val = Rn_BANK (rn - SIM_SH_R0_BANK_REGNUM); break; + case SIM_SH_TBR_REGNUM: + val = TBR; + break; + case SIM_SH_IBNR_REGNUM: + val = IBNR; + break; + case SIM_SH_IBCR_REGNUM: + val = IBCR; + break; + case SIM_SH_BANK_REGNUM: + /* This is a pseudo-register maintained just for gdb. + It tells us what register bank gdb would like to read/write. */ + val = gdb_bank_number; + break; + case SIM_SH_BANK_MACL_REGNUM: + val = saved_state.asregs.regstack[gdb_bank_number].regs[REGBANK_MACL]; + break; + case SIM_SH_BANK_GBR_REGNUM: + val = saved_state.asregs.regstack[gdb_bank_number].regs[REGBANK_GBR]; + break; + case SIM_SH_BANK_PR_REGNUM: + val = saved_state.asregs.regstack[gdb_bank_number].regs[REGBANK_PR]; + break; + case SIM_SH_BANK_IVN_REGNUM: + val = saved_state.asregs.regstack[gdb_bank_number].regs[REGBANK_IVN]; + break; + case SIM_SH_BANK_MACH_REGNUM: + val = saved_state.asregs.regstack[gdb_bank_number].regs[REGBANK_MACH]; + break; default: return 0; } @@ -2381,6 +2645,15 @@ sim_load (sd, prog, abfd, from_tty) prog_bfd = sim_load_file (sd, myname, callback, prog, abfd, sim_kind == SIM_OPEN_DEBUG, 0, sim_write); + + /* Set the bfd machine type. */ + if (prog_bfd) + saved_state.asregs.bfd_mach = bfd_get_mach (prog_bfd); + else if (abfd) + saved_state.asregs.bfd_mach = bfd_get_mach (abfd); + else + saved_state.asregs.bfd_mach = 0; + if (prog_bfd == NULL) return SIM_RC_FAIL; if (abfd == NULL) @@ -2403,6 +2676,10 @@ sim_create_inferior (sd, prog_bfd, argv, if (prog_bfd != NULL) saved_state.asregs.pc = bfd_get_start_address (prog_bfd); + /* Set the bfd machine type. */ + if (prog_bfd != NULL) + saved_state.asregs.bfd_mach = bfd_get_mach (prog_bfd); + /* Record the program's arguments. */ prog_argv = argv; Index: sim/testsuite/sim/sh/ChangeLog from Alexandre Oliva 2003-06-19 Michael Snyder * fsca.s: New file. * allinsn.exp: Add new tests. 2003-06-12 Michael Snyder * fsrra.s: New file. * allinsn.exp: Add new test. 2003-05-30 Michael Snyder * fail.s: New file, make sure fail works. * pass.s: New file, make sure pass works. Index: sim/testsuite/sim/sh/allinsn.exp =================================================================== RCS file: /cvs/uberbaum/./sim/testsuite/sim/sh/allinsn.exp,v retrieving revision 1.5 diff -u -p -r1.5 allinsn.exp --- sim/testsuite/sim/sh/allinsn.exp 12 Feb 2004 22:29:48 -0000 1.5 +++ sim/testsuite/sim/sh/allinsn.exp 29 Jul 2004 05:48:54 -0000 @@ -5,6 +5,16 @@ set all "sh shdsp" if [istarget sh-*elf] { run_sim_test add.s $all run_sim_test and.s $all + run_sim_test bandor.s sh + run_sim_test bandornot.s sh + run_sim_test bclr.s sh + run_sim_test bld.s sh + run_sim_test bldnot.s sh + run_sim_test bset.s sh + run_sim_test bst.s sh + run_sim_test bxor.s sh + run_sim_test clip.s sh + run_sim_test div.s sh run_sim_test dmxy.s shdsp run_sim_test fabs.s sh run_sim_test fadd.s sh @@ -32,10 +42,12 @@ if [istarget sh-*elf] { run_sim_test loop.s shdsp run_sim_test macl.s sh run_sim_test macw.s sh + run_sim_test mov.s $all run_sim_test movi.s $all run_sim_test movli.s $all run_sim_test movua.s $all run_sim_test movxy.s shdsp + run_sim_test mulr.s sh run_sim_test pabs.s shdsp run_sim_test paddc.s shdsp run_sim_test padd.s shdsp @@ -52,7 +64,9 @@ if [istarget sh-*elf] { run_sim_test pshlr.s shdsp run_sim_test psub.s shdsp run_sim_test pswap.s shdsp - run_sim_test sett.s $all + run_sim_test pushpop.s sh + run_sim_test resbank.s sh + run_sim_test sett.s sh run_sim_test shll.s $all run_sim_test shll2.s $all run_sim_test shll8.s $all Index: sim/testsuite/sim/sh/bandor.s =================================================================== RCS file: sim/testsuite/sim/sh/bandor.s diff -N sim/testsuite/sim/sh/bandor.s --- /dev/null 1 Jan 1970 00:00:00 -0000 +++ sim/testsuite/sim/sh/bandor.s 29 Jul 2004 05:48:54 -0000 @@ -0,0 +1,120 @@ +# sh testcase for band, bor +# mach: all +# as(sh): -defsym sim_cpu=0 +# as(shdsp): -defsym sim_cpu=1 -dsp + + .include "testutils.inc" + + .align 2 +_x: .long 0xa5a5a5a5 + + start + +bandor_b_imm_disp12_reg: + set_grs_a5a5 + # Make sure T is true to start. + sett + + mov.l x, r1 + + band.b #0, @(3, r1) + bf8k mfail + bor.b #1, @(3, r1) + bf8k mfail + band.b #2, @(3, r1) + bf8k mfail + bor.b #3, @(3, r1) + bf8k mfail + + bor.b #4, @(3, r1) + bf8k mfail + band.b #5, @(3, r1) + bf8k mfail + bor.b #6, @(3, r1) + bf8k mfail + band.b #7, @(3, r1) + bf8k mfail + + band.b #0, @(2, r1) + bf8k mfail + bor.b #1, @(2, r1) + bf8k mfail + band.b #2, @(2, r1) + bf8k mfail + bor.b #3, @(2, r1) + bf8k mfail + + bra .L2 + nop + + .align 2 +x: .long _x + +.L2: + bor.b #4, @(2, r1) + bf8k mfail + band.b #5, @(2, r1) + bf8k mfail + bor.b #6, @(2, r1) + bf8k mfail + band.b #7, @(2, r1) + bf8k mfail + + band.b #0, @(1, r1) + bf8k mfail + bor.b #1, @(1, r1) + bf8k mfail + band.b #2, @(1, r1) + bf8k mfail + bor.b #3, @(1, r1) + bf8k mfail + + bor.b #4, @(1, r1) + bf8k mfail + band.b #5, @(1, r1) + bf8k mfail + bor.b #6, @(1, r1) + bf8k mfail + band.b #7, @(1, r1) + bf8k mfail + + band.b #0, @(0, r1) + bf8k mfail + bor.b #1, @(0, r1) + bf8k mfail + band.b #2, @(0, r1) + bf8k mfail + bor.b #3, @(0, r1) + bf8k mfail + + bor.b #4, @(0, r1) + bf8k mfail + band.b #5, @(0, r1) + bf8k mfail + bor.b #6, @(0, r1) + bf8k mfail + band.b #7, @(0, r1) + bf8k mfail + + assertreg _x, r1 + + test_gr_a5a5 r0 + test_gr_a5a5 r2 + test_gr_a5a5 r3 + test_gr_a5a5 r4 + test_gr_a5a5 r5 + test_gr_a5a5 r6 + test_gr_a5a5 r7 + test_gr_a5a5 r8 + test_gr_a5a5 r9 + test_gr_a5a5 r10 + test_gr_a5a5 r11 + test_gr_a5a5 r12 + test_gr_a5a5 r13 + test_gr_a5a5 r14 + + pass + + exit 0 + + Index: sim/testsuite/sim/sh/bandornot.s =================================================================== RCS file: sim/testsuite/sim/sh/bandornot.s diff -N sim/testsuite/sim/sh/bandornot.s --- /dev/null 1 Jan 1970 00:00:00 -0000 +++ sim/testsuite/sim/sh/bandornot.s 29 Jul 2004 05:48:54 -0000 @@ -0,0 +1,120 @@ +# sh testcase for bandnot, bornot +# mach: all +# as(sh): -defsym sim_cpu=0 +# as(shdsp): -defsym sim_cpu=1 -dsp + + .include "testutils.inc" + + .align 2 +_x: .long 0xa5a5a5a5 + + start + +bandor_b_imm_disp12_reg: + set_grs_a5a5 + # Make sure T is true to start. + sett + + mov.l x, r1 + + bandnot.b #0, @(3, r1) + bt8k mfail + bornot.b #1, @(3, r1) + bf8k mfail + bandnot.b #2, @(3, r1) + bt8k mfail + bornot.b #3, @(3, r1) + bf8k mfail + + bornot.b #4, @(3, r1) + bf8k mfail + bandnot.b #5, @(3, r1) + bt8k mfail + bornot.b #6, @(3, r1) + bf8k mfail + bandnot.b #7, @(3, r1) + bt8k mfail + + bandnot.b #0, @(2, r1) + bt8k mfail + bornot.b #1, @(2, r1) + bf8k mfail + bandnot.b #2, @(2, r1) + bt8k mfail + bornot.b #3, @(2, r1) + bf8k mfail + + bra .L2 + nop + + .align 2 +x: .long _x + +.L2: + bornot.b #4, @(2, r1) + bf8k mfail + bandnot.b #5, @(2, r1) + bt8k mfail + bornot.b #6, @(2, r1) + bf8k mfail + bandnot.b #7, @(2, r1) + bt8k mfail + + bandnot.b #0, @(1, r1) + bt8k mfail + bornot.b #1, @(1, r1) + bf8k mfail + bandnot.b #2, @(1, r1) + bt8k mfail + bornot.b #3, @(1, r1) + bf8k mfail + + bornot.b #4, @(1, r1) + bf8k mfail + bandnot.b #5, @(1, r1) + bt8k mfail + bornot.b #6, @(1, r1) + bf8k mfail + bandnot.b #7, @(1, r1) + bt8k mfail + + bandnot.b #0, @(0, r1) + bt8k mfail + bornot.b #1, @(0, r1) + bf8k mfail + bandnot.b #2, @(0, r1) + bt8k mfail + bornot.b #3, @(0, r1) + bf8k mfail + + bornot.b #4, @(0, r1) + bf8k mfail + bandnot.b #5, @(0, r1) + bt8k mfail + bornot.b #6, @(0, r1) + bf8k mfail + bandnot.b #7, @(0, r1) + bt8k mfail + + assertreg _x, r1 + + test_gr_a5a5 r0 + test_gr_a5a5 r2 + test_gr_a5a5 r3 + test_gr_a5a5 r4 + test_gr_a5a5 r5 + test_gr_a5a5 r6 + test_gr_a5a5 r7 + test_gr_a5a5 r8 + test_gr_a5a5 r9 + test_gr_a5a5 r10 + test_gr_a5a5 r11 + test_gr_a5a5 r12 + test_gr_a5a5 r13 + test_gr_a5a5 r14 + + pass + + exit 0 + + Index: sim/testsuite/sim/sh/bclr.s =================================================================== RCS file: sim/testsuite/sim/sh/bclr.s diff -N sim/testsuite/sim/sh/bclr.s --- /dev/null 1 Jan 1970 00:00:00 -0000 +++ sim/testsuite/sim/sh/bclr.s 29 Jul 2004 05:48:54 -0000 @@ -0,0 +1,139 @@ +# sh testcase for bclr +# mach: all +# as(sh): -defsym sim_cpu=0 +# as(shdsp): -defsym sim_cpu=1 -dsp + + .include "testutils.inc" + + .align 2 +_x: .long 0xffffffff +_y: .long 0x55555555 + + start + +bclr_b_imm_disp12_reg: + set_grs_a5a5 + mov.l x, r1 + + bclr.b #0, @(3, r1) + assertmem _x, 0xfffffffe + bclr.b #1, @(3, r1) + assertmem _x, 0xfffffffc + bclr.b #2, @(3, r1) + assertmem _x, 0xfffffff8 + bclr.b #3, @(3, r1) + assertmem _x, 0xfffffff0 + + bclr.b #4, @(3, r1) + assertmem _x, 0xffffffe0 + bclr.b #5, @(3, r1) + assertmem _x, 0xffffffc0 + bclr.b #6, @(3, r1) + assertmem _x, 0xffffff80 + bclr.b #7, @(3, r1) + assertmem _x, 0xffffff00 + + bclr.b #0, @(2, r1) + assertmem _x, 0xfffffe00 + bclr.b #1, @(2, r1) + assertmem _x, 0xfffffc00 + bclr.b #2, @(2, r1) + assertmem _x, 0xfffff800 + bclr.b #3, @(2, r1) + assertmem _x, 0xfffff000 + + bra .L2 + nop + + .align 2 +x: .long _x +y: .long _y + +.L2: + bclr.b #4, @(2, r1) + assertmem _x, 0xffffe000 + bclr.b #5, @(2, r1) + assertmem _x, 0xffffc000 + bclr.b #6, @(2, r1) + assertmem _x, 0xffff8000 + bclr.b #7, @(2, r1) + assertmem _x, 0xffff0000 + + bclr.b #0, @(1, r1) + assertmem _x, 0xfffe0000 + bclr.b #1, @(1, r1) + assertmem _x, 0xfffc0000 + bclr.b #2, @(1, r1) + assertmem _x, 0xfff80000 + bclr.b #3, @(1, r1) + assertmem _x, 0xfff00000 + + bclr.b #4, @(1, r1) + assertmem _x, 0xffe00000 + bclr.b #5, @(1, r1) + assertmem _x, 0xffc00000 + bclr.b #6, @(1, r1) + assertmem _x, 0xff800000 + bclr.b #7, @(1, r1) + assertmem _x, 0xff000000 + + bclr.b #0, @(0, r1) + assertmem _x, 0xfe000000 + bclr.b #1, @(0, r1) + assertmem _x, 0xfc000000 + bclr.b #2, @(0, r1) + assertmem _x, 0xf8000000 + bclr.b #3, @(0, r1) + assertmem _x, 0xf0000000 + + bclr.b #4, @(0, r1) + assertmem _x, 0xe0000000 + bclr.b #5, @(0, r1) + assertmem _x, 0xc0000000 + bclr.b #6, @(0, r1) + assertmem _x, 0x80000000 + bclr.b #7, @(0, r1) + assertmem _x, 0x00000000 + + assertreg _x, r1 + +bclr_imm_reg: + set_greg 0xff, r1 + bclr #0, r1 + assertreg 0xfe, r1 + bclr #1, r1 + assertreg 0xfc, r1 + bclr #2, r1 + assertreg 0xf8, r1 + bclr #3, r1 + assertreg 0xf0, r1 + + bclr #4, r1 + assertreg 0xe0, r1 + bclr #5, r1 + assertreg 0xc0, r1 + bclr #6, r1 + assertreg 0x80, r1 + bclr #7, r1 + assertreg 0x00, r1 + + test_gr_a5a5 r0 + test_gr_a5a5 r2 + test_gr_a5a5 r3 + test_gr_a5a5 r4 + test_gr_a5a5 r5 + test_gr_a5a5 r6 + test_gr_a5a5 r7 + test_gr_a5a5 r8 + test_gr_a5a5 r9 + test_gr_a5a5 r10 + test_gr_a5a5 r11 + test_gr_a5a5 r12 + test_gr_a5a5 r13 + test_gr_a5a5 r14 + + pass + + exit 0 + + Index: sim/testsuite/sim/sh/bld.s =================================================================== RCS file: sim/testsuite/sim/sh/bld.s diff -N sim/testsuite/sim/sh/bld.s --- /dev/null 1 Jan 1970 00:00:00 -0000 +++ sim/testsuite/sim/sh/bld.s 29 Jul 2004 05:48:54 -0000 @@ -0,0 +1,121 @@ +# sh testcase for bld +# mach: all +# as(sh): -defsym sim_cpu=0 +# as(shdsp): -defsym sim_cpu=1 -dsp + + .include "testutils.inc" + + .align 2 +_x: .long 0xa5a5a5a5 +_y: .long 0x55555555 + + start + +bld_b_imm_disp12_reg: + set_grs_a5a5 + mov.l x, r1 + + bld.b #0, @(0, r1) + bf8k mfail + bld.b #1, @(0, r1) + bt8k mfail + bld.b #2, @(0, r1) + bf8k mfail + bld.b #3, @(0, r1) + bt8k mfail + + bld.b #4, @(0, r1) + bt8k mfail + bld.b #5, @(0, r1) + bf8k mfail + bld.b #6, @(0, r1) + bt8k mfail + bld.b #7, @(0, r1) + bf8k mfail + + bld.b #0, @(1, r1) + bf8k mfail + bld.b #1, @(1, r1) + bt8k mfail + bld.b #2, @(1, r1) + bf8k mfail + bld.b #3, @(1, r1) + bt8k mfail + + bld.b #4, @(1, r1) + bt8k mfail + bld.b #5, @(1, r1) + bf8k mfail + bld.b #6, @(1, r1) + bt8k mfail + bld.b #7, @(1, r1) + bf8k mfail + + bld.b #0, @(2, r1) + bf8k mfail + bld.b #1, @(2, r1) + bt8k mfail + bld.b #2, @(2, r1) + bf8k mfail + bld.b #3, @(2, r1) + bt8k mfail + + bld.b #4, @(2, r1) + bt8k mfail + bld.b #5, @(2, r1) + bf8k mfail + bld.b #6, @(2, r1) + bt8k mfail + bld.b #7, @(2, r1) + bf8k mfail + + bld.b #0, @(3, r1) + bf8k mfail + bld.b #1, @(3, r1) + bt8k mfail + bld.b #2, @(3, r1) + bf8k mfail + bld.b #3, @(3, r1) + bt8k mfail + + bld.b #4, @(3, r1) + bt8k mfail + bld.b #5, @(3, r1) + bf8k mfail + bld.b #6, @(3, r1) + bt8k mfail + bld.b #7, @(3, r1) + bf8k mfail + + assertreg _x, r1 + +bld_imm_reg: + set_greg 0xa5a5a5a5, r1 + bld #0, r1 + bf8k mfail + bld #1, r1 + bt8k mfail + bld #2, r1 + bf8k mfail + bld #3, r1 + bt8k mfail + + bld #4, r1 + bt8k mfail + bld #5, r1 + bf8k mfail + bld #6, r1 + bt8k mfail + bld #7, r1 + bf8k mfail + + test_grs_a5a5 + + pass + + exit 0 + + .align 2 +x: .long _x +y: .long _y + Index: sim/testsuite/sim/sh/bldnot.s =================================================================== RCS file: sim/testsuite/sim/sh/bldnot.s diff -N sim/testsuite/sim/sh/bldnot.s --- /dev/null 1 Jan 1970 00:00:00 -0000 +++ sim/testsuite/sim/sh/bldnot.s 29 Jul 2004 05:48:54 -0000 @@ -0,0 +1,102 @@ +# sh testcase for bldnot +# mach: all +# as(sh): -defsym sim_cpu=0 +# as(shdsp): -defsym sim_cpu=1 -dsp + + .include "testutils.inc" + + .align 2 +_x: .long 0xa5a5a5a5 +_y: .long 0x55555555 + + start + +bldnot_b_imm_disp12_reg: + set_grs_a5a5 + mov.l x, r1 + + bldnot.b #0, @(0, r1) + bt8k mfail + bldnot.b #1, @(0, r1) + bf8k mfail + bldnot.b #2, @(0, r1) + bt8k mfail + bldnot.b #3, @(0, r1) + bf8k mfail + + bldnot.b #4, @(0, r1) + bf8k mfail + bldnot.b #5, @(0, r1) + bt8k mfail + bldnot.b #6, @(0, r1) + bf8k mfail + bldnot.b #7, @(0, r1) + bt8k mfail + + bldnot.b #0, @(1, r1) + bt8k mfail + bldnot.b #1, @(1, r1) + bf8k mfail + bldnot.b #2, @(1, r1) + bt8k mfail + bldnot.b #3, @(1, r1) + bf8k mfail + + bldnot.b #4, @(1, r1) + bf8k mfail + bldnot.b #5, @(1, r1) + bt8k mfail + bldnot.b #6, @(1, r1) + bf8k mfail + bldnot.b #7, @(1, r1) + bt8k mfail + + bldnot.b #0, @(2, r1) + bt8k mfail + bldnot.b #1, @(2, r1) + bf8k mfail + bldnot.b #2, @(2, r1) + bt8k mfail + bldnot.b #3, @(2, r1) + bf8k mfail + + bldnot.b #4, @(2, r1) + bf8k mfail + bldnot.b #5, @(2, r1) + bt8k mfail + bldnot.b #6, @(2, r1) + bf8k mfail + bldnot.b #7, @(2, r1) + bt8k mfail + + bldnot.b #0, @(3, r1) + bt8k mfail + bldnot.b #1, @(3, r1) + bf8k mfail + bldnot.b #2, @(3, r1) + bt8k mfail + bldnot.b #3, @(3, r1) + bf8k mfail + + bldnot.b #4, @(3, r1) + bf8k mfail + bldnot.b #5, @(3, r1) + bt8k mfail + bldnot.b #6, @(3, r1) + bf8k mfail + bldnot.b #7, @(3, r1) + bt8k mfail + + assertreg _x, r1 + set_greg 0xa5a5a5a5, r1 + + test_grs_a5a5 + + pass + + exit 0 + + .align 2 +x: .long _x +y: .long _y + Index: sim/testsuite/sim/sh/bset.s =================================================================== RCS file: sim/testsuite/sim/sh/bset.s diff -N sim/testsuite/sim/sh/bset.s --- /dev/null 1 Jan 1970 00:00:00 -0000 +++ sim/testsuite/sim/sh/bset.s 29 Jul 2004 05:48:54 -0000 @@ -0,0 +1,139 @@ +# sh testcase for bset +# mach: all +# as(sh): -defsym sim_cpu=0 +# as(shdsp): -defsym sim_cpu=1 -dsp + + .include "testutils.inc" + + .align 2 +_x: .long 0 +_y: .long 0x55555555 + + start + +bset_b_imm_disp12_reg: + set_grs_a5a5 + mov.l x, r1 + + bset.b #0, @(3, r1) + assertmem _x, 0x1 + bset.b #1, @(3, r1) + assertmem _x, 0x3 + bset.b #2, @(3, r1) + assertmem _x, 0x7 + bset.b #3, @(3, r1) + assertmem _x, 0xf + + bset.b #4, @(3, r1) + assertmem _x, 0x1f + bset.b #5, @(3, r1) + assertmem _x, 0x3f + bset.b #6, @(3, r1) + assertmem _x, 0x7f + bset.b #7, @(3, r1) + assertmem _x, 0xff + + bset.b #0, @(2, r1) + assertmem _x, 0x1ff + bset.b #1, @(2, r1) + assertmem _x, 0x3ff + bset.b #2, @(2, r1) + assertmem _x, 0x7ff + bset.b #3, @(2, r1) + assertmem _x, 0xfff + + bra .L2 + nop + + .align 2 +x: .long _x +y: .long _y + +.L2: + bset.b #4, @(2, r1) + assertmem _x, 0x1fff + bset.b #5, @(2, r1) + assertmem _x, 0x3fff + bset.b #6, @(2, r1) + assertmem _x, 0x7fff + bset.b #7, @(2, r1) + assertmem _x, 0xffff + + bset.b #0, @(1, r1) + assertmem _x, 0x1ffff + bset.b #1, @(1, r1) + assertmem _x, 0x3ffff + bset.b #2, @(1, r1) + assertmem _x, 0x7ffff + bset.b #3, @(1, r1) + assertmem _x, 0xfffff + + bset.b #4, @(1, r1) + assertmem _x, 0x1fffff + bset.b #5, @(1, r1) + assertmem _x, 0x3fffff + bset.b #6, @(1, r1) + assertmem _x, 0x7fffff + bset.b #7, @(1, r1) + assertmem _x, 0xffffff + + bset.b #0, @(0, r1) + assertmem _x, 0x1ffffff + bset.b #1, @(0, r1) + assertmem _x, 0x3ffffff + bset.b #2, @(0, r1) + assertmem _x, 0x7ffffff + bset.b #3, @(0, r1) + assertmem _x, 0xfffffff + + bset.b #4, @(0, r1) + assertmem _x, 0x1fffffff + bset.b #5, @(0, r1) + assertmem _x, 0x3fffffff + bset.b #6, @(0, r1) + assertmem _x, 0x7fffffff + bset.b #7, @(0, r1) + assertmem _x, 0xffffffff + + assertreg _x, r1 + +bset_imm_reg: + set_greg 0, r1 + bset #0, r1 + assertreg 0x1, r1 + bset #1, r1 + assertreg 0x3, r1 + bset #2, r1 + assertreg 0x7, r1 + bset #3, r1 + assertreg 0xf, r1 + + bset #4, r1 + assertreg 0x1f, r1 + bset #5, r1 + assertreg 0x3f, r1 + bset #6, r1 + assertreg 0x7f, r1 + bset #7, r1 + assertreg 0xff, r1 + + test_gr_a5a5 r0 + test_gr_a5a5 r2 + test_gr_a5a5 r3 + test_gr_a5a5 r4 + test_gr_a5a5 r5 + test_gr_a5a5 r6 + test_gr_a5a5 r7 + test_gr_a5a5 r8 + test_gr_a5a5 r9 + test_gr_a5a5 r10 + test_gr_a5a5 r11 + test_gr_a5a5 r12 + test_gr_a5a5 r13 + test_gr_a5a5 r14 + + pass + + exit 0 + + Index: sim/testsuite/sim/sh/bst.s =================================================================== RCS file: sim/testsuite/sim/sh/bst.s diff -N sim/testsuite/sim/sh/bst.s --- /dev/null 1 Jan 1970 00:00:00 -0000 +++ sim/testsuite/sim/sh/bst.s 29 Jul 2004 05:48:54 -0000 @@ -0,0 +1,142 @@ +# sh testcase for bst +# mach: all +# as(sh): -defsym sim_cpu=0 +# as(shdsp): -defsym sim_cpu=1 -dsp + + .include "testutils.inc" + + .align 2 +_x: .long 0 +_y: .long 0x55555555 + + start + +bst_b_imm_disp12_reg: + set_grs_a5a5 + # Make sure T is true to start. + sett + + mov.l x, r1 + + bst.b #0, @(3, r1) + assertmem _x, 0x1 + bst.b #1, @(3, r1) + assertmem _x, 0x3 + bst.b #2, @(3, r1) + assertmem _x, 0x7 + bst.b #3, @(3, r1) + assertmem _x, 0xf + + bst.b #4, @(3, r1) + assertmem _x, 0x1f + bst.b #5, @(3, r1) + assertmem _x, 0x3f + bst.b #6, @(3, r1) + assertmem _x, 0x7f + bst.b #7, @(3, r1) + assertmem _x, 0xff + + bst.b #0, @(2, r1) + assertmem _x, 0x1ff + bst.b #1, @(2, r1) + assertmem _x, 0x3ff + bst.b #2, @(2, r1) + assertmem _x, 0x7ff + bst.b #3, @(2, r1) + assertmem _x, 0xfff + + bra .L2 + nop + + .align 2 +x: .long _x +y: .long _y + +.L2: + bst.b #4, @(2, r1) + assertmem _x, 0x1fff + bst.b #5, @(2, r1) + assertmem _x, 0x3fff + bst.b #6, @(2, r1) + assertmem _x, 0x7fff + bst.b #7, @(2, r1) + assertmem _x, 0xffff + + bst.b #0, @(1, r1) + assertmem _x, 0x1ffff + bst.b #1, @(1, r1) + assertmem _x, 0x3ffff + bst.b #2, @(1, r1) + assertmem _x, 0x7ffff + bst.b #3, @(1, r1) + assertmem _x, 0xfffff + + bst.b #4, @(1, r1) + assertmem _x, 0x1fffff + bst.b #5, @(1, r1) + assertmem _x, 0x3fffff + bst.b #6, @(1, r1) + assertmem _x, 0x7fffff + bst.b #7, @(1, r1) + assertmem _x, 0xffffff + + bst.b #0, @(0, r1) + assertmem _x, 0x1ffffff + bst.b #1, @(0, r1) + assertmem _x, 0x3ffffff + bst.b #2, @(0, r1) + assertmem _x, 0x7ffffff + bst.b #3, @(0, r1) + assertmem _x, 0xfffffff + + bst.b #4, @(0, r1) + assertmem _x, 0x1fffffff + bst.b #5, @(0, r1) + assertmem _x, 0x3fffffff + bst.b #6, @(0, r1) + assertmem _x, 0x7fffffff + bst.b #7, @(0, r1) + assertmem _x, 0xffffffff + + assertreg _x, r1 + +bst_imm_reg: + set_greg 0, r1 + bst #0, r1 + assertreg 0x1, r1 + bst #1, r1 + assertreg 0x3, r1 + bst #2, r1 + assertreg 0x7, r1 + bst #3, r1 + assertreg 0xf, r1 + + bst #4, r1 + assertreg 0x1f, r1 + bst #5, r1 + assertreg 0x3f, r1 + bst #6, r1 + assertreg 0x7f, r1 + bst #7, r1 + assertreg 0xff, r1 + + test_gr_a5a5 r0 + test_gr_a5a5 r2 + test_gr_a5a5 r3 + test_gr_a5a5 r4 + test_gr_a5a5 r5 + test_gr_a5a5 r6 + test_gr_a5a5 r7 + test_gr_a5a5 r8 + test_gr_a5a5 r9 + test_gr_a5a5 r10 + test_gr_a5a5 r11 + test_gr_a5a5 r12 + test_gr_a5a5 r13 + test_gr_a5a5 r14 + + pass + + exit 0 + + Index: sim/testsuite/sim/sh/bxor.s =================================================================== RCS file: sim/testsuite/sim/sh/bxor.s diff -N sim/testsuite/sim/sh/bxor.s --- /dev/null 1 Jan 1970 00:00:00 -0000 +++ sim/testsuite/sim/sh/bxor.s 29 Jul 2004 05:48:54 -0000 @@ -0,0 +1,120 @@ +# sh testcase for bxor +# mach: all +# as(sh): -defsym sim_cpu=0 +# as(shdsp): -defsym sim_cpu=1 -dsp + + .include "testutils.inc" + + .align 2 +_x: .long 0xa5a5a5a5 + + start + +bxor_b_imm_disp12_reg: + set_grs_a5a5 + # Make sure T is true to start. + sett + + mov.l x, r1 + + bxor.b #0, @(3, r1) + bt8k mfail + bxor.b #1, @(3, r1) + bt8k mfail + bxor.b #2, @(3, r1) + bf8k mfail + bxor.b #3, @(3, r1) + bf8k mfail + + bxor.b #4, @(3, r1) + bf8k mfail + bxor.b #5, @(3, r1) + bt8k mfail + bxor.b #6, @(3, r1) + bt8k mfail + bxor.b #7, @(3, r1) + bf8k mfail + + bxor.b #0, @(2, r1) + bt8k mfail + bxor.b #1, @(2, r1) + bt8k mfail + bxor.b #2, @(2, r1) + bf8k mfail + bxor.b #3, @(2, r1) + bf8k mfail + + bra .L2 + nop + + .align 2 +x: .long _x + +.L2: + bxor.b #4, @(2, r1) + bf8k mfail + bxor.b #5, @(2, r1) + bt8k mfail + bxor.b #6, @(2, r1) + bt8k mfail + bxor.b #7, @(2, r1) + bf8k mfail + + bxor.b #0, @(1, r1) + bt8k mfail + bxor.b #1, @(1, r1) + bt8k mfail + bxor.b #2, @(1, r1) + bf8k mfail + bxor.b #3, @(1, r1) + bf8k mfail + + bxor.b #4, @(1, r1) + bf8k mfail + bxor.b #5, @(1, r1) + bt8k mfail + bxor.b #6, @(1, r1) + bt8k mfail + bxor.b #7, @(1, r1) + bf8k mfail + + bxor.b #0, @(0, r1) + bt8k mfail + bxor.b #1, @(0, r1) + bt8k mfail + bxor.b #2, @(0, r1) + bf8k mfail + bxor.b #3, @(0, r1) + bf8k mfail + + bxor.b #4, @(0, r1) + bf8k mfail + bxor.b #5, @(0, r1) + bt8k mfail + bxor.b #6, @(0, r1) + bt8k mfail + bxor.b #7, @(0, r1) + bf8k mfail + + assertreg _x, r1 + + test_gr_a5a5 r0 + test_gr_a5a5 r2 + test_gr_a5a5 r3 + test_gr_a5a5 r4 + test_gr_a5a5 r5 + test_gr_a5a5 r6 + test_gr_a5a5 r7 + test_gr_a5a5 r8 + test_gr_a5a5 r9 + test_gr_a5a5 r10 + test_gr_a5a5 r11 + test_gr_a5a5 r12 + test_gr_a5a5 r13 + test_gr_a5a5 r14 + + pass + + exit 0 + + Index: sim/testsuite/sim/sh/clip.s =================================================================== RCS file: sim/testsuite/sim/sh/clip.s diff -N sim/testsuite/sim/sh/clip.s --- /dev/null 1 Jan 1970 00:00:00 -0000 +++ sim/testsuite/sim/sh/clip.s 29 Jul 2004 05:48:54 -0000 @@ -0,0 +1,89 @@ +# sh testcase for clips, clipu +# mach: all +# as(sh): -defsym sim_cpu=0 +# as(shdsp): -defsym sim_cpu=1 -dsp + + .include "testutils.inc" + + start + +clips_b: + set_grs_a5a5 + clips.b r1 + test_gr0_a5a5 + assertreg 0xffffff80 r1 + test_gr_a5a5 r2 + test_gr_a5a5 r3 + test_gr_a5a5 r4 + test_gr_a5a5 r5 + test_gr_a5a5 r6 + test_gr_a5a5 r7 + test_gr_a5a5 r8 + test_gr_a5a5 r9 + test_gr_a5a5 r10 + test_gr_a5a5 r11 + test_gr_a5a5 r12 + test_gr_a5a5 r13 + test_gr_a5a5 r14 + +clipu_b: + set_grs_a5a5 + clipu.b r1 + test_gr0_a5a5 + assertreg 0xff r1 + test_gr_a5a5 r2 + test_gr_a5a5 r3 + test_gr_a5a5 r4 + test_gr_a5a5 r5 + test_gr_a5a5 r6 + test_gr_a5a5 r7 + test_gr_a5a5 r8 + test_gr_a5a5 r9 + test_gr_a5a5 r10 + test_gr_a5a5 r11 + test_gr_a5a5 r12 + test_gr_a5a5 r13 + test_gr_a5a5 r14 + +clips_w: + set_grs_a5a5 + clips.w r1 + test_gr0_a5a5 + assertreg 0xffff8000 r1 + test_gr_a5a5 r2 + test_gr_a5a5 r3 + test_gr_a5a5 r4 + test_gr_a5a5 r5 + test_gr_a5a5 r6 + test_gr_a5a5 r7 + test_gr_a5a5 r8 + test_gr_a5a5 r9 + test_gr_a5a5 r10 + test_gr_a5a5 r11 + test_gr_a5a5 r12 + test_gr_a5a5 r13 + test_gr_a5a5 r14 + +clipu_w: + set_grs_a5a5 + clipu.w r1 + test_gr0_a5a5 + assertreg 0xffff r1 + test_gr_a5a5 r2 + test_gr_a5a5 r3 + test_gr_a5a5 r4 + test_gr_a5a5 r5 + test_gr_a5a5 r6 + test_gr_a5a5 r7 + test_gr_a5a5 r8 + test_gr_a5a5 r9 + test_gr_a5a5 r10 + test_gr_a5a5 r11 + test_gr_a5a5 r12 + test_gr_a5a5 r13 + test_gr_a5a5 r14 + + pass + + exit 0 + Index: sim/testsuite/sim/sh/div.s =================================================================== RCS file: sim/testsuite/sim/sh/div.s diff -N sim/testsuite/sim/sh/div.s --- /dev/null 1 Jan 1970 00:00:00 -0000 +++ sim/testsuite/sim/sh/div.s 29 Jul 2004 05:48:54 -0000 @@ -0,0 +1,199 @@ +# sh testcase for divs and divu +# mach: all +# as(sh): -defsym sim_cpu=0 +# as(shdsp): -defsym sim_cpu=1 -dsp + + .include "testutils.inc" + + start + +divs_1: ! divide by one + set_grs_a5a5 + mov #1, r0 + divs r0, r1 + assertreg0 1 + test_gr_a5a5 r1 + test_gr_a5a5 r2 + test_gr_a5a5 r3 + test_gr_a5a5 r4 + test_gr_a5a5 r5 + test_gr_a5a5 r6 + test_gr_a5a5 r7 + test_gr_a5a5 r8 + test_gr_a5a5 r9 + test_gr_a5a5 r10 + test_gr_a5a5 r11 + test_gr_a5a5 r12 + test_gr_a5a5 r13 + test_gr_a5a5 r14 + +divs_2: ! divide by two + set_grs_a5a5 + mov #2, r0 + divs r0, r1 + assertreg0 2 + assertreg 0xd2d2d2d3, r1 + test_gr_a5a5 r2 + test_gr_a5a5 r3 + test_gr_a5a5 r4 + test_gr_a5a5 r5 + test_gr_a5a5 r6 + test_gr_a5a5 r7 + test_gr_a5a5 r8 + test_gr_a5a5 r9 + test_gr_a5a5 r10 + test_gr_a5a5 r11 + test_gr_a5a5 r12 + test_gr_a5a5 r13 + test_gr_a5a5 r14 + +divs_3: ! divide by three + set_grs_a5a5 + mov #3, r0 + divs r0, r1 + assertreg0 3 + assertreg 0xe1e1e1e2, r1 + test_gr_a5a5 r2 + test_gr_a5a5 r3 + test_gr_a5a5 r4 + test_gr_a5a5 r5 + test_gr_a5a5 r6 + test_gr_a5a5 r7 + test_gr_a5a5 r8 + test_gr_a5a5 r9 + test_gr_a5a5 r10 + test_gr_a5a5 r11 + test_gr_a5a5 r12 + test_gr_a5a5 r13 + test_gr_a5a5 r14 + +divs_0: ! divide by zero + set_grs_a5a5 + mov #0, r0 + divs r0, r1 + assertreg0 0 + assertreg 0x7fffffff, r1 + test_gr_a5a5 r2 + test_gr_a5a5 r3 + test_gr_a5a5 r4 + test_gr_a5a5 r5 + test_gr_a5a5 r6 + test_gr_a5a5 r7 + test_gr_a5a5 r8 + test_gr_a5a5 r9 + test_gr_a5a5 r10 + test_gr_a5a5 r11 + test_gr_a5a5 r12 + test_gr_a5a5 r13 + test_gr_a5a5 r14 + +divs_o: ! divide signed overflow + set_grs_a5a5 + mov #16, r0 + movi20 #0x8000, r1 + shad r0, r1 ! r1 == 0x80000000 + mov #-1, r0 + divs r0, r1 + assertreg0 -1 + assertreg 0x7fffffff, r1 + test_gr_a5a5 r2 + test_gr_a5a5 r3 + test_gr_a5a5 r4 + test_gr_a5a5 r5 + test_gr_a5a5 r6 + test_gr_a5a5 r7 + test_gr_a5a5 r8 + test_gr_a5a5 r9 + test_gr_a5a5 r10 + test_gr_a5a5 r11 + test_gr_a5a5 r12 + test_gr_a5a5 r13 + test_gr_a5a5 r14 + + +divu_1: ! divide by one, unsigned + set_grs_a5a5 + mov #1, r0 + divu r0, r1 + assertreg0 1 + test_gr_a5a5 r1 + test_gr_a5a5 r2 + test_gr_a5a5 r3 + test_gr_a5a5 r4 + test_gr_a5a5 r5 + test_gr_a5a5 r6 + test_gr_a5a5 r7 + test_gr_a5a5 r8 + test_gr_a5a5 r9 + test_gr_a5a5 r10 + test_gr_a5a5 r11 + test_gr_a5a5 r12 + test_gr_a5a5 r13 + test_gr_a5a5 r14 + +divu_2: ! divide by two, unsigned + set_grs_a5a5 + mov #2, r0 + divu r0, r1 + assertreg0 2 + assertreg 0x52d2d2d2, r1 + test_gr_a5a5 r2 + test_gr_a5a5 r3 + test_gr_a5a5 r4 + test_gr_a5a5 r5 + test_gr_a5a5 r6 + test_gr_a5a5 r7 + test_gr_a5a5 r8 + test_gr_a5a5 r9 + test_gr_a5a5 r10 + test_gr_a5a5 r11 + test_gr_a5a5 r12 + test_gr_a5a5 r13 + test_gr_a5a5 r14 + +divu_3: ! divide by three, unsigned + set_grs_a5a5 + mov #3, r0 + divu r0, r1 + assertreg0 3 + assertreg 0x37373737, r1 + test_gr_a5a5 r2 + test_gr_a5a5 r3 + test_gr_a5a5 r4 + test_gr_a5a5 r5 + test_gr_a5a5 r6 + test_gr_a5a5 r7 + test_gr_a5a5 r8 + test_gr_a5a5 r9 + test_gr_a5a5 r10 + test_gr_a5a5 r11 + test_gr_a5a5 r12 + test_gr_a5a5 r13 + test_gr_a5a5 r14 + +divu_0: ! divide by zero, unsigned + set_grs_a5a5 + mov #0, r0 + divu r0, r1 + assertreg0 0 + assertreg 0xffffffff, r1 + test_gr_a5a5 r2 + test_gr_a5a5 r3 + test_gr_a5a5 r4 + test_gr_a5a5 r5 + test_gr_a5a5 r6 + test_gr_a5a5 r7 + test_gr_a5a5 r8 + test_gr_a5a5 r9 + test_gr_a5a5 r10 + test_gr_a5a5 r11 + test_gr_a5a5 r12 + test_gr_a5a5 r13 + test_gr_a5a5 r14 + + + pass + + exit 0 + + \ No newline at end of file Index: sim/testsuite/sim/sh/fail.s =================================================================== RCS file: sim/testsuite/sim/sh/fail.s diff -N sim/testsuite/sim/sh/fail.s --- /dev/null 1 Jan 1970 00:00:00 -0000 +++ sim/testsuite/sim/sh/fail.s 29 Jul 2004 05:48:54 -0000 @@ -0,0 +1,13 @@ +# sh testcase, fail +# mach: all +# as(sh): -defsym sim_cpu=0 +# as(shdsp): -defsym sim_cpu=1 -dsp + + .include "testutils.inc" + + start + + fail + + exit 0 + Index: sim/testsuite/sim/sh/fsca.s =================================================================== RCS file: sim/testsuite/sim/sh/fsca.s diff -N sim/testsuite/sim/sh/fsca.s --- /dev/null 1 Jan 1970 00:00:00 -0000 +++ sim/testsuite/sim/sh/fsca.s 29 Jul 2004 05:48:54 -0000 @@ -0,0 +1,97 @@ +# sh testcase for fsca +# mach: sh +# as(sh): -defsym sim_cpu=0 + + .include "testutils.inc" + + start +fsca: + set_grs_a5a5 + set_fprs_a5a5 + # Start with angle zero + mov.l zero, r0 + lds r0, fpul + fsca fpul, dr2 + assert_fpreg_i 0, fr2 + assert_fpreg_i 1, fr3 + + mov.l plus_90, r0 + lds r0, fpul + fsca fpul, dr2 + assert_fpreg_i 1, fr2 + assert_fpreg_i 0, fr3 + + mov.l plus_180, r0 + lds r0, fpul + fsca fpul, dr2 + assert_fpreg_i 0, fr2 + assert_fpreg_i -1, fr3 + + mov.l plus_270, r0 + lds r0, fpul + fsca fpul, dr2 + assert_fpreg_i -1, fr2 + assert_fpreg_i 0, fr3 + + mov.l plus_360, r0 + lds r0, fpul + fsca fpul, dr2 + assert_fpreg_i 0, fr2 + assert_fpreg_i 1, fr3 + + mov.l minus_90, r0 + lds r0, fpul + fsca fpul, dr2 + assert_fpreg_i -1, fr2 + assert_fpreg_i 0, fr3 + + mov.l minus_180, r0 + lds r0, fpul + fsca fpul, dr2 + assert_fpreg_i 0, fr2 + assert_fpreg_i -1, fr3 + + mov.l minus_270, r0 + lds r0, fpul + fsca fpul, dr2 + assert_fpreg_i 1, fr2 + assert_fpreg_i 0, fr3 + + mov.l minus_360, r0 + lds r0, fpul + fsca fpul, dr2 + assert_fpreg_i 0, fr2 + assert_fpreg_i 1, fr3 + + assertreg0 0xffff0000 + set_greg 0xa5a5a5a5, r0 + test_grs_a5a5 + test_fpr_a5a5 fr0 + test_fpr_a5a5 fr1 + test_fpr_a5a5 fr4 + test_fpr_a5a5 fr5 + test_fpr_a5a5 fr6 + test_fpr_a5a5 fr7 + test_fpr_a5a5 fr8 + test_fpr_a5a5 fr9 + test_fpr_a5a5 fr10 + test_fpr_a5a5 fr11 + test_fpr_a5a5 fr12 + test_fpr_a5a5 fr13 + test_fpr_a5a5 fr14 + test_fpr_a5a5 fr15 + pass + exit 0 + + .align 2 +zero: .long 0 +one_bitty: .long 1 +plus_90: .long 0x04000 +plus_180: .long 0x08000 +plus_270: .long 0x0c000 +plus_360: .long 0x10000 +minus_90: .long 0xffffc000 +minus_180: .long 0xffff8000 +minus_270: .long 0xffff4000 +minus_360: .long 0xffff0000 +minus_1_bitty: .long 0xffffffff Index: sim/testsuite/sim/sh/fsrra.s =================================================================== RCS file: sim/testsuite/sim/sh/fsrra.s diff -N sim/testsuite/sim/sh/fsrra.s --- /dev/null 1 Jan 1970 00:00:00 -0000 +++ sim/testsuite/sim/sh/fsrra.s 29 Jul 2004 05:48:54 -0000 @@ -0,0 +1,62 @@ +# sh testcase for fsrra +# mach: sh +# as(sh): -defsym sim_cpu=0 + + .include "testutils.inc" + + start +fsrra_single: + set_grs_a5a5 + set_fprs_a5a5 + # 1/sqrt(0.0) = +infinity. + fldi0 fr0 + fsrra fr0 + assert_fpreg_x 0x7f800000, fr0 + + # 1/sqrt(1.0) = 1.0. + fldi1 fr0 + fsrra fr0 + assert_fpreg_i 1, fr0 + + # 1/sqrt(4.0) = 1/2.0 + fldi1 fr0 + # Double it. + fadd fr0, fr0 + # Double it again. + fadd fr0, fr0 + fsrra fr0 + fldi1 fr2 + # Double it. + fadd fr2, fr2 + fldi1 fr1 + # Divide + fdiv fr2, fr1 + fcmp/eq fr0, fr1 + bt .L2 + fail +.L2: + # Double-check (pun intended) + fadd fr0, fr0 + assert_fpreg_i 1, fr0 + fadd fr1, fr1 + assert_fpreg_i 1, fr1 + + # And make sure the rest of the regs are un-affected. + assert_fpreg_i 2, fr2 + test_fpr_a5a5 fr3 + test_fpr_a5a5 fr4 + test_fpr_a5a5 fr5 + test_fpr_a5a5 fr6 + test_fpr_a5a5 fr7 + test_fpr_a5a5 fr8 + test_fpr_a5a5 fr9 + test_fpr_a5a5 fr10 + test_fpr_a5a5 fr11 + test_fpr_a5a5 fr12 + test_fpr_a5a5 fr13 + test_fpr_a5a5 fr14 + test_fpr_a5a5 fr15 + test_grs_a5a5 + + pass + exit 0 Index: sim/testsuite/sim/sh/mov.s =================================================================== RCS file: sim/testsuite/sim/sh/mov.s diff -N sim/testsuite/sim/sh/mov.s --- /dev/null 1 Jan 1970 00:00:00 -0000 +++ sim/testsuite/sim/sh/mov.s 29 Jul 2004 05:48:54 -0000 @@ -0,0 +1,118 @@ +# sh testcase for all mov.[bwl] instructions +# mach: sh +# as(sh): -defsym sim_cpu=0 + + .include "testutils.inc" + + .align 2 +_lsrc: .long 0x55555555 +_wsrc: .long 0x55550000 +_bsrc: .long 0x55000000 + + .align 2 +_ldst: .long 0 +_wdst: .long 0 +_bdst: .long 0 + + + start + +movb_disp12_reg: # Test 8-bit @(disp12,gr) -> gr + set_grs_a5a5 + mov.l bsrc, r1 + add #-111, r1 + add #-111, r1 + add #-111, r1 + add #-111, r1 + mov.b @(444,r1), r2 + + assertreg _bsrc-444, r1 + assertreg 0x55, r2 + +movb_reg_disp12: # Test 8-bit gr -> @(disp12,gr) + set_grs_a5a5 + mov.l bdst, r1 + add #-111, r1 + add #-111, r1 + add #-111, r1 + add #-111, r1 + mov.b r2, @(444,r1) + + assertreg _bdst-444, r1 + assertmem _bdst, 0xa5000000 + +movw_disp12_reg: # Test 16-bit @(disp12,gr) -> gr + set_grs_a5a5 + mov.l wsrc, r1 + add #-111, r1 + add #-111, r1 + add #-111, r1 + add #-111, r1 + mov.w @(444,r1), r2 + + assertreg _wsrc-444, r1 + assertreg 0x5555, r2 + +movw_reg_disp12: # Test 16-bit gr -> @(disp12,gr) + set_grs_a5a5 + mov.l wdst, r1 + add #-111, r1 + add #-111, r1 + add #-111, r1 + add #-111, r1 + mov.w r2, @(444,r1) + + assertreg _wdst-444, r1 + assertmem _wdst, 0xa5a50000 + +movl_disp12_reg: # Test 32-bit @(disp12,gr) -> gr + set_grs_a5a5 + mov.l lsrc, r1 + add #-111, r1 + add #-111, r1 + add #-111, r1 + add #-111, r1 + mov.l @(444,r1), r2 + + assertreg _lsrc-444, r1 + assertreg 0x55555555, r2 + +movl_reg_disp12: # Test 32-bit gr -> @(disp12,gr) + set_grs_a5a5 + mov.l ldst, r1 + add #-111, r1 + add #-111, r1 + add #-111, r1 + add #-111, r1 + mov.l r2, @(444,r1) + + assertreg _ldst-444, r1 + assertmem _ldst, 0xa5a5a5a5 + + test_gr_a5a5 r0 + test_gr_a5a5 r2 + test_gr_a5a5 r3 + test_gr_a5a5 r4 + test_gr_a5a5 r5 + test_gr_a5a5 r6 + test_gr_a5a5 r7 + test_gr_a5a5 r8 + test_gr_a5a5 r9 + test_gr_a5a5 r10 + test_gr_a5a5 r11 + test_gr_a5a5 r12 + test_gr_a5a5 r13 + test_gr_a5a5 r14 + + pass + + exit 0 + +lsrc: .long _lsrc +wsrc: .long _wsrc +bsrc: .long _bsrc + +ldst: .long _ldst +wdst: .long _wdst +bdst: .long _bdst + Index: sim/testsuite/sim/sh/movi.s =================================================================== RCS file: /cvs/uberbaum/./sim/testsuite/sim/sh/movi.s,v retrieving revision 1.1 diff -u -p -r1.1 movi.s --- sim/testsuite/sim/sh/movi.s 12 Feb 2004 22:29:48 -0000 1.1 +++ sim/testsuite/sim/sh/movi.s 29 Jul 2004 05:48:54 -0000 @@ -1,7 +1,6 @@ -# sh testcase for mov <#imm> -# mach: all +# sh testcase for all mov <#imm> instructions +# mach: sh # as(sh): -defsym sim_cpu=0 -# as(shdsp): -defsym sim_cpu=1 -dsp .include "testutils.inc" @@ -28,6 +27,48 @@ mov_i_reg: # Test test_gr_a5a5 r13 test_gr_a5a5 r14 +movi20_reg: # Test + set_grs_a5a5 + movi20 #-0x55555,r1 + + assertreg 0xfffaaaab, r1 + + test_gr_a5a5 r0 + test_gr_a5a5 r2 + test_gr_a5a5 r3 + test_gr_a5a5 r4 + test_gr_a5a5 r5 + test_gr_a5a5 r6 + test_gr_a5a5 r7 + test_gr_a5a5 r8 + test_gr_a5a5 r9 + test_gr_a5a5 r10 + test_gr_a5a5 r11 + test_gr_a5a5 r12 + test_gr_a5a5 r13 + test_gr_a5a5 r14 + +movi20s_reg: # Test << 8 + set_grs_a5a5 + movi20s #-0x5555500,r1 + + assertreg 0xfaaaab00, r1 + + test_gr_a5a5 r0 + test_gr_a5a5 r2 + test_gr_a5a5 r3 + test_gr_a5a5 r4 + test_gr_a5a5 r5 + test_gr_a5a5 r6 + test_gr_a5a5 r7 + test_gr_a5a5 r8 + test_gr_a5a5 r9 + test_gr_a5a5 r10 + test_gr_a5a5 r11 + test_gr_a5a5 r12 + test_gr_a5a5 r13 + test_gr_a5a5 r14 + pass exit 0 Index: sim/testsuite/sim/sh/mulr.s =================================================================== RCS file: sim/testsuite/sim/sh/mulr.s diff -N sim/testsuite/sim/sh/mulr.s --- /dev/null 1 Jan 1970 00:00:00 -0000 +++ sim/testsuite/sim/sh/mulr.s 29 Jul 2004 05:48:54 -0000 @@ -0,0 +1,162 @@ +# sh testcase for mulr +# mach: all +# as(sh): -defsym sim_cpu=0 +# as(shdsp): -defsym sim_cpu=1 -dsp + + .include "testutils.inc" + + start + +mulr_1: ! multiply by one + set_grs_a5a5 + mov #1, r0 + mulr r0, r1 + assertreg0 1 + test_gr_a5a5 r1 + test_gr_a5a5 r2 + test_gr_a5a5 r3 + test_gr_a5a5 r4 + test_gr_a5a5 r5 + test_gr_a5a5 r6 + test_gr_a5a5 r7 + test_gr_a5a5 r8 + test_gr_a5a5 r9 + test_gr_a5a5 r10 + test_gr_a5a5 r11 + test_gr_a5a5 r12 + test_gr_a5a5 r13 + test_gr_a5a5 r14 + +mulr_2: ! multiply by two + set_grs_a5a5 + mov #2, r0 + mov #12, r1 + mulr r0, r1 + assertreg0 2 + assertreg 24, r1 + test_gr_a5a5 r2 + test_gr_a5a5 r3 + test_gr_a5a5 r4 + test_gr_a5a5 r5 + test_gr_a5a5 r6 + test_gr_a5a5 r7 + test_gr_a5a5 r8 + test_gr_a5a5 r9 + test_gr_a5a5 r10 + test_gr_a5a5 r11 + test_gr_a5a5 r12 + test_gr_a5a5 r13 + test_gr_a5a5 r14 + +mulr_3: ! multiply five by five + set_grs_a5a5 + mov #5, r0 + mov #5, r1 + mulr r0, r1 + assertreg0 5 + assertreg 25, r1 + test_gr_a5a5 r2 + test_gr_a5a5 r3 + test_gr_a5a5 r4 + test_gr_a5a5 r5 + test_gr_a5a5 r6 + test_gr_a5a5 r7 + test_gr_a5a5 r8 + test_gr_a5a5 r9 + test_gr_a5a5 r10 + test_gr_a5a5 r11 + test_gr_a5a5 r12 + test_gr_a5a5 r13 + test_gr_a5a5 r14 + + +mulr_4: ! multiply 127 by 127 + set_grs_a5a5 + mov #127, r0 + mov #127, r1 + mulr r0, r1 + assertreg0 127 + assertreg 0x3f01, r1 + test_gr_a5a5 r2 + test_gr_a5a5 r3 + test_gr_a5a5 r4 + test_gr_a5a5 r5 + test_gr_a5a5 r6 + test_gr_a5a5 r7 + test_gr_a5a5 r8 + test_gr_a5a5 r9 + test_gr_a5a5 r10 + test_gr_a5a5 r11 + test_gr_a5a5 r12 + test_gr_a5a5 r13 + test_gr_a5a5 r14 + +mulr_5: ! multiply -1 by -1 + set_grs_a5a5 + mov #-1, r0 + mov #-1, r1 + mulr r0, r1 + assertreg0 -1 + assertreg 1, r1 + test_gr_a5a5 r2 + test_gr_a5a5 r3 + test_gr_a5a5 r4 + test_gr_a5a5 r5 + test_gr_a5a5 r6 + test_gr_a5a5 r7 + test_gr_a5a5 r8 + test_gr_a5a5 r9 + test_gr_a5a5 r10 + test_gr_a5a5 r11 + test_gr_a5a5 r12 + test_gr_a5a5 r13 + test_gr_a5a5 r14 + +mulr_6: ! multiply 46340 by 46340 + set_grs_a5a5 + movi20 #46340, r0 + movi20 #46340, r1 + mulr r0, r1 + assertreg0 46340 + assertreg 0x7ffea810, r1 + test_gr_a5a5 r2 + test_gr_a5a5 r3 + test_gr_a5a5 r4 + test_gr_a5a5 r5 + test_gr_a5a5 r6 + test_gr_a5a5 r7 + test_gr_a5a5 r8 + test_gr_a5a5 r9 + test_gr_a5a5 r10 + test_gr_a5a5 r11 + test_gr_a5a5 r12 + test_gr_a5a5 r13 + test_gr_a5a5 r14 + +mulr_7: ! multiply 7ffff by 7ffff (overflow) + set_grs_a5a5 + movi20 #0x7ffff, r0 + movi20 #0x7ffff, r1 + mulr r0, r1 + assertreg0 0x7ffff + assertreg 0xfff00001, r1 + test_gr_a5a5 r2 + test_gr_a5a5 r3 + test_gr_a5a5 r4 + test_gr_a5a5 r5 + test_gr_a5a5 r6 + test_gr_a5a5 r7 + test_gr_a5a5 r8 + test_gr_a5a5 r9 + test_gr_a5a5 r10 + test_gr_a5a5 r11 + test_gr_a5a5 r12 + test_gr_a5a5 r13 + test_gr_a5a5 r14 + + + pass + + exit 0 + + \ No newline at end of file Index: sim/testsuite/sim/sh/pass.s =================================================================== RCS file: sim/testsuite/sim/sh/pass.s diff -N sim/testsuite/sim/sh/pass.s --- /dev/null 1 Jan 1970 00:00:00 -0000 +++ sim/testsuite/sim/sh/pass.s 29 Jul 2004 05:48:54 -0000 @@ -0,0 +1,14 @@ +# sh testcase, pass +# mach: all +# as(sh): -defsym sim_cpu=0 +# as(shdsp): -defsym sim_cpu=1 -dsp + + .include "testutils.inc" + + start + set_grs_a5a5 + test_grs_a5a5 + pass + + exit 0 + Index: sim/testsuite/sim/sh/pushpop.s =================================================================== RCS file: sim/testsuite/sim/sh/pushpop.s diff -N sim/testsuite/sim/sh/pushpop.s --- /dev/null 1 Jan 1970 00:00:00 -0000 +++ sim/testsuite/sim/sh/pushpop.s 29 Jul 2004 05:48:54 -0000 @@ -0,0 +1,146 @@ +# sh testcase for push/pop (mov,movml,movmu...) insns. +# mach: all +# as(sh): -defsym sim_cpu=0 +# as(shdsp): -defsym sim_cpu=1 -dsp + + .include "testutils.inc" + + start +movml_1: + set_greg 0, r0 + set_greg 1, r1 + set_greg 2, r2 + set_greg 3, r3 + set_greg 4, r4 + set_greg 5, r5 + set_greg 6, r6 + set_greg 7, r7 + set_greg 8, r8 + set_greg 9, r9 + set_greg 10, r10 + set_greg 11, r11 + set_greg 12, r12 + set_greg 13, r13 + set_greg 14, r14 + set_sreg 15, pr + + movml.l r15,@-r15 + + assertmem stackt-4, 15 + assertmem stackt-8, 14 + assertmem stackt-12, 13 + assertmem stackt-16, 12 + assertmem stackt-20, 11 + assertmem stackt-24, 10 + assertmem stackt-28, 9 + assertmem stackt-32, 8 + assertmem stackt-36, 7 + assertmem stackt-40, 6 + assertmem stackt-44, 5 + assertmem stackt-48, 4 + assertmem stackt-52, 3 + assertmem stackt-56, 2 + assertmem stackt-60, 1 + assertmem stackt-64, 0 + + assertreg0 0 + assertreg 1, r1 + assertreg 2, r2 + assertreg 3, r3 + assertreg 4, r4 + assertreg 5, r5 + assertreg 6, r6 + assertreg 7, r7 + assertreg 8, r8 + assertreg 9, r9 + assertreg 10, r10 + assertreg 11, r11 + assertreg 12, r12 + assertreg 13, r13 + assertreg 14, r14 + mov r15, r0 + assertreg0 stackt-64 + +movml_2: + set_grs_a5a5 + movml.l @r15+, r15 + assert_sreg 15, pr + assertreg0 0 + assertreg 1, r1 + assertreg 2, r2 + assertreg 3, r3 + assertreg 4, r4 + assertreg 5, r5 + assertreg 6, r6 + assertreg 7, r7 + assertreg 8, r8 + assertreg 9, r9 + assertreg 10, r10 + assertreg 11, r11 + assertreg 12, r12 + assertreg 13, r13 + assertreg 14, r14 + mov r15, r0 + assertreg0 stackt + +movmu_1: + set_grs_a5a5 + add #1,r14 + add #2,r13 + add #3,r12 + set_sreg 0xa5a5,pr + + movmu.l r12,@-r15 + + assert_sreg 0xa5a5,pr + assertreg 0xa5a5a5a6, r14 + assertreg 0xa5a5a5a7, r13 + assertreg 0xa5a5a5a8, r12 + test_gr_a5a5 r11 + test_gr_a5a5 r10 + test_gr_a5a5 r9 + test_gr_a5a5 r8 + test_gr_a5a5 r7 + test_gr_a5a5 r6 + test_gr_a5a5 r5 + test_gr_a5a5 r4 + test_gr_a5a5 r3 + test_gr_a5a5 r2 + test_gr_a5a5 r1 + test_gr_a5a5 r0 + mov r15, r0 + assertreg stackt-16, r0 + + assertmem stackt-4, 0xa5a5 + assertmem stackt-8, 0xa5a5a5a6 + assertmem stackt-12, 0xa5a5a5a7 + assertmem stackt-16, 0xa5a5a5a8 + +movmu_2: + set_grs_a5a5 + movmu.l @r15+,r12 + + assert_sreg 0xa5a5, pr + assertreg 0xa5a5a5a6, r14 + assertreg 0xa5a5a5a7, r13 + assertreg 0xa5a5a5a8, r12 + test_gr_a5a5 r11 + test_gr_a5a5 r10 + test_gr_a5a5 r9 + test_gr_a5a5 r8 + test_gr_a5a5 r7 + test_gr_a5a5 r6 + test_gr_a5a5 r5 + test_gr_a5a5 r4 + test_gr_a5a5 r3 + test_gr_a5a5 r2 + test_gr_a5a5 r1 + test_gr_a5a5 r0 + mov r15, r0 + assertreg stackt, r0 + + pass + + exit 0 + + \ No newline at end of file Index: sim/testsuite/sim/sh/resbank.s =================================================================== RCS file: sim/testsuite/sim/sh/resbank.s diff -N sim/testsuite/sim/sh/resbank.s --- /dev/null 1 Jan 1970 00:00:00 -0000 +++ sim/testsuite/sim/sh/resbank.s 29 Jul 2004 05:48:54 -0000 @@ -0,0 +1,268 @@ +# sh testcase for ldbank stbank resbank +# mach: all +# as(sh): -defsym sim_cpu=0 +# as(shdsp): -defsym sim_cpu=1 -dsp + + .include "testutils.inc" + + .macro SEND reg bankno regno + set_greg ((\bankno << 7) + (\regno << 2)), \reg + .endm + + start + +stbank_1: + set_grs_a5a5 + mov #0, r0 + SEND r1, 0, 0 + stbank r0, @r1 + mov #1, r0 + SEND r1, 0, 1 + stbank r0, @r1 + mov #2, r0 + SEND r1, 0, 2 + stbank r0, @r1 + mov #3, r0 + SEND r1, 0, 3 + stbank r0, @r1 + mov #4, r0 + SEND r1, 0, 4 + stbank r0, @r1 + mov #5, r0 + SEND r1, 0, 5 + stbank r0, @r1 + mov #6, r0 + SEND r1, 0, 6 + stbank r0, @r1 + mov #7, r0 + SEND r1, 0, 7 + stbank r0, @r1 + mov #8, r0 + SEND r1, 0, 8 + stbank r0, @r1 + mov #9, r0 + SEND r1, 0, 9 + stbank r0, @r1 + mov #10, r0 + SEND r1, 0, 10 + stbank r0, @r1 + mov #11, r0 + SEND r1, 0, 11 + stbank r0, @r1 + mov #12, r0 + SEND r1, 0, 12 + stbank r0, @r1 + mov #13, r0 + SEND r1, 0, 13 + stbank r0, @r1 + mov #14, r0 + SEND r1, 0, 14 + stbank r0, @r1 + mov #15, r0 + SEND r1, 0, 15 + stbank r0, @r1 + mov #16, r0 + SEND r1, 0, 16 + stbank r0, @r1 + mov #17, r0 + SEND r1, 0, 17 + stbank r0, @r1 + mov #18, r0 + SEND r1, 0, 18 + stbank r0, @r1 + mov #19, r0 + SEND r1, 0, 19 + stbank r0, @r1 + + assertreg0 19 + assertreg 19 << 2, r1 + test_gr_a5a5 r2 + test_gr_a5a5 r3 + test_gr_a5a5 r4 + test_gr_a5a5 r5 + test_gr_a5a5 r6 + test_gr_a5a5 r7 + test_gr_a5a5 r8 + test_gr_a5a5 r9 + test_gr_a5a5 r10 + test_gr_a5a5 r11 + test_gr_a5a5 r12 + test_gr_a5a5 r13 + test_gr_a5a5 r14 + +ldbank_1: + set_grs_a5a5 + SEND r1, 0, 0 + ldbank @r1, r0 + assertreg0 0 + SEND r1, 0, 1 + ldbank @r1, r0 + assertreg0 1 + SEND r1, 0, 2 + ldbank @r1, r0 + assertreg0 2 + SEND r1, 0, 3 + ldbank @r1, r0 + assertreg0 3 + SEND r1, 0, 4 + ldbank @r1, r0 + assertreg0 4 + SEND r1, 0, 5 + ldbank @r1, r0 + assertreg0 5 + SEND r1, 0, 6 + ldbank @r1, r0 + assertreg0 6 + SEND r1, 0, 7 + ldbank @r1, r0 + assertreg0 7 + SEND r1, 0, 8 + ldbank @r1, r0 + assertreg0 8 + SEND r1, 0, 9 + ldbank @r1, r0 + assertreg0 9 + SEND r1, 0, 10 + ldbank @r1, r0 + assertreg0 10 + SEND r1, 0, 11 + ldbank @r1, r0 + assertreg0 11 + SEND r1, 0, 12 + ldbank @r1, r0 + assertreg0 12 + SEND r1, 0, 13 + ldbank @r1, r0 + assertreg0 13 + SEND r1, 0, 14 + ldbank @r1, r0 + assertreg0 14 + SEND r1, 0, 15 + ldbank @r1, r0 + assertreg0 15 + SEND r1, 0, 16 + ldbank @r1, r0 + assertreg0 16 + SEND r1, 0, 17 + ldbank @r1, r0 + assertreg0 17 + SEND r1, 0, 18 + ldbank @r1, r0 + assertreg0 18 + SEND r1, 0, 19 + ldbank @r1, r0 + assertreg0 19 + + assertreg (19 << 2), r1 + test_gr_a5a5 r2 + test_gr_a5a5 r3 + test_gr_a5a5 r4 + test_gr_a5a5 r5 + test_gr_a5a5 r6 + test_gr_a5a5 r7 + test_gr_a5a5 r8 + test_gr_a5a5 r9 + test_gr_a5a5 r10 + test_gr_a5a5 r11 + test_gr_a5a5 r12 + test_gr_a5a5 r13 + test_gr_a5a5 r14 + +resbank_1: + set_grs_a5a5 + mov #1, r0 + trapa #13 ! magic trap, sets ibnr + + resbank + + assertreg0 0 + assertreg 1, r1 + assertreg 2, r2 + assertreg 3, r3 + assertreg 4, r4 + assertreg 5, r5 + assertreg 6, r6 + assertreg 7, r7 + assertreg 8, r8 + assertreg 9, r9 + assertreg 10, r10 + assertreg 11, r11 + assertreg 12, r12 + assertreg 13, r13 + assertreg 14, r14 + assert_sreg 15, mach + assert_sreg 17, pr + assert_creg 18, gbr + assert_sreg 19, macl + +resbank_2: + set_grs_a5a5 + movi20 #555, r0 + mov.l r0, @-r15 + add #-1, r0 + mov.l r0, @-r15 + add #-1, r0 + mov.l r0, @-r15 + add #-1, r0 + mov.l r0, @-r15 + add #-1, r0 + mov.l r0, @-r15 + add #-1, r0 + mov.l r0, @-r15 + add #-1, r0 + mov.l r0, @-r15 + add #-1, r0 + mov.l r0, @-r15 + add #-1, r0 + mov.l r0, @-r15 + add #-1, r0 + mov.l r0, @-r15 + add #-1, r0 + mov.l r0, @-r15 + add #-1, r0 + mov.l r0, @-r15 + add #-1, r0 + mov.l r0, @-r15 + add #-1, r0 + mov.l r0, @-r15 + add #-1, r0 + mov.l r0, @-r15 + add #-1, r0 + mov.l r0, @-r15 + add #-1, r0 + mov.l r0, @-r15 + add #-1, r0 + mov.l r0, @-r15 + add #-1, r0 + mov.l r0, @-r15 + + set_sr_bit (1 << 14) ! set BO + + resbank + + assert_sreg 555, macl + assert_sreg 554, mach + assert_creg 553, gbr + assert_sreg 552, pr + assertreg 551, r14 + assertreg 550, r13 + assertreg 549, r12 + assertreg 548, r11 + assertreg 547, r10 + assertreg 546, r9 + assertreg 545, r8 + assertreg 544, r7 + assertreg 543, r6 + assertreg 542, r5 + assertreg 541, r4 + assertreg 540, r3 + assertreg 539, r2 + assertreg 538, r1 + assertreg0 537 + + mov r15, r0 + assertreg0 stackt + + pass + + exit 0 Index: sim/testsuite/sim/sh/testutils.inc =================================================================== RCS file: /cvs/uberbaum/./sim/testsuite/sim/sh/testutils.inc,v retrieving revision 1.3 diff -u -p -r1.3 testutils.inc --- sim/testsuite/sim/sh/testutils.inc 12 Feb 2004 22:29:48 -0000 1.3 +++ sim/testsuite/sim/sh/testutils.inc 29 Jul 2004 05:48:54 -0000 @@ -205,6 +205,19 @@ main: bra mfail nop .endm + # Branch if false -- 8k range + .macro bf8k label + bt .Lbf8k\@ + bra \label +.Lbf8k\@: + .endm + + # Branch if true -- 8k range + .macro bt8k label + bf .Lbt8k\@ + bra \label +.Lbt8k\@: + .endm # Assert value of register (any general register but r0) # Preserves r0 on stack, restores it on success. @@ -589,3 +602,16 @@ set_greg\@: lds r0, dsr pop r0 .endm + + .macro assertmem addr val + push r0 + mov.l .Laddr\@, r0 + mov.l @r0, r0 + assertreg0 \val + bra .Lam\@ + nop + .align 2 +.Laddr\@: + .long \addr +.Lam\@: pop r0 + .endm