Index: sim/testsuite/sim/h8300/ChangeLog
from  Alexandre Oliva  <aoliva@redhat.com>

	2004-06-17  Alexandre Oliva  <aoliva@redhat.com>
	* band.s, biand.s: imm3_abs16 is not available on h8300h.
	* bset.s: Likewise.  Ditto for rn_abs32.

Index: sim/testsuite/sim/h8300/band.s
===================================================================
RCS file: /cvs/uberbaum/./sim/testsuite/sim/h8300/band.s,v
retrieving revision 1.1
diff -u -p -r1.1 band.s
--- sim/testsuite/sim/h8300/band.s 19 Jun 2003 02:40:12 -0000 1.1
+++ sim/testsuite/sim/h8300/band.s 21 Jun 2004 10:42:48 -0000
@@ -104,7 +104,7 @@ band_imm3_abs8:
 
 	test_grs_a5a5		; general registers should not be changed.
 
-.if (sim_cpu)			; non-zero means not h8300
+.if (sim_cpu > h8300h)
 band_imm3_abs16:
 	set_grs_a5a5
 	set_ccr_zero
@@ -314,7 +314,7 @@ bld_imm3_abs8:
 
 	test_grs_a5a5		; general registers should not be changed.
 
-.if (sim_cpu)			; non-zero means not h8300
+.if (sim_cpu > h8300h)
 bld_imm3_abs16:
 	set_grs_a5a5
 	set_ccr_zero
@@ -491,7 +491,7 @@ btst_imm3_abs8:
 
 	test_grs_a5a5		; general registers should not be changed.
 
-.if (sim_cpu)			; non-zero means not h8300
+.if (sim_cpu > h8300h)
 btst_imm3_abs16:
 	set_grs_a5a5
 	set_ccr_zero
Index: sim/testsuite/sim/h8300/biand.s
===================================================================
RCS file: /cvs/uberbaum/./sim/testsuite/sim/h8300/biand.s,v
retrieving revision 1.1
diff -u -p -r1.1 biand.s
--- sim/testsuite/sim/h8300/biand.s 19 Jun 2003 02:40:12 -0000 1.1
+++ sim/testsuite/sim/h8300/biand.s 21 Jun 2004 10:42:48 -0000
@@ -104,7 +104,7 @@ biand_imm3_abs8:
 
 	test_grs_a5a5		; general registers should not be changed.
 
-.if (sim_cpu)			; non-zero means not h8300
+.if (sim_cpu > h8300h)
 biand_imm3_abs16:
 	set_grs_a5a5
 	set_ccr_zero
@@ -314,7 +314,7 @@ bild_imm3_abs8:
 
 	test_grs_a5a5		; general registers should not be changed.
 
-.if (sim_cpu)			; non-zero means not h8300
+.if (sim_cpu > h8300h)
 bild_imm3_abs16:
 	set_grs_a5a5
 	set_ccr_zero
Index: sim/testsuite/sim/h8300/bset.s
===================================================================
RCS file: /cvs/uberbaum/./sim/testsuite/sim/h8300/bset.s,v
retrieving revision 1.2
diff -u -p -r1.2 bset.s
--- sim/testsuite/sim/h8300/bset.s 19 Jun 2003 02:40:12 -0000 1.2
+++ sim/testsuite/sim/h8300/bset.s 21 Jun 2004 10:42:51 -0000
@@ -263,6 +263,7 @@ bclr_imm3_ind:	
 	test_gr_a5a5 6
 	test_gr_a5a5 7
 
+.if (sim_cpu > h8300h)
 bset_imm3_abs16:
 	set_grs_a5a5		; Fill all general regs with a fixed pattern
 
@@ -383,6 +384,7 @@ bclr_imm3_abs16:	
 	test_gr_a5a5 6
 	test_gr_a5a5 7
 .endif
+.endif
 
 bset_rs8_rd8:
 	set_grs_a5a5		; Fill all general regs with a fixed pattern
@@ -644,6 +646,7 @@ bclr_rs8_ind:	
 	test_gr_a5a5 6
 	test_gr_a5a5 7
 
+.if (sim_cpu > h8300h)
 bset_rs8_abs32:
 	set_grs_a5a5		; Fill all general regs with a fixed pattern
 
@@ -780,6 +783,7 @@ bclr_rs8_abs32:	
 	test_gr_a5a5 6
 	test_gr_a5a5 7
 .endif
+.endif
 
 .if (sim_cpu == h8sx)
 bset_eq_imm3_abs16: