From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 92697 invoked by alias); 8 Dec 2018 20:25:53 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Received: (qmail 92614 invoked by uid 89); 8 Dec 2018 20:25:42 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-26.9 required=5.0 tests=BAYES_00,GIT_PATCH_0,GIT_PATCH_1,GIT_PATCH_2,GIT_PATCH_3,RCVD_IN_DNSWL_NONE autolearn=ham version=3.3.2 spammy=floatingpoint, HX-Received:181c, gdb_test, Hx-languages-length:1491 X-HELO: mail-pf1-f175.google.com Received: from mail-pf1-f175.google.com (HELO mail-pf1-f175.google.com) (209.85.210.175) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Sat, 08 Dec 2018 20:25:41 +0000 Received: by mail-pf1-f175.google.com with SMTP id c123so3526192pfb.0 for ; Sat, 08 Dec 2018 12:25:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=date:subject:in-reply-to:cc:from:to:message-id:mime-version :content-transfer-encoding; bh=u4yxjszYrZxo5x1SRD8AKdj9lpZv2GVs88hya1hqpx0=; b=BzoHGs3/3PQ5v2NaWXH5VYvckodrAz+0FXMWkXUf60eZPqWFaRs/nwLopey6vkPcVq eeX3XfHgmqVKNQJ4gBC4so0ZxF/9a8E32xl6t6qTYP4IWRaL6drrfAnZO1qZ0pzHpMrW 7dimL1SBv/dg2ZROtmwkp0G+FKnnhSoN7WI+TD6ateeFkqww/79sSWoH/nnVkOJdvkK/ JMQAAI1NYftMWXSW90QxZkM72ucuSbB405DRc6KcbGsLN1sLIJpVDkez6bUVLPZ36gj7 mQNf2akos1rWu8MHpEmu/rnVuJYuGwQxXh/sU+n2IKb0RvMcFo/+EMhBlCeardNr8WJ0 Dgpg== Return-Path: Received: from localhost ([216.3.10.7]) by smtp.gmail.com with ESMTPSA id r66sm9102511pfk.157.2018.12.08.12.25.38 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 08 Dec 2018 12:25:38 -0800 (PST) Date: Sat, 08 Dec 2018 20:25:00 -0000 X-Google-Original-Date: Sat, 08 Dec 2018 12:22:58 PST (-0800) Subject: Re: [PATCH] gdb/riscv: Update test to handle targets without an fpu In-Reply-To: <20181204132934.26104-1-andrew.burgess@embecosm.com> CC: gdb-patches@sourceware.org, Jim Wilson , jhb@FreeBSD.org, andrew.burgess@embecosm.com From: Palmer Dabbelt To: andrew.burgess@embecosm.com Message-ID: Mime-Version: 1.0 (MHng) Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit X-SW-Source: 2018-12/txt/msg00109.txt.bz2 On Tue, 04 Dec 2018 05:29:34 PST (-0800), andrew.burgess@embecosm.com wrote: > The FPU is optional on RISC-V. The gdb.base/float.exp test currently > assumes that an fpu is always available on RISC-V. Update the test so > that this is not the case. > > gdb/testsuite/ChangeLog: > > * gdb.base/float.exp: Handle RISC-V targets without an FPU. > --- > gdb/testsuite/ChangeLog | 4 ++++ > gdb/testsuite/gdb.base/float.exp | 10 +++++++++- > 2 files changed, 13 insertions(+), 1 deletion(-) > > diff --git a/gdb/testsuite/gdb.base/float.exp b/gdb/testsuite/gdb.base/float.exp > index 71d3f60c499..23d68a13dfc 100644 > --- a/gdb/testsuite/gdb.base/float.exp > +++ b/gdb/testsuite/gdb.base/float.exp > @@ -111,7 +111,15 @@ if { [is_aarch64_target] } then { > } elseif [istarget "sparc*-*-*"] then { > gdb_test "info float" "f0.*f1.*f31.*d0.*d30.*" "info float" > } elseif [istarget "riscv*-*-*"] then { > - gdb_test "info float" "ft0.*ft1.*ft11.*fflags.*frm.*fcsr.*" "info float" > + # RISC-V may or may not have an FPU > + gdb_test_multiple "info float" "info float" { > + -re "ft0.*ft1.*ft11.*fflags.*frm.*fcsr.*$gdb_prompt $" { > + pass "info float (with FPU)" > + } > + -re "No floating.point info available for this processor.*$gdb_prompt $" { > + pass "info float (without FPU)" > + } > + } > } else { > gdb_test "info float" "No floating.point info available for this processor." "info float (unknown target)" > } Thanks!