From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 102396 invoked by alias); 28 Sep 2018 18:25:37 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Received: (qmail 102347 invoked by uid 89); 28 Sep 2018 18:25:36 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-3.2 required=5.0 tests=AWL,BAYES_00,RCVD_IN_DNSWL_NONE,SPF_PASS autolearn=ham version=3.3.2 spammy=falling, mature, H*RU:209.85.210.194, Hx-spam-relays-external:209.85.210.194 X-HELO: mail-pf1-f194.google.com Received: from mail-pf1-f194.google.com (HELO mail-pf1-f194.google.com) (209.85.210.194) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Fri, 28 Sep 2018 18:25:35 +0000 Received: by mail-pf1-f194.google.com with SMTP id m77-v6so4853499pfi.8 for ; Fri, 28 Sep 2018 11:25:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=date:subject:in-reply-to:cc:from:to:message-id:mime-version :content-transfer-encoding; bh=ve4MUn9UGJE5XlAkitbzdH0Guui0Yl3WdIuestqHYAo=; b=FfA8mJJGwq6rj/oSLeaFTjUVE2UNEiqmmamXUBjKEmefwGLZhKJfY/ZpoO5FOFW8S3 qNx4noZmrPyKqwq0eZaen7WyIvURe/E7Q5eTkpbhJZGiOK72wlUWuXsTyAHlIfV5eso/ mLdJQ3c55d4T+Lr8fG4KB7OK9Nyo5vQekjTOp3Fudy+s+6SqKJLVwU74imXYA5s4vntY IclkafqxrdvOm1UHj48UsYLK5MfZBDFAgv8Wzta0EjBLBSQ0J7PIaoPweoVDa+8wjvd3 8BquB1qZlFLJthV6MUZjBrnYY91YPfyUvtZG4P1JMJkh3enSbgYuea0DSKk6e4NXIdYr XojA== Return-Path: Received: from localhost ([12.206.222.5]) by smtp.gmail.com with ESMTPSA id 22-v6sm9154849pfl.126.2018.09.28.11.25.31 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 28 Sep 2018 11:25:32 -0700 (PDT) Date: Fri, 28 Sep 2018 18:25:00 -0000 X-Google-Original-Date: Fri, 28 Sep 2018 11:25:30 PDT (-0700) Subject: Re: [PATCH 2/4] Fall back to a default value of 0 for the MISA register. In-Reply-To: <20180928094355.GS5952@embecosm.com> CC: Jim Wilson , jhb@freebsd.org, gdb-patches@sourceware.org From: Palmer Dabbelt To: andrew.burgess@embecosm.com Message-ID: Mime-Version: 1.0 (MHng) Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit X-SW-Source: 2018-09/txt/msg00907.txt.bz2 On Fri, 28 Sep 2018 02:43:55 PDT (-0700), andrew.burgess@embecosm.com wrote: > * Jim Wilson [2018-09-21 10:25:47 -0700]: > >> On Fri, Sep 21, 2018 at 2:27 AM Andrew Burgess >> wrote: >> > Jim: Given that we agree that targets should definitely provide a >> > value for misa, at a minimum just returning the constant 0. But, >> > given that GDB already defaults to 0 in some cases anyway. And the >> > spec is quite clear that 0 is the right default value in the absence >> > of anything better, would you be OK with a patch that does return a >> > default of 0? >> >> The patch to decode an instruction to decide whether to use a >> compressed breakpoint or not solves my main problem. There is also >> the issue of finding FP register size, but since we only support >> rv64gc at the moment, it isn't a serious problem. > > I regularly test embeded RiscV against: > > rv32im rv32imc rv32imf rv32imfc > > rv64im rv64imc rv64imfd rv64imfdc > > with the last one of those being closes to rv64gc. The pass rate is > broadly the same against all of these targets, so right now I consider > these equally supported for baremetal. For those uniniated in RISC-V, "rv64gc" is the same as "rv64imafdc" (the G is short for IMAFD). Importantly it's probably close enough for embedded GDB testing, as all you're missing is the A extension and GDB doesn't really care about atomics. > I understand Linux support might be different. Right now all that's really supported in Linux land is rv64gc. The kernel should also build on rv64imac, rv32gc, and rv32imac but they're much less mature. The upstream glibc port supports rv64gc and rv64imac, but we test those only on rv64gc kernels. We try our best to avoid breaking the other targets, but until we get some better CI up and running I'd expect that non-rv64gc targets do keep falling apart. We're working on it :) On Linux you should be able to look at the HWCAP in the auxvec, which is meant to tell you what user state is available. The code to fill this out is here https://git.kernel.org/pub/scm/linux/kernel/git/palmer/riscv-linux.git/tree/arch/riscv/kernel/cpufeature.c#n26 > > Thanks, > > Andrew > > >> Also, I think the >> linker kernel may already be passing FP info via auxvec/hwcap, so I >> think we already have an alternate solution for that which just needs >> to be implemented. I haven't looked at that yet. So yes, I think it >> is OK to start defaulting misa to 0. >> >> FYI I have a qemu patch, which I may someday finish, that adds XML >> register support to the RISC-V qemu system-mode port, which allows >> qemu to provide a correct value of misa. We know that misa accesses >> already work with embedded targets via OpenOCD. So it is just linux >> and freebsd that need to worry about misa. >> >> The qemu patch is here, though it looks like github is confused by >> rebasing and the patch isn't readable anymore. >> https://github.com/riscv/riscv-qemu/pull/160 >> I'll have to figure out how to fix that. >> >> Jim