From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 20293 invoked by alias); 8 Nov 2018 19:32:57 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Received: (qmail 19985 invoked by uid 89); 8 Nov 2018 19:32:57 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-3.2 required=5.0 tests=AWL,BAYES_00,RCVD_IN_DNSWL_NONE,SPF_PASS autolearn=ham version=3.3.2 spammy=HX-Received:sk:w11-v6m, Hx-languages-length:1690, HX-HELO:sk:mail-pl, PST X-HELO: mail-pl1-f176.google.com Received: from mail-pl1-f176.google.com (HELO mail-pl1-f176.google.com) (209.85.214.176) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Thu, 08 Nov 2018 19:32:55 +0000 Received: by mail-pl1-f176.google.com with SMTP id f12-v6so8818397plo.1 for ; Thu, 08 Nov 2018 11:32:55 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=date:subject:in-reply-to:cc:from:to:message-id:mime-version :content-transfer-encoding; bh=il18WDoRII8MkDs0HS+oQH/XBFtImvM04tOO4fri7xg=; b=MmEi7uyyF0gLEoH7VO3zvf4N/SAJ+b7Gp4e7c5nWMrPTWOFxmX228JTw8w6UWtMwdW A0lKvFgkzcw7/sd+d2E/HDSrdVmy51mx7A2lCcGO1KadOS0+ElOvStJ9lO8X/iwDyWiX /HqdVbNv0+bZH1ZBNEujmafUMbxHCE1ocotYk3/FLIPK1K27b7kQrKU29hkLiTBaNRVa S+W8k5wuSS/dF0cid/8FclV10tx9YHE7+Z++azdYcPQwki1bfC5ykH3kAEzSjsGD6CcU eV74DZiihOciSkwjVW9PYuK4naulj/DqmRNHaJhSTxnxmtdgKhm+CCDhKvVuOzKgpPtu U6mg== Return-Path: Received: from localhost ([12.206.222.5]) by smtp.gmail.com with ESMTPSA id u5-v6sm3933463pgk.46.2018.11.08.11.32.52 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 08 Nov 2018 11:32:53 -0800 (PST) Date: Thu, 08 Nov 2018 19:32:00 -0000 X-Google-Original-Date: Thu, 08 Nov 2018 11:17:06 PST (-0800) Subject: Re: [RFC] gdb/riscv: Add target description support In-Reply-To: CC: andrew.burgess@embecosm.com, gdb-patches@sourceware.org, Jim Wilson From: Palmer Dabbelt To: jhb@FreeBSD.org Message-ID: Mime-Version: 1.0 (MHng) Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit X-SW-Source: 2018-11/txt/msg00130.txt.bz2 On Thu, 08 Nov 2018 10:32:57 PST (-0800), jhb@FreeBSD.org wrote: > On 11/8/18 8:07 AM, Andrew Burgess wrote: >> This commit adds target description support for riscv. >> >> I've used the split feature approach for specifying the architectural >> features, and the CSR feature is auto-generated from the riscv-opc.h >> header file. > > In general this looks fine to me (as far as I am familiar with the > target descriptions). The only possible question/comment I have is if > you considered describing fields of specific registers such as the FP > status registers or MSTATUS, etc. as fields in the XML to replace the > current special cases in riscv_print_one_register_info(). I think the > XML can't handle enum values as riscv_print_one_register_info() uses for > some cases, but I think it would be able to handle many of the special > cases in that function. > > Some related-ish questions (though not about this patch): I wonder if we > can do things with pseudo registers to automatically derive FFLAGS and > FRM if a target provides FCSR. > > One more note: AFAIU, 1.10 of the privilege spec removed hypervisor mode > with the intention of implementing virtualization support differently. > We might want to remove the references to hypervisor mode from riscv-tdep.c > as a result? The only reference I see is in the PRV decoding, which I think is OK: while the spec doesn't mention hypervisor mode any more, the bit pattern is still there and an upcoming spec will add it back in. I believe the official name is now "hypervisor-extended supervisor mode" but since that's a bit of a mouthfull I still call it hypervisor mode :)