From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 114227 invoked by alias); 9 Apr 2018 21:28:37 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Received: (qmail 114211 invoked by uid 89); 9 Apr 2018 21:28:36 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-25.9 required=5.0 tests=AWL,BAYES_00,GIT_PATCH_0,GIT_PATCH_1,GIT_PATCH_2,GIT_PATCH_3,RCVD_IN_DNSWL_NONE,SPF_PASS autolearn=ham version=3.3.2 spammy=dirty, flip, H*RU:209.85.160.66, Hx-spam-relays-external:209.85.160.66 X-HELO: mail-pl0-f66.google.com Received: from mail-pl0-f66.google.com (HELO mail-pl0-f66.google.com) (209.85.160.66) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Mon, 09 Apr 2018 21:28:35 +0000 Received: by mail-pl0-f66.google.com with SMTP id c7-v6so2733012plr.5 for ; Mon, 09 Apr 2018 14:28:35 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:subject:in-reply-to:cc:from:to:message-id :mime-version:content-transfer-encoding; bh=LYmYFyOqEfKWCwMqWwyvl3w7osUhyMBVq1rh9M0Z22g=; b=OMWBO53gqCLcdxE5koBwWdQxwrxAB4UbtXzwFbGdi2wdtvvYO4d+wtllbQcKbrQRyY NvSURqW87z/pS6YC3gA+kNM65dP2j3+q2h83yMdbM/ZPfeLKekx80XI0ZaLMEXFd7Ba3 mTMfMaZDv5cbjEnlr6Y0CcAlfOWw6vBtAJc44XtF6DMIf9O/xIMvnlIYwO4Kypx/Lsbr Jd/vqlDee5r+KP4zOGt/ndXfy3azDPwUxhvshtvICfwUbGPwxlxDDnyVdt9VCyy3IdZB hOfzTadNennKhvo3lkcZl6HjAqeGq5rspLcZncmCEzx+szbzJ3sQfEc0N03xFfdsRLgf 3ldg== X-Gm-Message-State: ALQs6tANn/wzGluwhmMVUnqDoS40gOzSNwqJXJo9AioOZIbYOBwWwBd5 s/8Nz7e7BIE+gZT1ukq22NnOxVmaxag= X-Google-Smtp-Source: AIpwx4+rs2dkMcTaCxiFk5mhZzq3UxCdvxzSpCeVMqB1BpbhXI4SAbv8MGabsjzy3K24SHvI9J4rqA== X-Received: by 2002:a17:902:5a8d:: with SMTP id r13-v6mr9900846pli.394.1523309313592; Mon, 09 Apr 2018 14:28:33 -0700 (PDT) Received: from localhost ([12.206.222.5]) by smtp.gmail.com with ESMTPSA id j15sm2095556pfn.62.2018.04.09.14.28.32 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 09 Apr 2018 14:28:33 -0700 (PDT) Date: Mon, 09 Apr 2018 21:28:00 -0000 X-Google-Original-Date: Mon, 09 Apr 2018 14:26:10 PDT (-0700) Subject: Re: [PATCH 2/3] gdb/testsuite: Filter out some registers for riscv In-Reply-To: <994fa101380c1495e1ca97a6dcbfdb3bd23ae173.1523286728.git.andrew.burgess@embecosm.com> CC: gdb-patches@sourceware.org, andrew.burgess@embecosm.com From: Palmer Dabbelt To: andrew.burgess@embecosm.com Message-ID: Mime-Version: 1.0 (MHng) Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit X-SW-Source: 2018-04/txt/msg00169.txt.bz2 On Mon, 09 Apr 2018 08:15:28 PDT (-0700), andrew.burgess@embecosm.com wrote: > On riscv the cycle counter, and instructions retired counter CSRs are > read only, this causes problems in the gdb.base/callfuncs.exp test, as > the values in these CSRs change after an inferior call, the check that > no target registers have been modified then fails. > > Luckily the test already has a mechanism in place for filtering out > registers that are modified (and can't be restored) by an inferior call, > so this commit adds the problem registers into this list for riscv. > > In the future we may end up needing to filter out more CSRs, but right > now, for the targets I have access too, these are the only ones causing > problems. > > gdb/testsuite/ChangeLog: > > * gdb.base/callfuncs.exp (fetch_all_registers): Add riscv register > filter pattern. > --- > gdb/testsuite/ChangeLog | 5 +++++ > gdb/testsuite/gdb.base/callfuncs.exp | 10 ++++++++++ > 2 files changed, 15 insertions(+) > > diff --git a/gdb/testsuite/gdb.base/callfuncs.exp b/gdb/testsuite/gdb.base/callfuncs.exp > index 94636938752..c5e39918c2a 100644 > --- a/gdb/testsuite/gdb.base/callfuncs.exp > +++ b/gdb/testsuite/gdb.base/callfuncs.exp > @@ -285,6 +285,16 @@ proc fetch_all_registers {test} { > } > exp_continue > } > + -re "^\(?:cycle\|instret\)\[ \t\]+\[^\r\n\]+\r\n" { > + if [istarget "riscv*-*-*"] { > + # Filter out the cycle counter and instructions > + # retired counter CSRs which are read-only, giving > + # spurious differences. > + } else { > + lappend all_registers_lines $expect_out(0,string) > + } > + exp_continue > + } > -re "^\[^ \t\]+\[ \t\]+\[^\r\n\]+\r\n" { > lappend all_registers_lines $expect_out(0,string) > exp_continue I think we only want to check the X and F registers here -- essentially every CSR is a special register where you can't really rely on the value not being changed somewhere by hardware. For example: * The interrupt pending bits could flip at any point, even if interrupts are disabled. * The floating-point dirty and exception state bits could change if a floating-point instruction executes. * The various trap CSRs (epc, badaddr, cause, etc) get set whenever a trap is executed.