From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 2712 invoked by alias); 29 Aug 2018 23:10:01 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Received: (qmail 2567 invoked by uid 89); 29 Aug 2018 23:10:01 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-25.7 required=5.0 tests=AWL,BAYES_00,GIT_PATCH_0,GIT_PATCH_1,GIT_PATCH_2,GIT_PATCH_3,RCVD_IN_DNSWL_NONE,SPF_PASS autolearn=ham version=3.3.2 spammy=H*M:4068, H*MI:4068, HX-Received:sk:s16-v6m X-HELO: mail-pl1-f172.google.com Received: from mail-pl1-f172.google.com (HELO mail-pl1-f172.google.com) (209.85.214.172) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Wed, 29 Aug 2018 23:09:59 +0000 Received: by mail-pl1-f172.google.com with SMTP id g23-v6so2944091plq.9 for ; Wed, 29 Aug 2018 16:09:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=date:subject:in-reply-to:cc:from:to:message-id:mime-version :content-transfer-encoding; bh=JlZgxV0YU3sNeBeVM6GLt6Nw1QW0S2j5vOpUckB1ZRs=; b=eu0IwPHqGLJro7sx08152x2EVO1bRBZuXu6SPNWUc9hsqIxd++3e9GqqRFVb9YnJfX h9GpNmU/jUGZ6TEL0FiCSCEbAaVk3u/SWY62y18+bwM6tqf6MyHnhCxMd1/+v9Y1DCNW 1tErpTeDOMutOq8PDx6XGOBEmhwdbxAT7jvQ+IeIF9apXsZ/z1WlpsGjGwzvJAW9NLgz br5p/RvYkw2fS2u96L+iUfTtOt02y4mbwF4UyYtv3HCSZbSAbNMdsEufuI9EGcE0PApi XGRWrPi4RcwuDXUfRDl4S+rOnJmqJFPy185Hbd44eczUofEBsmevBhhvpMlDX09vbbCv B1xQ== Return-Path: Received: from localhost ([12.206.222.5]) by smtp.gmail.com with ESMTPSA id y4-v6sm6709759pfm.137.2018.08.29.16.09.56 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 29 Aug 2018 16:09:56 -0700 (PDT) Date: Wed, 29 Aug 2018 23:10:00 -0000 X-Google-Original-Date: Wed, 29 Aug 2018 15:23:06 PDT (-0700) Subject: Re: [PATCH 2/4] gdb/riscv: Extend instruction decode to cover more instructions In-Reply-To: CC: gdb-patches@sourceware.org, Jim Wilson , andrew.burgess@embecosm.com From: Palmer Dabbelt To: andrew.burgess@embecosm.com Message-ID: Mime-Version: 1.0 (MHng) Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit X-SW-Source: 2018-08/txt/msg00787.txt.bz2 On Wed, 29 Aug 2018 09:40:52 PDT (-0700), andrew.burgess@embecosm.com wrote: > Extends the instruction decoder used during prologue scan and software > single step to cover more instructions. These instructions are > encountered when running the current GDB testsuite with the DWARF > stack unwinders turned off. > > gdb/ChangeLog: > > * riscv-tdep.c (riscv_insn::decode): Decode c.addi4spn, c.sd, > c.sw, c.swsp, and c.sdsp. > --- > gdb/ChangeLog | 5 +++++ > gdb/riscv-tdep.c | 40 ++++++++++++++++++++++++++++++++++++++-- > 2 files changed, 43 insertions(+), 2 deletions(-) > > diff --git a/gdb/riscv-tdep.c b/gdb/riscv-tdep.c > index 2f619c35e75..b4ac83a6dd9 100644 > --- a/gdb/riscv-tdep.c > +++ b/gdb/riscv-tdep.c > @@ -972,6 +972,31 @@ private: > m_imm.s = EXTRACT_STYPE_IMM (ival); > } > > + /* Helper for DECODE, decode 16-bit CS-type instruction. The immediate > + encoding is different for each CSS format instruction, so extracting I think you mean "each CS format" here -- it's true for CSS formats as well, just not relevant until below. > + the immediate is left up to the caller, who should pass the extracted > + immediate value through in IMM. */ > + void decode_cs_type_insn (enum opcode opcode, ULONGEST ival, int imm) > + { > + m_opcode = opcode; > + m_imm.s = imm; > + m_rs1 = decode_register_index_short (ival, OP_SH_CRS1S); > + m_rs2 = decode_register_index_short (ival, OP_SH_CRS2S); > + } > + > + /* Helper for DECODE, decode 16-bit CSS-type instruction. The immediate > + encoding is different for each CSS format instruction, so extracting > + the immediate is left up to the caller, who should pass the extracted > + immediate value through in IMM. */ > + void decode_css_type_insn (enum opcode opcode, ULONGEST ival, int imm) > + { > + m_opcode = opcode; > + m_imm.s = imm; > + m_rs1 = RISCV_SP_REGNUM; > + /* Not a compressed register number in this case. */ > + m_rs2 = decode_register_index (ival, OP_SH_CRS2); > + } > + > /* Helper for DECODE, decode 32-bit U-type instruction. */ > void decode_u_type_insn (enum opcode opcode, ULONGEST ival) > { > @@ -1165,14 +1190,25 @@ riscv_insn::decode (struct gdbarch *gdbarch, CORE_ADDR pc) > m_rd = m_rs1 = decode_register_index (ival, OP_SH_RD); > m_imm.s = EXTRACT_RVC_ADDI16SP_IMM (ival); > } > + else if (xlen < 16 && is_c_addi4spn_insn (ival)) > + { > + m_opcode = ADDI; > + m_rd = decode_register_index_short (ival, OP_SH_CRS2S); > + m_rs1 = RISCV_SP_REGNUM; > + m_imm.s = EXTRACT_RVC_ADDI4SPN_IMM (ival); I think this is OK: the immediate is actually unsigned, but it's only 10 bits long so it doesn't matter. > + } > else if (is_c_lui_insn (ival)) > m_opcode = OTHER; > /* C_SD and C_FSW have the same opcode. C_SD is RV64 and RV128 only, > and C_FSW is RV32 only. */ > else if (xlen != 4 && is_c_sd_insn (ival)) > - m_opcode = OTHER; > + decode_cs_type_insn (SD, ival, EXTRACT_RVC_LD_IMM (ival)); > else if (is_c_sw_insn (ival)) > - m_opcode = OTHER; > + decode_cs_type_insn (SW, ival, EXTRACT_RVC_LW_IMM (ival)); > + else if (is_c_swsp_insn (ival)) > + decode_css_type_insn (SW, ival, EXTRACT_RVC_SWSP_IMM (ival)); > + else if (is_c_sdsp_insn (ival)) > + decode_css_type_insn (SW, ival, EXTRACT_RVC_SDSP_IMM (ival)); > /* C_JR and C_MV have the same opcode. If RS2 is 0, then this is a C_JR. > So must try to match C_JR first as it ahs more bits in mask. */ > else if (is_c_jr_insn (ival))