From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 6745 invoked by alias); 18 Apr 2005 12:17:30 -0000 Mailing-List: contact gdb-patches-help@sources.redhat.com; run by ezmlm Precedence: bulk List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sources.redhat.com Received: (qmail 6658 invoked from network); 18 Apr 2005 12:17:17 -0000 Received: from unknown (HELO mx1.redhat.com) (66.187.233.31) by sourceware.org with SMTP; 18 Apr 2005 12:17:17 -0000 Received: from int-mx1.corp.redhat.com (int-mx1.corp.redhat.com [172.16.52.254]) by mx1.redhat.com (8.12.11/8.12.11) with ESMTP id j3ICHGNO009058 for ; Mon, 18 Apr 2005 08:17:16 -0400 Received: from pobox.surrey.redhat.com (pobox.surrey.redhat.com [172.16.10.17]) by int-mx1.corp.redhat.com (8.11.6/8.11.6) with ESMTP id j3ICHGO23567 for ; Mon, 18 Apr 2005 08:17:16 -0400 Received: from localhost.localdomain.redhat.com (vpnuser9.surrey.redhat.com [172.16.9.9]) by pobox.surrey.redhat.com (8.12.8/8.12.8) with ESMTP id j3ICHEkk026911 for ; Mon, 18 Apr 2005 13:17:15 +0100 To: gdb-patches@sources.redhat.com Subject: Fix compile time warnings in sim/arm/iwmmxt.c From: Nick Clifton Date: Mon, 18 Apr 2005 12:17:00 -0000 Message-ID: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii X-SW-Source: 2005-04/txt/msg00193.txt.bz2 Hi Guys, I am applying the patch below to fix some compile time warnings generated by a 4.0 version of GCC when compiling the ARM simulator source file iwmmxt.c. Cheers Nick sim/arm/ChangeLog 2005-04-18 Nick Clifton * iwmmxt.c (WMAC, WMADD): Move casts from the LHS of an assignment operator to the RHS. (WSLL, WSRA, WSRL, WUNPCKEH, WUNPACKEL): Use ULL suffix to indicate an unsigned long long constant. Index: sim/arm/iwmmxt.c =================================================================== RCS file: /cvs/src/src/sim/arm/iwmmxt.c,v retrieving revision 1.1 diff -c -3 -p -r1.1 iwmmxt.c *** sim/arm/iwmmxt.c 27 Mar 2003 17:13:33 -0000 1.1 --- sim/arm/iwmmxt.c 18 Apr 2005 12:12:22 -0000 *************** WMAC (ARMword instr) *** 2114,2120 **** s = (signed long) a * (signed long) b; ! (signed long long) t += s; } else { --- 2114,2120 ---- s = (signed long) a * (signed long) b; ! t = t + (ARMdword) s; } else { *************** WMAC (ARMword instr) *** 2130,2136 **** wR [BITS (12, 15)] = 0; if (BIT (21)) /* Signed. */ ! (signed long long) wR[BITS (12, 15)] += (signed long long) t; else wR [BITS (12, 15)] += t; --- 2130,2136 ---- wR [BITS (12, 15)] = 0; if (BIT (21)) /* Signed. */ ! wR[BITS (12, 15)] += t; else wR [BITS (12, 15)] += t; *************** WMADD (ARMword instr) *** 2166,2172 **** b = wRHALF (BITS (0, 3), i * 2); b = EXTEND16 (b); ! (signed long) s1 = a * b; a = wRHALF (BITS (16, 19), i * 2 + 1); a = EXTEND16 (a); --- 2166,2172 ---- b = wRHALF (BITS (0, 3), i * 2); b = EXTEND16 (b); ! s1 = (ARMdword) (a * b); a = wRHALF (BITS (16, 19), i * 2 + 1); a = EXTEND16 (a); *************** WMADD (ARMword instr) *** 2174,2180 **** b = wRHALF (BITS (0, 3), i * 2 + 1); b = EXTEND16 (b); ! (signed long) s2 = a * b; } else /* Unsigned. */ { --- 2174,2180 ---- b = wRHALF (BITS (0, 3), i * 2 + 1); b = EXTEND16 (b); ! s2 = (ARMdword) (a * b); } else /* Unsigned. */ { *************** WMADD (ARMword instr) *** 2183,2194 **** a = wRHALF (BITS (16, 19), i * 2); b = wRHALF (BITS ( 0, 3), i * 2); ! (unsigned long) s1 = a * b; a = wRHALF (BITS (16, 19), i * 2 + 1); b = wRHALF (BITS ( 0, 3), i * 2 + 1); ! (signed long) s2 = a * b; } r |= (ARMdword) ((s1 + s2) & 0xffffffff) << (i ? 32 : 0); --- 2183,2194 ---- a = wRHALF (BITS (16, 19), i * 2); b = wRHALF (BITS ( 0, 3), i * 2); ! s1 = (ARMdword) (a * b); a = wRHALF (BITS (16, 19), i * 2 + 1); b = wRHALF (BITS ( 0, 3), i * 2 + 1); ! s2 = (ARMdword) a * b; } r |= (ARMdword) ((s1 + s2) & 0xffffffff) << (i ? 32 : 0); *************** WSLL (ARMul_State * state, ARMword instr *** 2837,2843 **** if (shift > 63) r = 0; else ! r = ((wR[BITS (16, 19)] & 0xffffffffffffffff) << shift); SIMD64_SET (psr, NBIT64 (r), SIMD_NBIT); SIMD64_SET (psr, ZBIT64 (r), SIMD_ZBIT); --- 2837,2843 ---- if (shift > 63) r = 0; else ! r = ((wR[BITS (16, 19)] & 0xffffffffffffffffULL) << shift); SIMD64_SET (psr, NBIT64 (r), SIMD_NBIT); SIMD64_SET (psr, ZBIT64 (r), SIMD_ZBIT); *************** WSRA (ARMul_State * state, ARMword instr *** 2914,2922 **** case Dqual: if (shift > 63) ! r = (wR [BITS (16, 19)] & 0x8000000000000000) ? 0xffffffffffffffff : 0; else ! r = ((signed long long) (wR[BITS (16, 19)] & 0xffffffffffffffff) >> shift); SIMD64_SET (psr, NBIT64 (r), SIMD_NBIT); SIMD64_SET (psr, ZBIT64 (r), SIMD_ZBIT); break; --- 2914,2922 ---- case Dqual: if (shift > 63) ! r = (wR [BITS (16, 19)] & 0x8000000000000000ULL) ? 0xffffffffffffffffULL : 0; else ! r = ((signed long long) (wR[BITS (16, 19)] & 0xffffffffffffffffULL) >> shift); SIMD64_SET (psr, NBIT64 (r), SIMD_NBIT); SIMD64_SET (psr, ZBIT64 (r), SIMD_ZBIT); break; *************** WSRL (ARMul_State * state, ARMword instr *** 2985,2991 **** if (shift > 63) r = 0; else ! r = (wR [BITS (16, 19)] & 0xffffffffffffffff) >> shift; SIMD64_SET (psr, NBIT64 (r), SIMD_NBIT); SIMD64_SET (psr, ZBIT64 (r), SIMD_ZBIT); --- 2985,2991 ---- if (shift > 63) r = 0; else ! r = (wR [BITS (16, 19)] & 0xffffffffffffffffULL) >> shift; SIMD64_SET (psr, NBIT64 (r), SIMD_NBIT); SIMD64_SET (psr, ZBIT64 (r), SIMD_ZBIT); *************** WUNPCKEH (ARMul_State * state, ARMword i *** 3287,3293 **** r = wRWORD (BITS (16, 19), 1); if (BIT (21) && NBIT32 (r)) ! r |= 0xffffffff00000000; SIMD64_SET (psr, NBIT64 (r), SIMD_NBIT); SIMD64_SET (psr, ZBIT64 (r), SIMD_ZBIT); --- 3287,3293 ---- r = wRWORD (BITS (16, 19), 1); if (BIT (21) && NBIT32 (r)) ! r |= 0xffffffff00000000ULL; SIMD64_SET (psr, NBIT64 (r), SIMD_NBIT); SIMD64_SET (psr, ZBIT64 (r), SIMD_ZBIT); *************** WUNPCKEL (ARMul_State * state, ARMword i *** 3354,3360 **** r = wRWORD (BITS (16, 19), 0); if (BIT (21) && NBIT32 (r)) ! r |= 0xffffffff00000000; SIMD64_SET (psr, NBIT64 (r), SIMD_NBIT); SIMD64_SET (psr, ZBIT64 (r), SIMD_ZBIT); --- 3354,3360 ---- r = wRWORD (BITS (16, 19), 0); if (BIT (21) && NBIT32 (r)) ! r |= 0xffffffff00000000ULL; SIMD64_SET (psr, NBIT64 (r), SIMD_NBIT); SIMD64_SET (psr, ZBIT64 (r), SIMD_ZBIT);