From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 25786 invoked by alias); 6 Apr 2003 08:50:42 -0000 Mailing-List: contact gdb-patches-help@sources.redhat.com; run by ezmlm Precedence: bulk List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sources.redhat.com Received: (qmail 25777 invoked from network); 6 Apr 2003 08:50:39 -0000 Received: from unknown (HELO mx1.redhat.com) (66.187.233.31) by sources.redhat.com with SMTP; 6 Apr 2003 08:50:39 -0000 Received: from int-mx1.corp.redhat.com (int-mx1.corp.redhat.com [172.16.52.254]) by mx1.redhat.com (8.11.6/8.11.6) with ESMTP id h368ode26122 for ; Sun, 6 Apr 2003 04:50:39 -0400 Received: from pobox.corp.redhat.com (pobox.corp.redhat.com [172.16.52.156]) by int-mx1.corp.redhat.com (8.11.6/8.11.6) with ESMTP id h368ocJ28847; Sun, 6 Apr 2003 04:50:38 -0400 Received: from workshop.nickc.cambridge.redhat.com.redhat.com (vpn50-8.rdu.redhat.com [172.16.50.8]) by pobox.corp.redhat.com (8.11.6/8.11.6) with ESMTP id h368oY312600; Sun, 6 Apr 2003 04:50:36 -0400 To: Andrew Cagney Cc: gdb-patches@sources.redhat.com Subject: Re: RFA: v850 simulator does not sign extend first operand to divh References: <3E8F2760.6030005@redhat.com> From: Nick Clifton Date: Sun, 06 Apr 2003 08:50:00 -0000 In-Reply-To: <3E8F2760.6030005@redhat.com> Message-ID: User-Agent: Gnus/5.0808 (Gnus v5.8.8) Emacs/21.2 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii X-SW-Source: 2003-04/txt/msg00095.txt.bz2 Hi Andrew, > > 2003-04-03 Nick Clifton > > * simops.c (OP_40): Make divh sign extend its first operand. > > > > Yes, but can you please put the fixed code directly in v850.igen > (deleting OP_40): I have applied the patch below to do this. Why did you want the code moved ? Cheers Nick 2003-04-06 Nick Clifton * simops.c (OP_40): Delete. Move code to... * v850-igen.c (): ...Here. Sign extend the first operand. * simops.h (OP_40): Remove prototype. Index: sim/v850/simops.c =================================================================== RCS file: /cvs/src/src/sim/v850/simops.c,v retrieving revision 1.6 diff -c -3 -p -w -r1.6 simops.c *** sim/v850/simops.c 30 Nov 2002 18:01:30 -0000 1.6 --- sim/v850/simops.c 6 Apr 2003 08:46:41 -0000 *************** OP_6E0 () *** 771,820 **** return 4; } - /* divh reg1, reg2 */ - int - OP_40 () - { - unsigned int op0, op1, result, ov, s, z; - int temp; - - trace_input ("divh", OP_REG_REG, 0); - - /* Compute the result. */ - temp = EXTEND16 (State.regs[ OP[0] ]); - op0 = temp; - op1 = State.regs[OP[1]]; - - if (op0 == 0xffffffff && op1 == 0x80000000) - { - result = 0x80000000; - ov = 1; - } - else if (op0 != 0) - { - result = op1 / op0; - ov = 0; - } - else - { - result = 0x0; - ov = 1; - } - - /* Compute the condition codes. */ - z = (result == 0); - s = (result & 0x80000000); - - /* Store the result and condition codes. */ - State.regs[OP[1]] = result; - PSW &= ~(PSW_Z | PSW_S | PSW_OV); - PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0) - | (ov ? PSW_OV : 0)); - trace_output (OP_REG_REG); - - return 2; - } - /* cmp reg, reg */ int OP_1E0 () --- 771,776 ---- Index: sim/v850/simops.h =================================================================== RCS file: /cvs/src/src/sim/v850/simops.h,v retrieving revision 1.1 diff -c -3 -p -w -r1.1 simops.h *** sim/v850/simops.h 2 Dec 2001 19:27:29 -0000 1.1 --- sim/v850/simops.h 6 Apr 2003 08:46:41 -0000 *************** int OP_180 (void); *** 17,23 **** int OP_E0 (void); int OP_2E0 (void); int OP_6E0 (void); - int OP_40 (void); int OP_1E0 (void); int OP_260 (void); int OP_7E0 (void); --- 17,22 ---- Index: sim/v850/v850.igen =================================================================== RCS file: /cvs/src/src/sim/v850/v850.igen,v retrieving revision 1.5 diff -c -3 -p -w -r1.5 v850.igen *** sim/v850/v850.igen 19 Sep 2002 07:52:02 -0000 1.5 --- sim/v850/v850.igen 6 Apr 2003 08:46:41 -0000 *************** rrrrr,111111,RRRRR + wwwww,01011000000:X *** 332,338 **** rrrrr!0,000010,RRRRR!0:I:::divh "divh r, r" { ! COMPAT_1 (OP_40 ()); } rrrrr,111111,RRRRR + wwwww,01010000000:XI:::divh --- 332,379 ---- rrrrr!0,000010,RRRRR!0:I:::divh "divh r, r" { ! unsigned32 ov, s, z; ! signed long int op0, op1, result; ! ! trace_input ("divh", OP_REG_REG, 0); ! ! PC = cia; ! OP[0] = instruction_0 & 0x1f; ! OP[1] = (instruction_0 >> 11) & 0x1f; ! ! /* Compute the result. */ ! op0 = EXTEND16 (State.regs[OP[0]]); ! op1 = State.regs[OP[1]]; ! ! if (op0 == 0xffffffff && op1 == 0x80000000) ! { ! result = 0x80000000; ! ov = 1; ! } ! else if (op0 != 0) ! { ! result = op1 / op0; ! ov = 0; ! } ! else ! { ! result = 0x0; ! ov = 1; ! } ! ! /* Compute the condition codes. */ ! z = (result == 0); ! s = (result & 0x80000000); ! ! /* Store the result and condition codes. */ ! State.regs[OP[1]] = result; ! PSW &= ~(PSW_Z | PSW_S | PSW_OV); ! PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0) | (ov ? PSW_OV : 0)); ! ! trace_output (OP_REG_REG); ! ! PC += 2; ! nia = PC; } rrrrr,111111,RRRRR + wwwww,01010000000:XI:::divh