From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 31426 invoked by alias); 5 Sep 2003 15:59:51 -0000 Mailing-List: contact gdb-patches-help@sources.redhat.com; run by ezmlm Precedence: bulk List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sources.redhat.com Received: (qmail 31306 invoked from network); 5 Sep 2003 15:59:41 -0000 Received: from unknown (HELO mx1.redhat.com) (66.187.233.31) by sources.redhat.com with SMTP; 5 Sep 2003 15:59:41 -0000 Received: from int-mx1.corp.redhat.com (int-mx1.corp.redhat.com [172.16.52.254]) by mx1.redhat.com (8.11.6/8.11.6) with ESMTP id h85FxZl31174 for ; Fri, 5 Sep 2003 11:59:36 -0400 Received: from pobox.corp.redhat.com (pobox.corp.redhat.com [172.16.52.156]) by int-mx1.corp.redhat.com (8.11.6/8.11.6) with ESMTP id h85FxZs25101 for ; Fri, 5 Sep 2003 11:59:35 -0400 Received: from localhost.localdomain.redhat.com (vpn50-2.rdu.redhat.com [172.16.50.2]) by pobox.corp.redhat.com (8.12.8/8.12.8) with ESMTP id h85FxUA3032761; Fri, 5 Sep 2003 11:59:31 -0400 To: gdb-patches@sources.redhat.com Cc: nickc@redhat.com Subject: RFA: Add support for V850E1 instructions to V850 sim From: Nick Clifton Date: Fri, 05 Sep 2003 15:59:00 -0000 Message-ID: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii X-SW-Source: 2003-09/txt/msg00071.txt.bz2 Hi Guys, I would like permission to contribute the following patch which adds support for the V850E1 processor to the V850 simulator. The code was written by Andrew Cagney and myself a while ago and Mitsubishi have recently given us permission to contribute it. Cheers Nick sim/v850/ChangeLog 2003-09-05 Andrew Cagney Nick Clifton * interp.c (sim_open): Accept bfd_mach_v850e1. * v850-dc: Add entry for v850e1. * v850.igen: Add support for v850e1. Add code for DBTRAP and DBRET instructions. (dbtrap): Create a separate v850e1 specific instruction. Only generate a trap if the target is not the v850e1. Otherwise treat it as a special kind of branch. (break): Mark as v850/v850e specific. Index: sim/v850/interp.c =================================================================== RCS file: /cvs/src/src/sim/v850/interp.c,v retrieving revision 1.3 diff -c -3 -p -r1.3 interp.c *** sim/v850/interp.c 27 Feb 2003 23:26:34 -0000 1.3 --- sim/v850/interp.c 5 Sep 2003 15:56:24 -0000 *************** sim_open (kind, cb, abfd, argv) *** 277,282 **** --- 277,283 ---- { case bfd_mach_v850: case bfd_mach_v850e: + case bfd_mach_v850e1: STATE_CPU (sd, 0)->psw_mask = (PSW_NP | PSW_EP | PSW_ID | PSW_SAT | PSW_CY | PSW_OV | PSW_S | PSW_Z); break; Index: sim/v850/v850-dc =================================================================== RCS file: /cvs/src/src/sim/v850/v850-dc,v retrieving revision 1.2 diff -c -3 -p -r1.2 v850-dc *** sim/v850/v850-dc 19 Sep 2002 07:52:02 -0000 1.2 --- sim/v850/v850-dc 5 Sep 2003 15:56:24 -0000 *************** *** 11,16 **** --- 11,17 ---- switch,combine : 4 : 0 : : : : 1 : V,VII : switch,combine : 4 : 0 : : : : 1 : V,XIII : v850e + switch,combine : 4 : 0 : : : : 1 : V,XIII : v850e1 # for opcode 63, 127, 1087 et.al. Index: sim/v850/v850.igen =================================================================== RCS file: /cvs/src/src/sim/v850/v850.igen,v retrieving revision 1.6 diff -c -3 -p -r1.6 v850.igen *** sim/v850/v850.igen 6 Apr 2003 08:51:04 -0000 1.6 --- sim/v850/v850.igen 5 Sep 2003 15:56:24 -0000 *************** *** 12,17 **** --- 12,19 ---- :option:::multi-sim:true :model:::v850e:v850e: + :option:::multi-sim:true + :model:::v850e1:v850e1: // Cache macros *************** ddddd,1011,ddd,cccc:III:::Bcond *** 156,161 **** --- 158,164 ---- // BSH rrrrr,11111100000 + wwwww,01101000010:XII:::bsh *v850e + *v850e1 "bsh r, r" { unsigned32 value; *************** rrrrr,11111100000 + wwwww,01101000010:XI *** 178,183 **** --- 181,187 ---- // BSW rrrrr,11111100000 + wwwww,01101000000:XII:::bsw *v850e + *v850e1 "bsw r, r" { #define WORDHASNULLBYTE(x) (((x) - 0x01010101) & ~(x)&0x80808080) *************** rrrrr,11111100000 + wwwww,01101000000:XI *** 203,208 **** --- 207,213 ---- // CALLT 0000001000,iiiiii:II:::callt *v850e + *v850e1 "callt " { unsigned32 adr; *************** rrrrr,11111100000 + wwwww,01101000000:XI *** 225,230 **** --- 230,236 ---- rrrrr,111111,RRRRR + 0000000011100100:IX:::clr1 *v850e + *v850e1 "clr1 r, [r]" { COMPAT_2 (OP_E407E0 ()); *************** rrrrr,111111,RRRRR + 0000000011100100:IX *** 234,239 **** --- 240,246 ---- // CTRET 0000011111100000 + 0000000101000100:X:::ctret *v850e + *v850e1 "ctret" { nia = (CTPC & ~1); *************** rrrrr,111111,RRRRR + 0000000011100100:IX *** 244,249 **** --- 251,257 ---- // CMOV rrrrr,111111,RRRRR + wwwww,011001,cccc,0:XI:::cmov *v850e + *v850e1 "cmov %s, r, r, r" { int cond = condition_met (cccc); *************** rrrrr,111111,RRRRR + wwwww,011001,cccc,0 *** 254,259 **** --- 262,268 ---- rrrrr,111111,iiiii + wwwww,011000,cccc,0:XII:::cmov *v850e + *v850e1 "cmov %s, , r, r" { int cond = condition_met (cccc); *************** rrrrr,010011,iiiii:II:::cmp *** 291,296 **** --- 300,306 ---- // "dispose , " 0000011001,iiiii,L + LLLLLLLLLLL,RRRRR:XIII:::dispose *v850e + *v850e1 "dispose , ":RRRRR == 0 "dispose , , [reg1]" { *************** rrrrr,010011,iiiii:II:::cmp *** 322,327 **** --- 332,338 ---- // DIV rrrrr,111111,RRRRR + wwwww,01011000000:XI:::div *v850e + *v850e1 "div r, r, r" { COMPAT_2 (OP_2C007E0 ()); *************** rrrrr!0,000010,RRRRR!0:I:::divh *** 378,383 **** --- 389,395 ---- rrrrr,111111,RRRRR + wwwww,01010000000:XI:::divh *v850e + *v850e1 "divh r, r, r" { COMPAT_2 (OP_28007E0 ()); *************** rrrrr,111111,RRRRR + wwwww,01010000000:X *** 387,392 **** --- 399,405 ---- // DIVHU rrrrr,111111,RRRRR + wwwww,01010000010:XI:::divhu *v850e + *v850e1 "divhu r, r, r" { COMPAT_2 (OP_28207E0 ()); *************** rrrrr,111111,RRRRR + wwwww,01010000010:X *** 396,401 **** --- 409,415 ---- // DIVU rrrrr,111111,RRRRR + wwwww,01011000010:XI:::divu *v850e + *v850e1 "divu r, r, r" { COMPAT_2 (OP_2C207E0 ()); *************** rrrrr,111111,RRRRR + wwwww,01011000010:X *** 423,428 **** --- 437,443 ---- // HSW rrrrr,11111100000 + wwwww,01101000100:XII:::hsw *v850e + *v850e1 "hsw r, r" { unsigned32 value; *************** rrrrr,111001,RRRRR + ddddddddddddddd,1:V *** 497,502 **** --- 512,518 ---- rrrrr!0,11110,b,RRRRR + ddddddddddddddd,1:VII:::ld.bu *v850e + *v850e1 "ld.bu [r], r" { COMPAT_2 (OP_10780 ()); *************** rrrrr!0,11110,b,RRRRR + ddddddddddddddd, *** 504,509 **** --- 520,526 ---- rrrrr!0,111111,RRRRR + ddddddddddddddd,1:VII:::ld.hu *v850e + *v850e1 "ld.hu [r], r" { COMPAT_2 (OP_107E0 ()); *************** rrrrr!0,010000,iiiii:II:::mov *** 544,549 **** --- 561,567 ---- 00000110001,RRRRR + iiiiiiiiiiiiiiii + IIIIIIIIIIIIIIII:VI:::mov *v850e + *v850e1 "mov , r" { SAVE_2; *************** rrrrr!0,110010,RRRRR + iiiiiiiiiiiiiiii: *** 577,582 **** --- 595,601 ---- // MUL rrrrr,111111,RRRRR + wwwww,01000100000:XI:::mul *v850e + *v850e1 "mul r, r, r" { COMPAT_2 (OP_22007E0 ()); *************** rrrrr,111111,RRRRR + wwwww,01000100000:X *** 584,589 **** --- 603,609 ---- rrrrr,111111,iiiii + wwwww,01001,IIII,00:XII:::mul *v850e + *v850e1 "mul , r, r" { COMPAT_2 (OP_24007E0 ()); *************** rrrrr!0,110111,RRRRR + iiiiiiiiiiiiiiii: *** 617,622 **** --- 637,643 ---- // MULU rrrrr,111111,RRRRR + wwwww,01000100010:XI:::mulu *v850e + *v850e1 "mulu r, r, r" { COMPAT_2 (OP_22207E0 ()); *************** rrrrr,111111,RRRRR + wwwww,01000100010:X *** 624,629 **** --- 645,651 ---- rrrrr,111111,iiiii + wwwww,01001,IIII,10:XII:::mulu *v850e + *v850e1 "mulu , r, r" { COMPAT_2 (OP_24207E0 ()); *************** rrrrr,000001,RRRRR:I:::not *** 658,663 **** --- 680,686 ---- rrrrr,111111,RRRRR + 0000000011100010:IX:::not1 *v850e + *v850e1 "not1 r, r" { COMPAT_2 (OP_E207E0 ()); *************** rrrrr,110100,RRRRR + iiiiiiiiiiiiiiii:VI *** 686,691 **** --- 709,715 ---- // PREPARE 0000011110,iiiii,L + LLLLLLLLLLL,00001:XIII:::prepare *v850e + *v850e1 "prepare , " { int i; *************** rrrrr,110100,RRRRR + iiiiiiiiiiiiiiii:VI *** 710,715 **** --- 734,740 ---- 0000011110,iiiii,L + LLLLLLLLLLL,00011:XIII:::prepare00 *v850e + *v850e1 "prepare , , sp" { COMPAT_2 (OP_30780 ()); *************** rrrrr,110100,RRRRR + iiiiiiiiiiiiiiii:VI *** 717,722 **** --- 742,748 ---- 0000011110,iiiii,L + LLLLLLLLLLL,01011 + iiiiiiiiiiiiiiii:XIII:::prepare01 *v850e + *v850e1 "prepare , , " { COMPAT_2 (OP_B0780 ()); *************** rrrrr,110100,RRRRR + iiiiiiiiiiiiiiii:VI *** 724,729 **** --- 750,756 ---- 0000011110,iiiii,L + LLLLLLLLLLL,10011 + iiiiiiiiiiiiiiii:XIII:::prepare10 *v850e + *v850e1 "prepare , , " { COMPAT_2 (OP_130780 ()); *************** rrrrr,110100,RRRRR + iiiiiiiiiiiiiiii:VI *** 731,736 **** --- 758,764 ---- 0000011110,iiiii,L + LLLLLLLLLLL,11011 + iiiiiiiiiiiiiiii + dddddddddddddddd:XIII:::prepare11 *v850e + *v850e1 "prepare , , " { COMPAT_2 (OP_1B0780 ()); *************** rrrrr,010101,iiiii:II:::sar *** 780,785 **** --- 808,814 ---- // SASF rrrrr,1111110,cccc + 0000001000000000:IX:::sasf *v850e + *v850e1 "sasf %s, r" { COMPAT_2 (OP_20007E0 ()); *************** rrrrr,1111110,cccc + 0000000000000000:IX *** 848,853 **** --- 877,883 ---- rrrrr,111111,RRRRR + 0000000011100000:IX:::set1 *v850e + *v850e1 "set1 r, [r]" { COMPAT_2 (OP_E007E0 ()); *************** rrrrr,1010,dddddd,0:IV:::sld.w *** 935,940 **** --- 965,971 ---- rrrrr!0,0000110,dddd:IV:::sld.bu *v850e + *v850e1 "sld.b [ep], r":(PSW & PSW_US) "sld.bu [ep], r" { *************** rrrrr!0,0000110,dddd:IV:::sld.bu *** 955,960 **** --- 986,992 ---- rrrrr!0,0000111,dddd:IV:::sld.hu *v850e + *v850e1 "sld.h [ep], r":(PSW & PSW_US) "sld.hu [ep], r" { *************** rrrrr,001100,RRRRR:I:::subr *** 1037,1042 **** --- 1069,1075 ---- // SWITCH 00000000010,RRRRR:I:::switch *v850e + *v850e1 "switch r" { unsigned long adr; *************** rrrrr,001100,RRRRR:I:::subr *** 1050,1055 **** --- 1083,1089 ---- // SXB 00000000101,RRRRR:I:::sxb *v850e + *v850e1 "sxb r" { TRACE_ALU_INPUT1 (GR[reg1]); *************** rrrrr,001100,RRRRR:I:::subr *** 1060,1065 **** --- 1094,1100 ---- // SXH 00000000111,RRRRR:I:::sxh *v850e + *v850e1 "sxh r" { TRACE_ALU_INPUT1 (GR[reg1]); *************** rrrrr,001011,RRRRR:I:::tst *** 1090,1095 **** --- 1125,1131 ---- rrrrr,111111,RRRRR + 0000000011100110:IX:::tst1 *v850e + *v850e1 "tst1 r, [r]" { COMPAT_2 (OP_E607E0 ()); *************** rrrrr,110101,RRRRR + iiiiiiiiiiiiiiii:VI *** 1112,1117 **** --- 1148,1154 ---- // ZXB 00000000100,RRRRR:I:::zxb *v850e + *v850e1 "zxb r" { TRACE_ALU_INPUT1 (GR[reg1]); *************** rrrrr,110101,RRRRR + iiiiiiiiiiiiiiii:VI *** 1122,1127 **** --- 1159,1165 ---- // ZXH 00000000110,RRRRR:I:::zxh *v850e + *v850e1 "zxh r" { TRACE_ALU_INPUT1 (GR[reg1]); *************** rrrrr,110101,RRRRR + iiiiiiiiiiiiiiii:VI *** 1132,1143 **** --- 1170,1205 ---- // Right field must be zero so that it doesn't clash with DIVH // Left field must be non-zero so that it doesn't clash with SWITCH 11111,000010,00000:I:::break + *v850 + *v850e { sim_engine_halt (SD, CPU, NULL, cia, sim_stopped, SIM_SIGTRAP); } + 11111,000010,00000:I:::dbtrap + *v850e1 + "dbtrap" + { + DBPC = cia + 2; + DBPSW = PSW; + PSW = PSW | (PSW_NP | PSW_EP | PSW_ID); + PC = 0x00000060; + nia = 0x00000060; + TRACE_BRANCH0 (); + } + // New breakpoint: 0x7E0 0x7E0 00000,111111,00000 + 00000,11111,100000:X:::ilgop { sim_engine_halt (SD, CPU, NULL, cia, sim_stopped, SIM_SIGTRAP); + } + + // Return from debug trap: 0x146007e0 + 0000011111100000 + 0000000101000110:X:::dbret + *v850e1 + "dbret" + { + nia = DBPC; + PSW = DBPSW; + TRACE_BRANCH1 (PSW); }