From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 18732 invoked by alias); 5 Feb 2002 10:55:27 -0000 Mailing-List: contact gdb-patches-help@sources.redhat.com; run by ezmlm Precedence: bulk List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sources.redhat.com Received: (qmail 18277 invoked from network); 5 Feb 2002 10:55:19 -0000 Received: from unknown (HELO dell-pe2450-3.cambridge.redhat.com) (195.224.55.225) by sources.redhat.com with SMTP; 5 Feb 2002 10:55:19 -0000 Received: from north-pole.nickc.cambridge.redhat.com (host217-35-28-24.in-addr.btopenworld.com [217.35.28.24]) by dell-pe2450-3.cambridge.redhat.com (Postfix) with ESMTP id 1927A849D4 for ; Tue, 5 Feb 2002 10:55:19 +0000 (GMT) Received: from north-pole.nickc.cambridge.redhat.com.nickc.cambridge.redhat.com (localhost [127.0.0.1]) by north-pole.nickc.cambridge.redhat.com (Postfix) with ESMTP id 0AEF4111C25 for ; Tue, 5 Feb 2002 10:55:57 +0000 (GMT) To: gdb-patches@sources.redhat.com Subject: SIM: Handle XScale COFF binaries From: Nick Clifton Date: Tue, 05 Feb 2002 02:55:00 -0000 Message-ID: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii X-SW-Source: 2002-02/txt/msg00109.txt.bz2 Hi Guys, I have checked in the following patch. It fixes the ARM simulator so that COFF based XScale binaries will be correctly simulated. The problem was that the COFF header did not have enough bits to distinguish between the v5, v5T, v5TE and XScale architectures, and so it was defaulting to v5, disabling the simulation of the XScale instructions. Cheers Nick 2002-02-04 Nick Clifton * wrapper.c: If a v5 architecture is detected, assume it might be an XScale binary, since there is no way to distinguish between the two in the COFF file format. Index: sim/arm/wrapper.c =================================================================== RCS file: /cvs/src/src/sim/arm/wrapper.c,v retrieving revision 1.15 retrieving revision 1.16 diff -c -3 -p -w -r1.15 -r1.16 *** wrapper.c 2002/01/09 15:08:21 1.15 --- wrapper.c 2002/02/04 16:27:22 1.16 *************** sim_create_inferior (sd, abfd, argv, env *** 234,239 **** --- 234,248 ---- break; case bfd_mach_arm_5: + /* This is a special case in order to support COFF based ARM toolchains. + The COFF header does not have enough room to store all the different + kinds of ARM cpu, so the XScale, v5T and v5TE architectures all default + to v5. (See coff_set_flags() in bdf/coffcode.h). So if we see a v5 + machine type here, we assume it could be any of the above architectures + and so select the most feature-full. */ + ARMul_SelectProcessor (state, ARM_v5_Prop | ARM_v5e_Prop | ARM_XScale_Prop); + break; + case bfd_mach_arm_5T: ARMul_SelectProcessor (state, ARM_v5_Prop); break;