From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 8376 invoked by alias); 19 Sep 2002 07:50:08 -0000 Mailing-List: contact gdb-patches-help@sources.redhat.com; run by ezmlm Precedence: bulk List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sources.redhat.com Received: (qmail 8369 invoked from network); 19 Sep 2002 07:50:05 -0000 Received: from unknown (HELO mx1.redhat.com) (66.187.233.31) by sources.redhat.com with SMTP; 19 Sep 2002 07:50:05 -0000 Received: from int-mx1.corp.redhat.com (int-mx1.corp.redhat.com [172.16.52.254]) by mx1.redhat.com (8.11.6/8.11.6) with ESMTP id g8J7Woi17381 for ; Thu, 19 Sep 2002 03:32:50 -0400 Received: from pobox.corp.redhat.com (pobox.corp.redhat.com [172.16.52.156]) by int-mx1.corp.redhat.com (8.11.6/8.11.6) with ESMTP id g8J7o4h14022; Thu, 19 Sep 2002 03:50:04 -0400 Received: from north-pole.nickc.cambridge.redhat.com.redhat.com (vpnuser1.stuttgart.redhat.com [172.16.4.1]) by pobox.corp.redhat.com (8.11.6/8.11.6) with ESMTP id g8J7o0f14617; Thu, 19 Sep 2002 03:50:02 -0400 To: Hans-Peter Nilsson Cc: gdb-patches@sources.redhat.com Subject: Re: v850 sim noncompile (was: Re: Add v850 linker relaxation) References: From: Nick Clifton Date: Thu, 19 Sep 2002 00:50:00 -0000 In-Reply-To: Message-ID: User-Agent: Gnus/5.0808 (Gnus v5.8.8) Emacs/21.1 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii X-SW-Source: 2002-09/txt/msg00457.txt.bz2 Hi Hans-Peter, > I just noticed this error when doing a "full build" as per > yaddayaddayadda: > .../sim/v850/interp.c: In function `sim_open': > .../sim/v850/interp.c:283: `bfd_mach_v850ea' undeclared (first use in this function) Oopsie, fixed by applying the attached patch. Cheers Nick 2002-09-19 Nick Clifton * interp.c (sim_open): Remove reference to v850ea. (sim_create_inferior): Likewise. * v850-dc: Likewise. * v850.igen: Remove all references to v850ea, including v850ea specific instructions. Index: sim/v850/interp.c =================================================================== RCS file: /cvs/src/src/sim/v850/interp.c,v retrieving revision 1.1.1.1 diff -c -3 -p -w -r1.1.1.1 interp.c *** sim/v850/interp.c 16 Apr 1999 01:35:12 -0000 1.1.1.1 --- sim/v850/interp.c 19 Sep 2002 07:46:52 -0000 *************** sim_open (kind, cb, abfd, argv) *** 280,291 **** STATE_CPU (sd, 0)->psw_mask = (PSW_NP | PSW_EP | PSW_ID | PSW_SAT | PSW_CY | PSW_OV | PSW_S | PSW_Z); break; - case bfd_mach_v850ea: - PSW |= PSW_US; - STATE_CPU (sd, 0)->psw_mask = (PSW_US - | PSW_NP | PSW_EP | PSW_ID | PSW_SAT - | PSW_CY | PSW_OV | PSW_S | PSW_Z); - break; } return sd; --- 280,285 ---- *************** sim_create_inferior (sd, prog_bfd, argv, *** 310,320 **** memset (&State, 0, sizeof (State)); if (prog_bfd != NULL) PC = bfd_get_start_address (prog_bfd); - /* For v850ea, set PSW[US] by default */ - if (STATE_ARCHITECTURE (sd) != NULL - && STATE_ARCHITECTURE (sd)->arch == bfd_arch_v850 - && STATE_ARCHITECTURE (sd)->mach == bfd_mach_v850ea) - PSW |= PSW_US; return SIM_RC_OK; } --- 304,309 ---- Index: sim/v850/v850-dc =================================================================== RCS file: /cvs/src/src/sim/v850/v850-dc,v retrieving revision 1.1.1.1 diff -c -3 -p -w -r1.1.1.1 v850-dc *** sim/v850/v850-dc 16 Apr 1999 01:35:12 -0000 1.1.1.1 --- sim/v850/v850-dc 19 Sep 2002 07:46:52 -0000 *************** *** 11,17 **** switch,combine : 4 : 0 : : : : 1 : V,VII : switch,combine : 4 : 0 : : : : 1 : V,XIII : v850e - switch,combine : 4 : 0 : : : : 1 : V,XIII : v850ea # for opcode 63, 127, 1087 et.al. --- 11,16 ---- *************** *** 23,29 **** # for opcode 40 et.al. switch,combine : 4 : 0 : : : : 0 : III,IV : - switch,combine : 4 : 0 : : : : 0 : III,IV,XIV : v850ea # for opcode 66 - divh/break --- 22,27 ---- Index: sim/v850/v850.igen =================================================================== RCS file: /cvs/src/src/sim/v850/v850.igen,v retrieving revision 1.4 diff -c -3 -p -w -r1.4 v850.igen *** sim/v850/v850.igen 30 May 2000 18:36:57 -0000 1.4 --- sim/v850/v850.igen 19 Sep 2002 07:46:52 -0000 *************** *** 13,23 **** :option:::multi-sim:true :model:::v850e:v850e: - :option:::multi-sim:true - :model:::v850ea:v850ea: - - - // Cache macros :cache:::unsigned:reg1:RRRRR:(RRRRR) --- 13,18 ---- *************** ddddd,1011,ddd,cccc:III:::Bcond *** 161,167 **** // BSH rrrrr,11111100000 + wwwww,01101000010:XII:::bsh *v850e - *v850ea "bsh r, r" { unsigned32 value; --- 156,161 ---- *************** rrrrr,11111100000 + wwwww,01101000010:XI *** 184,190 **** // BSW rrrrr,11111100000 + wwwww,01101000000:XII:::bsw *v850e - *v850ea "bsw r, r" { #define WORDHASNULLBYTE(x) (((x) - 0x01010101) & ~(x)&0x80808080) --- 178,183 ---- *************** rrrrr,11111100000 + wwwww,01101000000:XI *** 210,216 **** // CALLT 0000001000,iiiiii:II:::callt *v850e - *v850ea "callt " { unsigned32 adr; --- 203,208 ---- *************** rrrrr,11111100000 + wwwww,01101000000:XI *** 233,239 **** rrrrr,111111,RRRRR + 0000000011100100:IX:::clr1 *v850e - *v850ea "clr1 r, [r]" { COMPAT_2 (OP_E407E0 ()); --- 225,230 ---- *************** rrrrr,111111,RRRRR + 0000000011100100:IX *** 243,249 **** // CTRET 0000011111100000 + 0000000101000100:X:::ctret *v850e - *v850ea "ctret" { nia = (CTPC & ~1); --- 234,239 ---- *************** rrrrr,111111,RRRRR + 0000000011100100:IX *** 254,260 **** // CMOV rrrrr,111111,RRRRR + wwwww,011001,cccc,0:XI:::cmov *v850e - *v850ea "cmov %s, r, r, r" { int cond = condition_met (cccc); --- 244,249 ---- *************** rrrrr,111111,RRRRR + wwwww,011001,cccc,0 *** 265,271 **** rrrrr,111111,iiiii + wwwww,011000,cccc,0:XII:::cmov *v850e - *v850ea "cmov %s, , r, r" { int cond = condition_met (cccc); --- 254,259 ---- *************** rrrrr,010011,iiiii:II:::cmp *** 303,309 **** // "dispose , " 0000011001,iiiii,L + LLLLLLLLLLL,RRRRR:XIII:::dispose *v850e - *v850ea "dispose , ":RRRRR == 0 "dispose , , [reg1]" { --- 291,296 ---- *************** rrrrr,111111,RRRRR + wwwww,01011000010:X *** 395,401 **** // HSW rrrrr,11111100000 + wwwww,01101000100:XII:::hsw *v850e - *v850ea "hsw r, r" { unsigned32 value; --- 382,387 ---- *************** rrrrr,111001,RRRRR + ddddddddddddddd,1:V *** 470,476 **** rrrrr!0,11110,b,RRRRR + ddddddddddddddd,1:VII:::ld.bu *v850e - *v850ea "ld.bu [r], r" { COMPAT_2 (OP_10780 ()); --- 456,461 ---- *************** rrrrr!0,11110,b,RRRRR + ddddddddddddddd, *** 478,484 **** rrrrr!0,111111,RRRRR + ddddddddddddddd,1:VII:::ld.hu *v850e - *v850ea "ld.hu [r], r" { COMPAT_2 (OP_107E0 ()); --- 463,468 ---- *************** rrrrr!0,010000,iiiii:II:::mov *** 519,525 **** 00000110001,RRRRR + iiiiiiiiiiiiiiii + IIIIIIIIIIIIIIII:VI:::mov *v850e - *v850ea "mov , r" { SAVE_2; --- 503,508 ---- *************** rrrrr!0,110010,RRRRR + iiiiiiiiiiiiiiii: *** 553,559 **** // MUL rrrrr,111111,RRRRR + wwwww,01000100000:XI:::mul *v850e - *v850ea "mul r, r, r" { COMPAT_2 (OP_22007E0 ()); --- 536,541 ---- *************** rrrrr,111111,RRRRR + wwwww,01000100000:X *** 561,567 **** rrrrr,111111,iiiii + wwwww,01001,IIII,00:XII:::mul *v850e - *v850ea "mul , r, r" { COMPAT_2 (OP_24007E0 ()); --- 543,548 ---- *************** rrrrr!0,110111,RRRRR + iiiiiiiiiiiiiiii: *** 595,601 **** // MULU rrrrr,111111,RRRRR + wwwww,01000100010:XI:::mulu *v850e - *v850ea "mulu r, r, r" { COMPAT_2 (OP_22207E0 ()); --- 576,581 ---- *************** rrrrr,111111,RRRRR + wwwww,01000100010:X *** 603,609 **** rrrrr,111111,iiiii + wwwww,01001,IIII,10:XII:::mulu *v850e - *v850ea "mulu , r, r" { COMPAT_2 (OP_24207E0 ()); --- 583,588 ---- *************** rrrrr,000001,RRRRR:I:::not *** 638,644 **** rrrrr,111111,RRRRR + 0000000011100010:IX:::not1 *v850e - *v850ea "not1 r, r" { COMPAT_2 (OP_E207E0 ()); --- 617,622 ---- *************** rrrrr,110100,RRRRR + iiiiiiiiiiiiiiii:VI *** 667,673 **** // PREPARE 0000011110,iiiii,L + LLLLLLLLLLL,00001:XIII:::prepare *v850e - *v850ea "prepare , " { int i; --- 645,650 ---- *************** rrrrr,110100,RRRRR + iiiiiiiiiiiiiiii:VI *** 692,698 **** 0000011110,iiiii,L + LLLLLLLLLLL,00011:XIII:::prepare00 *v850e - *v850ea "prepare , , sp" { COMPAT_2 (OP_30780 ()); --- 669,674 ---- *************** rrrrr,110100,RRRRR + iiiiiiiiiiiiiiii:VI *** 700,706 **** 0000011110,iiiii,L + LLLLLLLLLLL,01011 + iiiiiiiiiiiiiiii:XIII:::prepare01 *v850e - *v850ea "prepare , , " { COMPAT_2 (OP_B0780 ()); --- 676,681 ---- *************** rrrrr,110100,RRRRR + iiiiiiiiiiiiiiii:VI *** 708,714 **** 0000011110,iiiii,L + LLLLLLLLLLL,10011 + iiiiiiiiiiiiiiii:XIII:::prepare10 *v850e - *v850ea "prepare , , " { COMPAT_2 (OP_130780 ()); --- 683,688 ---- *************** rrrrr,110100,RRRRR + iiiiiiiiiiiiiiii:VI *** 716,722 **** 0000011110,iiiii,L + LLLLLLLLLLL,11011 + iiiiiiiiiiiiiiii + dddddddddddddddd:XIII:::prepare11 *v850e - *v850ea "prepare , , " { COMPAT_2 (OP_1B0780 ()); --- 690,695 ---- *************** rrrrr,010101,iiiii:II:::sar *** 766,772 **** // SASF rrrrr,1111110,cccc + 0000001000000000:IX:::sasf *v850e - *v850ea "sasf %s, r" { COMPAT_2 (OP_20007E0 ()); --- 739,744 ---- *************** rrrrr,1111110,cccc + 0000000000000000:IX *** 835,841 **** rrrrr,111111,RRRRR + 0000000011100000:IX:::set1 *v850e - *v850ea "set1 r, [r]" { COMPAT_2 (OP_E007E0 ()); --- 807,812 ---- *************** rrrrr,1010,dddddd,0:IV:::sld.w *** 923,929 **** rrrrr!0,0000110,dddd:IV:::sld.bu *v850e - *v850ea "sld.b [ep], r":(PSW & PSW_US) "sld.bu [ep], r" { --- 894,899 ---- *************** rrrrr!0,0000110,dddd:IV:::sld.bu *** 944,950 **** rrrrr!0,0000111,dddd:IV:::sld.hu *v850e - *v850ea "sld.h [ep], r":(PSW & PSW_US) "sld.hu [ep], r" { --- 914,919 ---- *************** rrrrr!0,0000111,dddd:IV:::sld.hu *** 963,969 **** } } - // SST rrrrr,0111,ddddddd:IV:::sst.b "sst.b r, [ep]" --- 932,937 ---- *************** rrrrr,1010,dddddd,1:IV:::sst.w *** 983,990 **** COMPAT_1 (OP_501 ()); } - - // ST rrrrr,111010,RRRRR + dddddddddddddddd:VII:::st.b "st.b r, [r]" --- 951,956 ---- *************** rrrrr,111011,RRRRR + ddddddddddddddd,1:V *** 1004,1011 **** COMPAT_2 (OP_10760 ()); } - - // STSR rrrrr,111111,regID + 0000000001000000:IX:::stsr "stsr s, r" --- 970,975 ---- *************** rrrrr,111111,regID + 0000000001000000:IX *** 1015,1022 **** TRACE_ALU_RESULT (GR[reg2]); } - - // SUB rrrrr,001101,RRRRR:I:::sub "sub r, r" --- 979,984 ---- *************** rrrrr,001101,RRRRR:I:::sub *** 1024,1031 **** COMPAT_1 (OP_1A0 ()); } - - // SUBR rrrrr,001100,RRRRR:I:::subr "subr r, r" --- 986,991 ---- *************** rrrrr,001100,RRRRR:I:::subr *** 1033,1044 **** COMPAT_1 (OP_180 ()); } - - // SWITCH 00000000010,RRRRR:I:::switch *v850e - *v850ea "switch r" { unsigned long adr; --- 993,1001 ---- *************** rrrrr,001100,RRRRR:I:::subr *** 1049,1059 **** trace_output (OP_REG); } - // SXB 00000000101,RRRRR:I:::sxb *v850e - *v850ea "sxb r" { TRACE_ALU_INPUT1 (GR[reg1]); --- 1006,1014 ---- *************** rrrrr,001100,RRRRR:I:::subr *** 1064,1070 **** // SXH 00000000111,RRRRR:I:::sxh *v850e - *v850ea "sxh r" { TRACE_ALU_INPUT1 (GR[reg1]); --- 1019,1024 ---- *************** rrrrr,001100,RRRRR:I:::subr *** 1072,1079 **** TRACE_ALU_RESULT (GR[reg1]); } - - // TRAP 00000111111,iiiii + 0000000100000000:X:::trap "trap " --- 1026,1031 ---- *************** rrrrr,001100,RRRRR:I:::subr *** 1081,1088 **** COMPAT_2 (OP_10007E0 ()); } - - // TST rrrrr,001011,RRRRR:I:::tst "tst r, r" --- 1033,1038 ---- *************** rrrrr,001011,RRRRR:I:::tst *** 1090,1097 **** COMPAT_1 (OP_160 ()); } - - // TST1 11,bbb,111110,RRRRR + dddddddddddddddd:VIII:::tst1 "tst1 , [r]" --- 1040,1045 ---- *************** rrrrr,001011,RRRRR:I:::tst *** 1101,1114 **** rrrrr,111111,RRRRR + 0000000011100110:IX:::tst1 *v850e - *v850ea "tst1 r, [r]" { COMPAT_2 (OP_E607E0 ()); } - - // XOR rrrrr,001001,RRRRR:I:::xor "xor r, r" --- 1049,1059 ---- *************** rrrrr,001001,RRRRR:I:::xor *** 1116,1123 **** COMPAT_1 (OP_120 ()); } - - // XORI rrrrr,110101,RRRRR + iiiiiiiiiiiiiiii:VI:::xori "xori , r, r" --- 1061,1066 ---- *************** rrrrr,110101,RRRRR + iiiiiiiiiiiiiiii:VI *** 1125,1136 **** COMPAT_2 (OP_6A0 ()); } - - // ZXB 00000000100,RRRRR:I:::zxb *v850e - *v850ea "zxb r" { TRACE_ALU_INPUT1 (GR[reg1]); --- 1068,1076 ---- *************** rrrrr,110101,RRRRR + iiiiiiiiiiiiiiii:VI *** 1141,1147 **** // ZXH 00000000110,RRRRR:I:::zxh *v850e - *v850ea "zxh r" { TRACE_ALU_INPUT1 (GR[reg1]); --- 1081,1086 ---- *************** rrrrr,110101,RRRRR + iiiiiiiiiiiiiiii:VI *** 1149,1155 **** TRACE_ALU_RESULT (GR[reg1]); } - // Right field must be zero so that it doesn't clash with DIVH // Left field must be non-zero so that it doesn't clash with SWITCH 11111,000010,00000:I:::break --- 1088,1093 ---- *************** rrrrr,110101,RRRRR + iiiiiiiiiiiiiiii:VI *** 1157,1418 **** sim_engine_halt (SD, CPU, NULL, cia, sim_stopped, SIM_SIGTRAP); } - // New breakpoint: 0x7E0 0x7E0 00000,111111,00000 + 00000,11111,100000:X:::ilgop { sim_engine_halt (SD, CPU, NULL, cia, sim_stopped, SIM_SIGTRAP); } - - // DIVHN - rrrrr,111111,RRRRR + wwwww,01010,iiii,00:XI:::divhn - *v850ea - "divhn , r, r, r" - { - signed32 quotient; - signed32 remainder; - signed32 divide_by; - signed32 divide_this; - boolean overflow = false; - SAVE_2; - - trace_input ("divhn", OP_IMM_REG_REG_REG, 0); - - divide_by = EXTEND16 (State.regs[ reg1 ]); - divide_this = State.regs[ reg2 ]; - - divn (imm5, divide_by, divide_this, & quotient, & remainder, & overflow); - - State.regs[ reg2 ] = quotient; - State.regs[ reg3 ] = remainder; - - /* Set condition codes. */ - PSW &= ~(PSW_Z | PSW_S | PSW_OV); - - if (overflow) PSW |= PSW_OV; - if (quotient == 0) PSW |= PSW_Z; - if (quotient < 0) PSW |= PSW_S; - - trace_output (OP_IMM_REG_REG_REG); - } - - - - // DIVHUN - rrrrr,111111,RRRRR + wwwww,01010,iiii,10:XI:::divhun - *v850ea - "divhun , r, r, r" - { - signed32 quotient; - signed32 remainder; - signed32 divide_by; - signed32 divide_this; - boolean overflow = false; - SAVE_2; - - trace_input ("divhun", OP_IMM_REG_REG_REG, 0); - - divide_by = State.regs[ reg1 ] & 0xffff; - divide_this = State.regs[ reg2 ]; - - divun (imm5, divide_by, divide_this, & quotient, & remainder, & overflow); - - State.regs[ reg2 ] = quotient; - State.regs[ reg3 ] = remainder; - - /* Set condition codes. */ - PSW &= ~(PSW_Z | PSW_S | PSW_OV); - - if (overflow) PSW |= PSW_OV; - if (quotient == 0) PSW |= PSW_Z; - if (quotient & 0x80000000) PSW |= PSW_S; - - trace_output (OP_IMM_REG_REG_REG); - } - - - - // DIVN - rrrrr,111111,RRRRR + wwwww,01011,iiii,00:XI:::divn - *v850ea - "divn , r, r, r" - { - signed32 quotient; - signed32 remainder; - signed32 divide_by; - signed32 divide_this; - boolean overflow = false; - SAVE_2; - - trace_input ("divn", OP_IMM_REG_REG_REG, 0); - - divide_by = State.regs[ reg1 ]; - divide_this = State.regs[ reg2 ]; - - divn (imm5, divide_by, divide_this, & quotient, & remainder, & overflow); - - State.regs[ reg2 ] = quotient; - State.regs[ reg3 ] = remainder; - - /* Set condition codes. */ - PSW &= ~(PSW_Z | PSW_S | PSW_OV); - - if (overflow) PSW |= PSW_OV; - if (quotient == 0) PSW |= PSW_Z; - if (quotient < 0) PSW |= PSW_S; - - trace_output (OP_IMM_REG_REG_REG); - } - - - - // DIVUN - rrrrr,111111,RRRRR + wwwww,01011,iiii,10:XI:::divun - *v850ea - "divun , r, r, r" - { - signed32 quotient; - signed32 remainder; - signed32 divide_by; - signed32 divide_this; - boolean overflow = false; - SAVE_2; - - trace_input ("divun", OP_IMM_REG_REG_REG, 0); - - divide_by = State.regs[ reg1 ]; - divide_this = State.regs[ reg2 ]; - - divun (imm5, divide_by, divide_this, & quotient, & remainder, & overflow); - - State.regs[ reg2 ] = quotient; - State.regs[ reg3 ] = remainder; - - /* Set condition codes. */ - PSW &= ~(PSW_Z | PSW_S | PSW_OV); - - if (overflow) PSW |= PSW_OV; - if (quotient == 0) PSW |= PSW_Z; - if (quotient & 0x80000000) PSW |= PSW_S; - - trace_output (OP_IMM_REG_REG_REG); - } - - - - // SDIVHN - rrrrr,111111,RRRRR + wwwww,00110,iiii,00:XI:::sdivhn - *v850ea - "sdivhn , r, r, r" - { - COMPAT_2 (OP_18007E0 ()); - } - - - - // SDIVHUN - rrrrr,111111,RRRRR + wwwww,00110,iiii,10:XI:::sdivhun - *v850ea - "sdivhun , r, r, r" - { - COMPAT_2 (OP_18207E0 ()); - } - - - - // SDIVN - rrrrr,111111,RRRRR + wwwww,00111,iiii,00:XI:::sdivn - *v850ea - "sdivn , r, r, r" - { - COMPAT_2 (OP_1C007E0 ()); - } - - - - // SDIVUN - rrrrr,111111,RRRRR + wwwww,00111,iiii,10:XI:::sdivun - *v850ea - "sdivun , r, r, r" - { - COMPAT_2 (OP_1C207E0 ()); - } - - - - // PUSHML - 000001111110,LLLL + LLLLLLLLLLLL,S,001:XIV:::pushml - *v850ea - "pushml " - { - int i; - SAVE_2; - - trace_input ("pushml", OP_PUSHPOP3, 0); - - /* Store the registers with lower number registers being placed at - higher addresses. */ - - for (i = 0; i < 15; i++) - if ((OP[3] & (1 << type3_regs[ i ]))) - { - SP -= 4; - store_mem (SP & ~ 3, 4, State.regs[ i + 1 ]); - } - - if (OP[3] & (1 << 3)) - { - SP -= 4; - - store_mem (SP & ~ 3, 4, PSW); - } - - if (OP[3] & (1 << 19)) - { - SP -= 8; - - if ((PSW & PSW_NP) && ((PSW & PSW_EP) == 0)) - { - store_mem ((SP + 4) & ~ 3, 4, FEPC); - store_mem ( SP & ~ 3, 4, FEPSW); - } - else - { - store_mem ((SP + 4) & ~ 3, 4, EIPC); - store_mem ( SP & ~ 3, 4, EIPSW); - } - } - - trace_output (OP_PUSHPOP2); - } - - - - // PUSHHML - 000001111110,LLLL + LLLLLLLLLLLL,S,011:XIV:::pushmh - *v850ea - "pushhml " - { - COMPAT_2 (OP_307E0 ()); - } - - - - // POPML - 000001111111,LLLL + LLLLLLLLLLLL,S,001:XIV:::popml - *v850ea - "popml " - { - COMPAT_2 (OP_107F0 ()); - } - - - - // POPMH - 000001111111,LLLL + LLLLLLLLLLLL,S,011:XIV:::popmh - *v850ea - "popmh " - { - COMPAT_2 (OP_307F0 ()); - } - --- 1095,1102 ----