RFA: Add support for CLASS_IGNORE and ARG_NIM4

[Nick Clifton <nickc@cambridge.redhat.com>]

Hi Guys,

  The binutils z8k sources were recently updated to add a new opcode
  class - CLASS_IGNORE - and a new immediate argument type -
  ARG_NIM4.  This patch adds support for these changes to the z8k
  simulator.

  OK to apply ?

Cheers
        Nick

2002-04-29  Nick Clifton  <nickc@cambridge.redhat.com>

	* writecode.c (lookup_inst): Ignore CLASS_IGNORE.
        (info_args): Treat CLASS_IGNORE like CLASS_BIT.
        Handle ARG_NIM4.
        (info_len_in_words): Handle CLASS_IGNORE and ARG_NIM4.


Index: sim/z8k/writecode.c
===================================================================
RCS file: /cvs/src/src/sim/z8k/writecode.c,v
retrieving revision 1.1.1.1
diff -c -3 -p -w -r1.1.1.1 writecode.c
*** sim/z8k/writecode.c	16 Apr 1999 01:35:14 -0000	1.1.1.1
--- sim/z8k/writecode.c	29 Apr 2002 12:53:07 -0000
*************** lookup_inst (what)
*** 139,144 ****
--- 139,146 ----
  		    nibl_matched = 0;
  		  break;
  
+ 		case CLASS_IGNORE:
+ 		  break;
  		case CLASS_BIT:
  		  if (datum_value != instr_nibl)
  		    nibl_matched = 0;
*************** info_args (p)
*** 539,544 ****
--- 541,547 ----
  	case CLASS_BIT_1OR2:
  	  emit ("register unsigned int imm_src=(<insn_4>& 2)?2:1;\n");
  	  break;
+ 	case CLASS_IGNORE:
  	case CLASS_BIT:
  	  /* Just ignore these, we've already decoded this bit */
  	  nibs++;
*************** break;	  
*** 589,594 ****
--- 592,601 ----
  		emit ("register unsigned int imm_src=<insn_4>;\n");
  		nibs++;
  		break;
+ 	      case ARG_NIM4:
+ 		emit ("register unsigned int imm_src = - <insn_4>;\n");
+ 		nibs++;
+ 		break;
  	      case ARG_IMM2:
  		emit ("register unsigned int imm_src=<insn_4> & 0x2;\n");
  		nibs++;
*************** info_len_in_words (o)
*** 1938,1943 ****
--- 1945,1951 ----
      {
        switch (*p & CLASS_MASK)
  	{
+ 	case CLASS_IGNORE:
  	case CLASS_BIT:
  	case CLASS_REGN0:
  	case CLASS_REG:
*************** info_len_in_words (o)
*** 1959,1964 ****
--- 1967,1973 ----
  	      break;
  	    case ARG_IMM2:
  	    case ARG_IMM4:
+ 	    case ARG_NIM4:
  	    case ARG_IMM4M1:
  	    case ARG_IMM_1:
  	    case ARG_IMM_2: