Index: gdb/mips-tdep.c
===================================================================
RCS file: /cvs/src/src/gdb/mips-tdep.c,v
retrieving revision 1.490
diff -u -p -r1.490 mips-tdep.c
--- gdb/mips-tdep.c	22 Feb 2009 01:02:17 -0000	1.490
+++ gdb/mips-tdep.c	4 Mar 2009 21:39:25 -0000
@@ -440,13 +440,27 @@ mips_register_name (struct gdbarch *gdba
     "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
   };
 
+  /* MIPS GPR register numbers, as used by assembler.  Order must
+     reflect gdb's regno<->MIPS register number mapping which is 
+     currently 1-1.  */
+  static char *mips_gpr_numeric_names[] = {
+    "0", "1", "2", "3", "4", "5", "6", "7",
+    "8", "9", "10", "11", "12", "13", "14", "15",
+    "16", "17", "18", "19", "20", "21", "22", "23",
+    "24", "25", "26", "27", "28", "29", "30", "31"
+  };
+
   enum mips_abi abi = mips_abi (gdbarch);
 
-  /* Map [gdbarch_num_regs .. 2*gdbarch_num_regs) onto the raw registers, 
-     but then don't make the raw register names visible.  */
+  /* Map [gdbarch_num_regs .. 2*gdbarch_num_regs) onto the raw registers.  */
   int rawnum = regno % gdbarch_num_regs (gdbarch);
   if (regno < gdbarch_num_regs (gdbarch))
-    return "";
+    {
+      if (regno >= 0 && regno < 32)
+	return mips_gpr_numeric_names [regno];
+      else
+	return "";
+    }
 
   /* The MIPS integer registers are always mapped from 0 to 31.  The
      names of the registers (which reflects the conventions regarding
@@ -4601,7 +4615,6 @@ mips_print_registers_info (struct gdbarc
 {
   if (regnum != -1)		/* do one specified register */
     {
-      gdb_assert (regnum >= gdbarch_num_regs (gdbarch));
       if (*(gdbarch_register_name (gdbarch, regnum)) == '\0')
 	error (_("Not a valid register for the current processor type"));