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boundary="------------cIyfprd40LdKfwn4OWXOA0zf" Message-ID: Date: Tue, 29 Sep 2026 14:05:46 +0530 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v1] PowerPC: Add support for Dense Math registers (RFC02653) To: Ulrich Weigand , "gdb-patches@sourceware.org" Cc: "cel@linux.ibm.com" , Abhay Kandpal References: <20260924063013.288753-1-abhay@linux.ibm.com> <4b8f1c34708d1b5373966c7995f53a5e7f1d548f.camel@de.ibm.com> <687032cb-729a-437e-b1cc-0fa01772e0ac@linux.ibm.com> From: Abhay Kandpal Content-Language: en-GB In-Reply-To: X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: 61Y8zMlN-ieZF_xZC7xonIt53rl4zMTe X-Proofpoint-GUID: 61Y8zMlN-ieZF_xZC7xonIt53rl4zMTe X-Proofpoint-Spam-Info: AW1haW4tMjYwOTI5MDAzNCBTYWx0ZWRfX5u/CX7lBIJRQ iOTt8XHkDeWJQgDv5DWgvw7DBH4cY677VmvTGOtugFUaTXxdolOZBTo2L+qQTMC0tpIfvsF37AD qceqyYmZB82dYo81Ym5aMVwYzTA+lcc= X-Authority-Analysis: v=2.4 cv=Vv62kO2n c=1 sm=1 tr=0 ts=6abb7869 cx=c_pps a=bLidbwmWQ0KltjZqbj+ezA==:117 a=bLidbwmWQ0KltjZqbj+ezA==:17 a=VdqzKS8jKosA:10 a=VkNPw1HP01LnGYTKEx00:22 a=RnoormkPH1_aCDwRdu11:22 a=Y2IxJ9c9Rs8Kov3niI8_:22 a=r77TgQKjGQsHNAKrUKIA:9 a=VnNF1IyMAAAA:8 a=O_-OZW6xSfCN2ZJeBG0A:9 a=QEXdDO2ut3YA:10 a=vdU1x8LOaOAPeDUM:21 a=_W_S_7VecoQA:10 a=lqcHg5cX4UMA:10 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTI5MDAzNCBTYWx0ZWRfX2Gno6SEaI6ln 0bQykfce73NJDud/UhsDctTtAxcJtWrmOR/00FMmYsFgNHxmCTnmlP36Yqm4u+OPedzFYYULshy nivLswtW63Ob7fBksEmWrJd8h5ywpfBEfKZLHu3lhWQKA1Gou73RoCmIdCPYoMVNZJeAlKsfQRt V1Eu2oUxpKX2iiX1qx9zp4bVu7/g2zi1WweUE+TKqLzPlEZG+0XMTbZgMG9ndmpyhO2MtZ4x//R TOwKq+yAkXGz3PokZYFHuK6HzddCJAPfpVDgCkM34minDl3phxLiDk9OVRfJewvb7elIbH3z/5R 3jJLPHlPAPzDERTlJt5AgH+gO0XFyNhThcV9ocPCBYsKvHbH+tweo9d/5/f33204pbjn0Hpwe4K blOlWrzALxSXwzxHctkE1FRuUSUT0cgPYCAMJQ60swY3WuSgumwfYnvPz4j1qM74fgSGX3JbJt+ ONhtRwHd95A16XSspaw== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-29_03,2026-09-21_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 spamscore=0 phishscore=0 bulkscore=0 adultscore=0 priorityscore=1501 malwarescore=0 clxscore=1015 lowpriorityscore=0 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2609290034 X-BeenThere: gdb-patches@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gdb-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gdb-patches-bounces~public-inbox=simark.ca@sourceware.org This is a multi-part message in MIME format. --------------cIyfprd40LdKfwn4OWXOA0zf Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Hi Ulrich, On 28/09/26 14:52, Ulrich Weigand wrote: > Abhay Kandpal wrote: > >> The existing names encode the base ISA level, but DMR is a later ISA >> feature layered on an isa207-derived description, so isa207-dmr would >> misstate the ISA level. A few options: >> >> 1. powerpc-isa207-dmr-vsx64l - names the base feature set the description extends >> 2. powerpc-isa32-dmr-vsx64l - names DMR's own ISA level (ISA 3.2) >> 3. powerpc-dmr-vsx64l - as posted, no ISA level > I'm not familiar with ISA 3.2 - is DMR mandatory or optional in 3.2? I checked with our architecture team. DMR can't be disabled independently, it depends on VSX being enabled, and an ISA 3.2 implementation running with VSX disabled isn't a configuration that's supported in practice. So there is no realistic ISA 3.2 target without DMR. > And are there any *other* 3.2 features that GDB needs to implement? No - DMR is the only new architected register state in ISA 3.2, so the GDB work is limited to these registers. > > I'd prefer "powerpc-isa32-vsx64l" to refer to an implementation of > all mandatory features (including DMR if mandatory), and if DMR is > optional, then in addition "powerpc-isa32-dmr-vsx64l" for the > combination of mandatory ISA 3.2 features plus DMR. Given the above, v2 uses a single description,|powerpc-isa32-vsx32l/64l|, which includes DMR. Your other comments are addressed in v2 as well. Regards, Abhay > > >> So in v2 I'll convert the native side to the regset mechanism >> throughout: fetch_regset/store_regset with NT_PPC_DMR in >> fetch_register, fetch_ppc_registers, store_register and >> store_ppc_registers, and a regset-based availability check in >> read_description. That removes the need for the >> PTRACE_GETDMREGS/PTRACE_SETDMREGS defines, so I'll drop the >> block rather than move it - unless something still needs them, >> in which case I'll relocate it as you suggest. > No, if they're not needed, it's better to drop these defines. > >> Yes - PPC_FEATURE2_DMF (0x00008000, Dense Math Facility). I'll add > that >> check. The kernel does save and restore these registers across context >> switches. The hwcap bit and the DMR ptrace support are currently in >> separate kernel branches here, so I'm assembling a tree with both before >> validating v2. > Thanks! > > Bye, > Ulrich --------------cIyfprd40LdKfwn4OWXOA0zf Content-Type: text/html; charset=UTF-8 Content-Transfer-Encoding: 7bit 
Hi Ulrich,
On 28/09/26 14:52, Ulrich Weigand wrote:
Abhay Kandpal <abhay@linux.ibm.com> wrote:
 

The existing names encode the base ISA level, but DMR is a later ISA
feature layered on an isa207-derived description, so isa207-dmr would 
misstate the ISA level. A few options:

1. powerpc-isa207-dmr-vsx64l - names the base feature set the description extends
2. powerpc-isa32-dmr-vsx64l - names DMR's own ISA level (ISA 3.2)
3. powerpc-dmr-vsx64l - as posted, no ISA level

I'm not familiar with ISA 3.2 - is DMR mandatory or optional in 3.2?
I checked with our architecture team. DMR can't be disabled independently,
it depends on VSX being enabled, and an ISA 3.2 implementation running with
VSX disabled isn't a configuration that's supported in practice. So there is
no realistic ISA 3.2 target without DMR.
And are there any *other* 3.2 features that GDB needs to implement?
No - DMR is the only new architected register state in ISA 3.2,
so the GDB work is limited to these registers.

I'd prefer "powerpc-isa32-vsx64l" to refer to an implementation of
all mandatory features (including DMR if mandatory), and if DMR is
optional, then in addition "powerpc-isa32-dmr-vsx64l" for the
combination of mandatory ISA 3.2 features plus DMR.
Given the above, v2 uses a single description, powerpc-isa32-vsx32l/64l, 
which includes DMR. Your other comments are addressed in v2 as well.

Regards,
Abhay

 

So in v2 I'll convert the native side to the regset mechanism
throughout: fetch_regset/store_regset with NT_PPC_DMR in
fetch_register, fetch_ppc_registers, store_register and
store_ppc_registers, and a regset-based availability check in
read_description. That removes the need for the 
PTRACE_GETDMREGS/PTRACE_SETDMREGS defines, so I'll drop the 
block rather than move it - unless something still needs them,
in which case I'll relocate it as you suggest.

No, if they're not needed, it's better to drop these defines.


Yes - PPC_FEATURE2_DMF (0x00008000, Dense Math Facility). I'll add

that

check. The kernel does save and restore these registers across context 
switches. The hwcap bit and the DMR ptrace support are currently in 
separate kernel branches here, so I'm assembling a tree with both before
validating v2.

Thanks!

Bye,
Ulrich
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