From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 123911 invoked by alias); 14 Nov 2018 17:42:27 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Received: (qmail 123892 invoked by uid 89); 14 Nov 2018 17:42:25 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-2.7 required=5.0 tests=AWL,BAYES_00,SPF_HELO_PASS,SPF_SOFTFAIL autolearn=no version=3.3.2 spammy= X-HELO: mail.baldwin.cx Received: from bigwig.baldwin.cx (HELO mail.baldwin.cx) (96.47.65.170) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Wed, 14 Nov 2018 17:42:22 +0000 Received: from John-Baldwins-MacBook-Pro-2.local (ralph.baldwin.cx [66.234.199.215]) by mail.baldwin.cx (Postfix) with ESMTPSA id 87F4C10A87D; Wed, 14 Nov 2018 12:42:20 -0500 (EST) Subject: Re: [RFC] gdb/riscv: Add target description support To: Andrew Burgess References: <20181108160745.24600-1-andrew.burgess@embecosm.com> <20181114142942.GL16539@embecosm.com> Cc: gdb-patches@sourceware.org, jimw@sifive.com, palmer@sifive.com From: John Baldwin Openpgp: preference=signencrypt Message-ID: Date: Wed, 14 Nov 2018 17:42:00 -0000 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.12; rv:52.0) Gecko/20100101 Thunderbird/52.9.1 MIME-Version: 1.0 In-Reply-To: <20181114142942.GL16539@embecosm.com> Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit X-IsSubscribed: yes X-SW-Source: 2018-11/txt/msg00229.txt.bz2 On 11/14/18 6:29 AM, Andrew Burgess wrote: > * John Baldwin [2018-11-08 10:32:57 -0800]: > >> On 11/8/18 8:07 AM, Andrew Burgess wrote: >>> This commit adds target description support for riscv. >>> >>> I've used the split feature approach for specifying the architectural >>> features, and the CSR feature is auto-generated from the riscv-opc.h >>> header file. >> >> In general this looks fine to me (as far as I am familiar with the >> target descriptions). The only possible question/comment I have is if >> you considered describing fields of specific registers such as the FP >> status registers or MSTATUS, etc. as fields in the XML to replace the >> current special cases in riscv_print_one_register_info(). > > I took a look at switching over to using flag fields in the xml > description, but in the end I decided against this. > > The main reason is that there appears to be a bug with registers > described as a flag type, I was unable to assign to the register. > What I saw was an invalid cast error. > > I defined the type like this: > > > > > > > > > > > > But then, when I try to assign to the register I see this error: > > (gdb) set $fflags=0x3 > Invalid cast Weird, on x86 you can assign raw values to $eflags which is also described as a flags field: ... (gdb) p $eflags $1 = [ PF IF ] (gdb) p/x $eflags $2 = 0x206 (gdb) set $eflags = $eflags | 1 (gdb) p $eflags $3 = [ CF PF IF ] However, if it doesn't work I think it's fine to not use it. I just wanted to make sure you weren't duplicating work you wouldn't need. >> Some related-ish questions (though not about this patch): I wonder if we >> can do things with pseudo registers to automatically derive FFLAGS and >> FRM if a target provides FCSR. > > I like this idea a lot, and I definitely plan to implement this, just > because I think it would be a neat feature. However, my understanding > is that FFLAGS and FRM _are_ real CSRs, at least in the sense that > there's a real CSR offset from which we can read to extract the FFLAGS > or FRM part of FCSR. So, initially I'd prefer to merge this with > these registers as real registers. > > But I think it would be great if for targets that only announce FCSR, > we could automatically emulate FRM and FCSR. Ok. I had assumed that we would have to use pseudo registers to do this, but perhaps it can be done another way that allows a target to provide them explicitly if it chose. -- John Baldwin                                                                            Â