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Mon, 25 Jan 2021 18:31:56 +0000 Subject: Re: [Patch] GDB: aarch64: Add ability to step over a BR/BLR instruction Thread-Topic: [Patch] GDB: aarch64: Add ability to step over a BR/BLR instruction Thread-Index: AQHWUUqlDO5w7rG1KkW9eumw3CukZKj1/NiAgAAIewCAGmWhAIAFCscAgAAJ/gCAACQ+gIArl+SAgBe9FQA= Date: Mon, 25 Jan 2021 18:31:56 +0000 Message-ID: References: <9226b8ae-aaea-65c3-3e86-f607b11fd375@linaro.org> <9EACDC38-BB8D-4804-AD19-057E3309819A@arm.com> <3d86bcb9-dedd-6eb2-7cff-e8349d4b20da@palves.net> In-Reply-To: Accept-Language: en-GB, en-US Content-Language: en-GB X-MS-Has-Attach: yes X-MS-TNEF-Correlator: x-ms-exchange-imapappendstamp: AM6PR08MB3157.eurprd08.prod.outlook.com (15.20.3348.016) user-agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.9.0 Authentication-Results-Original: palves.net; dkim=none (message not signed) header.d=none;palves.net; dmarc=none action=none header.from=arm.com; x-originating-ip: [217.140.99.251] x-ms-publictraffictype: Email X-MS-Office365-Filtering-HT: Tenant X-MS-Office365-Filtering-Correlation-Id: ddfabdf7-1df4-45af-382b-08d8c15f8372 x-ms-traffictypediagnostic: AS8PR08MB6470:|DBBPR08MB4629: x-ms-exchange-transport-forked: True X-Microsoft-Antispam-PRVS: x-checkrecipientrouted: true nodisclaimer: true x-ms-oob-tlc-oobclassifiers: OLM:9508;OLM:9508; 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charset="iso-8859-1" Content-ID: <710A95314F02F248AED3210C98A0433D@arm.com> Content-Transfer-Encoding: quoted-printable I'd like to ping the below patch.=0A= =0A= N.b. When I last sent it up running with `--target_board=3Dnative-gdbserver= ` was not working, but I ran the tests after a rebase just now and everythi= ng now passes.=0A= =0A= Given the problem I noticed before was not in this patch (explanation in th= e previous email), and this patch applies cleanly now, is this good to go i= n?=0A= =0A= Regards,=0A= Matthew=0A= =0A= On 20/08/2020 13:41, Matthew Malcomson wrote:=0A= >> On 7/23/20 5:48 PM, Matthew Malcomson wrote:=0A= >>> +=0A= >>> +# Test for displaced stepping over the BLR instruction.=0A= >>> +gdb_test "run" \=0A= >>> + "Starting program.*Breakpoint $decimal.*" \=0A= >>> + "Run until BLR test start"=0A= >>> +=0A= >>=0A= >> Please don't use "run" directly. Use one of runto, runto_main,=0A= >> gdb_run_cmd instead. See amd64-disp-step.exp for example.=0A= >>=0A= >> If you use "run" directly, then the testcase won't run against=0A= >> gdbserver. Please make sure this passes cleanly:=0A= >>=0A= >> $ make check \=0A= >> RUNTESTFLAGS=3D"--target_board=3Dnative-gdbserver" \=0A= >> TESTS=3D"gdb.arch/aarch64-disp-stepping.exp"=0A= >>=0A= > =0A= > =0A= > Thanks for the suggestion, as it turns out trying to use this meant I not= iced a=0A= > bunch of other things, and I couldn't get this to pass cleanly ...=0A= > =0A= > I have now found some existing cases for displaced stepping on AArch64 in= =0A= > insn-reloc.c driven by disp-step-insn-reloc.exp.=0A= > Hence I've added the BR and BLR testcases there rather than making my own= test=0A= > driver.=0A= > =0A= > However, it seems the existing tests already show there are some problems= =0A= > with AArch64 displaced stepping on gdbserver -- it seems there's some pro= blem=0A= > with ensuring the context is the same when running using=0A= > `--target_board=3Dnative-gdbserver`.=0A= > I see errors on the existing cbz, tbnz, bcond_true, and bcond_false tests= .=0A= > The bl test fails because of an illegal instruction in the bcond_false te= st=0A= > that only gets run when the test is failing (swithing `b.eq 0b` in that= =0A= > function to `b.eq 0f` works for me and I'll make that switch in a differe= nt=0A= > patch).=0A= > The new BR and BLR tests also fail from what seems to be using the values= of=0A= > the registers as seen by `info registers` which don't appear to be gettin= g=0A= > updated correctly as the program proceeds.=0A= > I can see the same problem on the instruction `mov x1, x2` (that the valu= e of=0A= > x2 used is what GDB prints out with `info registers` rather than the valu= e it=0A= > should be based on the code.=0A= > =0A= > So, the testcase does not pass cleanly with the command you suggested, bu= t I=0A= > think it's not a problem with the changes I've made.=0A= > =0A= > -------- MOV Testcase that fails under gdbserver=0A= > Putting this function in the insn-reloc.c (and placing it in the test arr= ay so=0A= > it gets called before the program exits from a broken test) demonstrates = that=0A= > displaced stepping doesn't seem to use the correct values from the gdbser= ver=0A= > context.=0A= > =0A= > =0A= > static void=0A= > can_relocate_mov (void)=0A= > {=0A= > int ok =3D 0;=0A= > asm (" mov x1, #1\n"=0A= > "set_point15:\n"=0A= > " mov %[ok], x1\n"=0A= > : [ok] "=3Dr" (ok)=0A= > : : "x1");=0A= > if (ok =3D=3D 1)=0A= > pass();=0A= > else=0A= > fail();=0A= > }=0A= > -------=0A= > =0A= > =0A= > =0A= > If Ok could someone apply this for me (I don't have commit rights)?=0A= > =0A= > =0A= > ###### Proposed commit message and patch below=0A= > =0A= > Enable displaced stepping over a BR/BLR instruction=0A= > =0A= > Displaced stepping over an instruction executes a instruction in a=0A= > scratch area and then manually fixes up the PC address to leave=0A= > execution where it would have been if the instruction were in its=0A= > original location.=0A= > =0A= > The BR instruction does not need modification in order to run correctly= =0A= > at a different address, but the displaced step fixup method should not=0A= > manually adjust the PC since the BR instruction sets that value already.= =0A= > =0A= > The BLR instruction should also avoid such a fixup, but must also have=0A= > the link register modified to point to just after the original code=0A= > location rather than back to the scratch location.=0A= > =0A= > This patch adds the above functionality.=0A= > We add this functionality by modifying aarch64_displaced_step_others=0A= > rather than by adding a new visitor method to aarch64_insn_visitor.=0A= > We choose this since it seems that visitor approach is designed=0A= > specifically for PC relative instructions (which must always be modified= =0A= > when executed in a different location).=0A= > =0A= > It seems that the BR and BLR instructions are more like the RET=0A= > instruction which is already handled specially in=0A= > aarch64_displaced_step_others.=0A= > =0A= > This also means the gdbserver code to relocate an instruction when=0A= > creating a fast tracepoint does not need to be modified, since nothing=0A= > special is needed for the BR and BLR instructions there.=0A= > =0A= > Regression tests showed nothing untoward on native aarch64.=0A= > I noticed that the disp-step-insn-reloc.exp test produces quite a few=0A= > errors when running with RUNTESTFLAGS=3D"--target_board=3Dnative-gdbserve= r"=0A= > (bcond_true, cbz, tbnz, bcond_false, blr, br).=0A= > There are existing errors, and the BLR and BR tests also fail.=0A= > It seems the context is not preserved properly for displaced=0A= > stepping(for the Conditional instructions the condition flags are not=0A= > preserved, and for BLR/BR the general registers are not preserved).=0A= > The same problem can be observed when using displaced stepping on a=0A= > `mov %[ok], x1` instruction, so I'm confident this is not a problem with= =0A= > my patch.=0A= > =0A= > ------#####=0A= > Original observed (mis)behaviour before was that displaced stepping over= =0A= > a BR or BLR instruction would not execute the function they called.=0A= > Most easily seen by putting a breakpoint with a condition on such an=0A= > instruction and a print statement in the functions they called.=0A= > When run with the breakpoint enabled the function is not called and=0A= > "numargs called" is not printed.=0A= > When run with the breakpoint disabled the function is called and the=0A= > message is printed.=0A= > =0A= > --- GDB Session=0A= > hw-a20-10:gcc-source [15:57:14] % gdb ../using-blr=0A= > Reading symbols from ../using-blr...done.=0A= > (gdb) disassemble blr_call_value=0A= > Dump of assembler code for function blr_call_value:=0A= > ...=0A= > 0x0000000000400560 <+28>: blr x2=0A= > ...=0A= > 0x00000000004005b8 <+116>: ret=0A= > End of assembler dump.=0A= > (gdb) break *0x0000000000400560=0A= > Breakpoint 1 at 0x400560: file ../using-blr.c, line 22.=0A= > (gdb) condition 1 10 =3D=3D 0=0A= > (gdb) run=0A= > Starting program: /home/matmal01/using-blr=0A= > [Inferior 1 (process 33279) exited with code 012]=0A= > (gdb) disable 1=0A= > (gdb) run=0A= > Starting program: /home/matmal01/using-blr=0A= > numargs called=0A= > [Inferior 1 (process 33289) exited with code 012]=0A= > (gdb)=0A= > =0A= > Test program:=0A= > ---- using-blr ----=0A= > \#include =0A= > typedef int (foo) (int, int);=0A= > typedef void (bar) (int, int);=0A= > struct sls_testclass {=0A= > foo *x;=0A= > bar *y;=0A= > int left;=0A= > int right;=0A= > };=0A= > =0A= > __attribute__ ((noinline))=0A= > int blr_call_value (struct sls_testclass x)=0A= > {=0A= > int retval =3D x.x(x.left, x.right);=0A= > if (retval % 10)=0A= > return 100;=0A= > return 9;=0A= > }=0A= > =0A= > __attribute__ ((noinline))=0A= > int blr_call (struct sls_testclass x)=0A= > {=0A= > x.y(x.left, x.right);=0A= > if (x.left % 10)=0A= > return 100;=0A= > return 9;=0A= > }=0A= > =0A= > int=0A= > numargs (__attribute__ ((unused)) int left, __attribute__ ((unused)) int = right)=0A= > {=0A= > printf("numargs called\n");=0A= > return 10;=0A= > }=0A= > =0A= > void=0A= > altfunc (__attribute__ ((unused)) int left, __attribute__ ((unused)) int = right)=0A= > {=0A= > printf("altfunc called\n");=0A= > }=0A= > =0A= > int main(int argc, char **argv)=0A= > {=0A= > struct sls_testclass x =3D { .x =3D numargs, .y =3D altfunc, .left =3D= 1, .right =3D 2 };=0A= > if (argc > 2)=0A= > {=0A= > blr_call (x);=0A= > }=0A= > else=0A= > blr_call_value (x);=0A= > return 10;=0A= > }=0A= > =0A= > ------=0A= > =0A= > gdb/ChangeLog:=0A= > 2020-08-19 Matthew Malcomson =0A= > =0A= > * aarch64-tdep.c (aarch64_displaced_step_others): Account for=0A= > BLR and BR instructions.=0A= > * arch/aarch64-insn.h (enum aarch64_opcodes): Add BR opcode.=0A= > (enum aarch64_masks): New.=0A= > =0A= > gdb/testsuite/ChangeLog:=0A= > 2020-08-19 Matthew Malcomson =0A= > =0A= > * gdb.arch/insn-reloc.c: Add tests for BR and BLR.=0A= > =0A= > =0A= > =0A= > ############### Attachment also inlined for ease of reply ########= #######=0A= > =0A= > =0A= > diff --git a/gdb/aarch64-tdep.c b/gdb/aarch64-tdep.c=0A= > index 5e7d0d0b8682af04ce4f01fd999d26c9eb459932..d247108f53bf045a018b2bf85= 284088563868ae0 100644=0A= > --- a/gdb/aarch64-tdep.c=0A= > +++ b/gdb/aarch64-tdep.c=0A= > @@ -2974,15 +2974,22 @@ aarch64_displaced_step_others (const uint32_t ins= n,=0A= > struct aarch64_displaced_step_data *dsd=0A= > =3D (struct aarch64_displaced_step_data *) data;=0A= > =0A= > - aarch64_emit_insn (dsd->insn_buf, insn);=0A= > - dsd->insn_count =3D 1;=0A= > -=0A= > - if ((insn & 0xfffffc1f) =3D=3D 0xd65f0000)=0A= > + uint32_t masked_insn =3D (insn & CLEAR_Rn_MASK);=0A= > + if (masked_insn =3D=3D BLR)=0A= > {=0A= > - /* RET */=0A= > - dsd->dsc->pc_adjust =3D 0;=0A= > + /* Emit a BR to the same register and then update LR to the origin= al=0A= > + address (similar to aarch64_displaced_step_b). */=0A= > + aarch64_emit_insn (dsd->insn_buf, insn & 0xffdfffff);=0A= > + regcache_cooked_write_unsigned (dsd->regs, AARCH64_LR_REGNUM,=0A= > + data->insn_addr + 4);=0A= > }=0A= > else=0A= > + aarch64_emit_insn (dsd->insn_buf, insn);=0A= > + dsd->insn_count =3D 1;=0A= > +=0A= > + if (masked_insn =3D=3D RET || masked_insn =3D=3D BR || masked_insn =3D= =3D BLR)=0A= > + dsd->dsc->pc_adjust =3D 0;=0A= > + else=0A= > dsd->dsc->pc_adjust =3D 4;=0A= > }=0A= > =0A= > diff --git a/gdb/arch/aarch64-insn.h b/gdb/arch/aarch64-insn.h=0A= > index 6a63ce9c2005acd6fe018a12c640f1be01751d6b..f261363feefe4e93e155434ba= 6d3df8e4b994c9f 100644=0A= > --- a/gdb/arch/aarch64-insn.h=0A= > +++ b/gdb/arch/aarch64-insn.h=0A= > @@ -40,7 +40,9 @@ enum aarch64_opcodes=0A= > CBNZ =3D 0x21000000 | B,=0A= > TBZ =3D 0x36000000 | B,=0A= > TBNZ =3D 0x37000000 | B,=0A= > + /* BR 1101 0110 0001 1111 0000 00rr rrr0 0000 */=0A= > /* BLR 1101 0110 0011 1111 0000 00rr rrr0 0000 */=0A= > + BR =3D 0xd61f0000,=0A= > BLR =3D 0xd63f0000,=0A= > /* RET 1101 0110 0101 1111 0000 00rr rrr0 0000 */=0A= > RET =3D 0xd65f0000,=0A= > @@ -107,6 +109,14 @@ enum aarch64_opcodes=0A= > NOP =3D (0 << 5) | HINT,=0A= > };=0A= > =0A= > +/* List of useful masks. */=0A= > +enum aarch64_masks=0A= > +{=0A= > + /* Used for masking out an Rn argument from an opcode. */=0A= > + CLEAR_Rn_MASK =3D 0xfffffc1f,=0A= > +};=0A= > +=0A= > +=0A= > /* Representation of a general purpose register of the form xN or wN.= =0A= > =0A= > This type is used by emitting functions that take registers as opera= nds. */=0A= > diff --git a/gdb/testsuite/gdb.arch/insn-reloc.c b/gdb/testsuite/gdb.arch= /insn-reloc.c=0A= > index 106fd6ed1e8cb146863ff767130a82814ee89f86..9e7cf7a12df387e85881e19bd= ef7372046ba2861 100644=0A= > --- a/gdb/testsuite/gdb.arch/insn-reloc.c=0A= > +++ b/gdb/testsuite/gdb.arch/insn-reloc.c=0A= > @@ -512,6 +512,99 @@ can_relocate_bl (void)=0A= > : : : "x30"); /* Test that LR is updated correctly. */=0A= > }=0A= > =0A= > +/* Make sure we can relocate a BR instruction.=0A= > +=0A= > + ... Set x0 to target=0A= > + set_point12:=0A= > + BR x0 ; jump to target (tracepoint here).=0A= > + MOV %[ok], #0=0A= > + B end=0A= > + target:=0A= > + MOV %[ok], #1=0A= > + end=0A= > +=0A= > + */=0A= > +=0A= > +static void=0A= > +can_relocate_br (void)=0A= > +{=0A= > + int ok =3D 0;=0A= > +=0A= > + asm (" movz x0, :abs_g3:0f\n"=0A= > + " movk x0, :abs_g2_nc:0f\n"=0A= > + " movk x0, :abs_g1_nc:0f\n"=0A= > + " movk x0, :abs_g0_nc:0f\n"=0A= > + "set_point12:\n"=0A= > + " br x0\n"=0A= > + " mov %[ok], #0\n"=0A= > + " b 1f\n"=0A= > + "0:\n"=0A= > + " mov %[ok], #1\n"=0A= > + "1:\n"=0A= > + : [ok] "=3Dr" (ok)=0A= > + :=0A= > + : "0");=0A= > +=0A= > + if (ok =3D=3D 1)=0A= > + pass ();=0A= > + else=0A= > + fail ();=0A= > +}=0A= > +=0A= > +/* Make sure we can relocate a BLR instruction.=0A= > +=0A= > + We use two different functions since the test runner expects one brea= kpoint=0A= > + per function and we want to test two different things.=0A= > + For BLR we want to test that the BLR actually jumps to the relevant= =0A= > + function, *and* that it sets the LR register correctly.=0A= > +=0A= > + Hence we create one testcase that jumps to `pass` using BLR, and one= =0A= > + testcase that jumps to `pass` if BLR has set the LR correctly.=0A= > +=0A= > + -- can_relocate_blr_jumps=0A= > + ... Set x0 to pass=0A= > + set_point13:=0A= > + BLR x0 ; jump to pass (tracepoint here).=0A= > +=0A= > + -- can_relocate_blr_sets_lr=0A= > + ... Set x0 to foo=0A= > + set_point14:=0A= > + BLR x0 ; jumps somewhere else (tracepoint here).=0A= > + BL pass ; ensures the LR was set correctly by the BLR.=0A= > +=0A= > + */=0A= > +=0A= > +static void=0A= > +can_relocate_blr_jumps (void)=0A= > +{=0A= > + int ok =3D 0;=0A= > +=0A= > + /* Test BLR indeed jumps to the target. */=0A= > + asm (" movz x0, :abs_g3:pass\n"=0A= > + " movk x0, :abs_g2_nc:pass\n"=0A= > + " movk x0, :abs_g1_nc:pass\n"=0A= > + " movk x0, :abs_g0_nc:pass\n"=0A= > + "set_point13:\n"=0A= > + " blr x0\n"=0A= > + : : : "x0","x30");=0A= > +}=0A= > +=0A= > +static void=0A= > +can_relocate_blr_sets_lr (void)=0A= > +{=0A= > + int ok =3D 0;=0A= > +=0A= > + /* Test BLR sets the LR correctly. */=0A= > + asm (" movz x0, :abs_g3:foo\n"=0A= > + " movk x0, :abs_g2_nc:foo\n"=0A= > + " movk x0, :abs_g1_nc:foo\n"=0A= > + " movk x0, :abs_g0_nc:foo\n"=0A= > + "set_point14:\n"=0A= > + " blr x0\n"=0A= > + " bl pass\n"=0A= > + : : : "x0","x30");=0A= > +}=0A= > +=0A= > #endif=0A= > =0A= > /* Functions testing relocations need to be placed here. GDB will read= =0A= > @@ -536,6 +629,9 @@ static testcase_ftype testcases[] =3D {=0A= > can_relocate_ldr,=0A= > can_relocate_bcond_false,=0A= > can_relocate_bl,=0A= > + can_relocate_br,=0A= > + can_relocate_blr_jumps,=0A= > + can_relocate_blr_sets_lr,=0A= > #endif=0A= > };=0A= > =0A= > =0A= =0A= --_002_fa78eb8c93cfafcab5fb2d9549ccf38earmcom_ Content-Type: text/x-patch; name="blr-with-new-tests.patch" Content-Description: blr-with-new-tests.patch Content-Disposition: attachment; filename="blr-with-new-tests.patch"; size=5067; creation-date="Mon, 25 Jan 2021 18:31:54 GMT"; modification-date="Mon, 25 Jan 2021 18:31:54 GMT" Content-Transfer-Encoding: base64 ZGlmZiAtLWdpdCBhL2dkYi9hYXJjaDY0LXRkZXAuYyBiL2dkYi9hYXJjaDY0LXRkZXAuYwppbmRl eCA1ZTdkMGQwYjg2ODJhZjA0Y2U0ZjAxZmQ5OTlkMjZjOWViNDU5OTMyLi5kMjQ3MTA4ZjUzYmYw NDVhMDE4YjJiZjg1Mjg0MDg4NTYzODY4YWUwIDEwMDY0NAotLS0gYS9nZGIvYWFyY2g2NC10ZGVw LmMKKysrIGIvZ2RiL2FhcmNoNjQtdGRlcC5jCkBAIC0yOTc0LDE1ICsyOTc0LDIyIEBAIGFhcmNo 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