From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 18938 invoked by alias); 20 Jun 2014 06:10:04 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Received: (qmail 18925 invoked by uid 89); 20 Jun 2014 06:10:02 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.7 required=5.0 tests=AWL,BAYES_00,RCVD_IN_DNSWL_LOW,SPF_HELO_PASS,SPF_PASS autolearn=ham version=3.3.2 X-HELO: na01-bl2-obe.outbound.protection.outlook.com Received: from mail-bl2lp0203.outbound.protection.outlook.com (HELO na01-bl2-obe.outbound.protection.outlook.com) (207.46.163.203) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES256-SHA encrypted) ESMTPS; Fri, 20 Jun 2014 06:10:00 +0000 Received: from BY2FFO11FD052.protection.gbl (10.1.14.32) by BY2FFO11HUB041.protection.gbl (10.1.14.82) with Microsoft SMTP Server (TLS) id 15.0.969.12; Fri, 20 Jun 2014 06:09:44 +0000 Received: from xsj-pvapsmtpgw01 (149.199.60.83) by BY2FFO11FD052.mail.protection.outlook.com (10.1.15.189) with Microsoft SMTP Server (TLS) id 15.0.969.12 via Frontend Transport; Fri, 20 Jun 2014 06:09:44 +0000 Received: from unknown-38-66.xilinx.com ([149.199.38.66] helo=xsj-smtp1) by xsj-pvapsmtpgw01 with esmtp (Exim 4.63) (envelope-from ) id 1Wxs1I-0002F8-Fw; Thu, 19 Jun 2014 23:09:52 -0700 From: Ajit Kumar Agarwal To: "gdb-patches@sourceware.org" CC: Michael Eager , Pedro Alves , Vinod Kathail , Vidhumouli Hunsigida , Nagaraju Mekala Subject: RE: [Patch, microblaze]: Add support of microblaze software single stepping Date: Fri, 20 Jun 2014 06:10:00 -0000 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-RCIS-Action: ALLOW Message-ID: X-EOPAttributedMessage: 0 X-Forefront-Antispam-Report: CIP:149.199.60.83;CTRY:US;IPV:NLI;IPV:NLI;EFV:NLI;SFV:NSPM;SFS:(6009001)(438001)(189002)(199002)(377424004)(53416004)(50466002)(31696002)(64706001)(47776003)(79102001)(92726001)(76482001)(87936001)(83072002)(2656002)(85852003)(99396002)(46406003)(97756001)(92566001)(86362001)(20776003)(77982001)(21056001)(46102001)(54356999)(50986999)(81342001)(19580395003)(83322001)(19580405001)(6806004)(44976005)(74502001)(74662001)(31966008)(1496007)(80022001)(85306003)(23726002)(95666004)(104016002)(74316001)(77096002)(81542001)(70736001)(33646001)(4396001);DIR:OUT;SFP:;SCL:1;SRVR:BY2FFO11HUB041;H:xsj-pvapsmtpgw01;FPR:;MLV:sfv;PTR:unknown-60-83.xilinx.com;MX:1;A:1;LANG:en; X-OriginatorOrg: xilinx.onmicrosoft.com X-Microsoft-Antispam: BCL:0;PCL:0;RULEID: X-Forefront-PRVS: 024847EE92 Received-SPF: Pass (: domain of xilinx.com designates 149.199.60.83 as permitted sender) receiver=; client-ip=149.199.60.83; helo=xsj-pvapsmtpgw01; Authentication-Results: spf=pass (sender IP is 149.199.60.83) smtp.mailfrom=ajit.kumar.agarwal@xilinx.com; X-SW-Source: 2014-06/txt/msg00723.txt.bz2 Please find the patch that supports the microblaze software single stepping= . This patch handles the cases of branch and return with delay slot and the imm instruction in microblaze. Could you please review and let me k= now if its okay.=20=20=20 [Patch, microblaze]: Add support of microblaze software single stepping =20=20=20=20 This patch adds the support of microblaze software single stepping. It handles the cases of branch and return with delay slot and imm instruct= ion in microblaze. =20=20=20=20 ChangeLog: 2014-06-19 Ajit Agarwal =20=20=20=20 * microblaze-tdep.c (microblaze_software_single_step): New. (microblaze_gdbarch_init): Use of set_gdbarch_software_single_step. =20=20=20=20 Signed-off-by:Ajit Agarwal ajitkum@xilinx.com --- gdb/microblaze-tdep.c | 79 +++++++++++++++++++++++++++++++++++++++++++++= ++++ 1 files changed, 79 insertions(+), 0 deletions(-) diff --git a/gdb/microblaze-tdep.c b/gdb/microblaze-tdep.c index 14c1b52..3de2f70 100644 --- a/gdb/microblaze-tdep.c +++ b/gdb/microblaze-tdep.c @@ -628,6 +628,83 @@ microblaze_stabs_argument_has_addr (struct gdbarch *gd= barch, struct type *type) return (TYPE_LENGTH (type) =3D=3D 16); } =20 +static int=20 +microblaze_software_single_step (struct frame_info *frame)=20 +{=20 + struct gdbarch *arch =3D get_frame_arch (frame);=20 + struct address_space *aspace =3D get_frame_address_space (frame);=20 + struct gdbarch_tdep *tdep =3D gdbarch_tdep (arch);=20 + enum bfd_endian byte_order =3D gdbarch_byte_order (arch);=20 + int ret =3D 0;=20 + int ii;=20 + CORE_ADDR pc;=20 + long insn; + enum microblaze_instr minstr;=20 + bfd_boolean isunsignednum;=20 + enum microblaze_instr_type insn_type;=20 + short delay_slots;=20 + int imm;=20 + bfd_boolean immfound =3D FALSE;=20 + CORE_ADDR breaks[2] =3D {-1,-1}; + CORE_ADDR address; + int targetvalid; + + /* Set a breakpoint at the next instruction */=20 + /* If the current instruction is an imm, set it at the inst after */=20 + /* If the instruction has a delay slot, skip the delay slot */=20 + pc =3D get_frame_pc (frame);=20 + insn =3D microblaze_fetch_instruction (pc);=20 + minstr =3D get_insn_microblaze (insn, &isunsignednum, &insn_type, &delay= _slots);=20 + if (insn_type =3D=3D immediate_inst)=20 + {=20 + int rd, ra, rb;=20 + immfound =3D TRUE;=20 + minstr =3D microblaze_decode_insn (insn, &rd, &ra, &rb, &imm);=20 + pc =3D pc + INST_WORD_SIZE;=20 + insn =3D microblaze_fetch_instruction (pc);=20 + minstr =3D get_insn_microblaze (insn, &isunsignednum, &insn_type, &d= elay_slots);=20 + }=20=20=20 + if (insn_type !=3D return_inst)=20 + breaks[0] =3D pc + delay_slots * INST_WORD_SIZE + INST_WORD_SIZE; +=20=20=20=20 + /* Now check for branch or return instructions */=20 + if (insn_type =3D=3D branch_inst || insn_type =3D=3D return_inst)=20 + {=20 + int limm;=20 + int lrd, lra, lrb;=20 + int ra, rb;=20 + bfd_boolean targetvalid;=20 + bfd_boolean unconditionalbranch;=20 + microblaze_decode_insn (insn, &lrd, &lra, &lrb, &limm);=20 + if (lra >=3D 0 && lra < MICROBLAZE_NUM_REGS)=20 + ra =3D get_frame_register_unsigned (frame, lra);=20 + else=20 + ra =3D 0;=20 + if (lrb >=3D 0 && lrb < MICROBLAZE_NUM_REGS)=20 + rb =3D get_frame_register_unsigned (frame, lrb);=20 + else=20 + rb =3D 0;=20 + address =3D microblaze_get_target_address (insn, immfound, imm, pc, = ra, rb, &targetvalid, &unconditionalbranch);=20 +=20=20=20=20=20=20=20=20 + if (!unconditionalbranch)=20 + breaks[1] =3D address; + }=20=20 +=20=20=20=20 + /* Insert the breakpoints */ + if (breaks[0] !=3D -1)=20 + { + insert_single_step_breakpoint (arch, aspace, breaks[0]);=20 + ret =3D 1;=20 + } + if (breaks[1] !=3D -1)=20 + {=20=20=20 + insert_single_step_breakpoint (arch, aspace, breaks[1]);=20=20=20=20= =20 + ret =3D 1;=20=20 + } + + return ret;=20 +} +=20 static void microblaze_write_pc (struct regcache *regcache, CORE_ADDR pc) { @@ -708,6 +785,8 @@ microblaze_gdbarch_init (struct gdbarch_info info, stru= ct gdbarch_list *arches) =20 set_gdbarch_breakpoint_from_pc (gdbarch, microblaze_breakpoint_from_pc); =20 + set_gdbarch_software_single_step (gdbarch, microblaze_software_single_st= ep); + set_gdbarch_frame_args_skip (gdbarch, 8); =20 set_gdbarch_print_insn (gdbarch, print_insn_microblaze); --=20 1.7.1 Thanks & Regards Ajit