Hi,

The simulator currently implements only the SH1 version of the mac.w
instruction.  On SH1 the MACH:MACL accumulator register is only 42-bit.  It
was extended to 64-bit on SH2 and every variant that followed after.

The issue probably never showed up because GCC hasn't been able to emit the
SH integer mac instructions.  I ran into this because I was trying to do
exactly that and while running some tests on sh-sim.

The attached patch uses the bfd_mach field to distinguish between SH1 and
not-SH1 in the simulation of the mac.w instruction, in a similar way as it's
already been done for some SH2A instructions.


OK to commit & push?

Best regards,
Oleg Endo