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From: Hui Zhu <teawater@gmail.com>
Date: Fri, 17 Jul 2009 08:50:00 -0000
Message-ID: <daef60380907170146u7c1dd6d4yb4e5e99a9add4634@mail.gmail.com>
Subject: Re: [RFA/RFC Prec] Add Linux AMD64 process record support second  	version, (instruction set support) 1/3
To: Michael Snyder <msnyder@vmware.com>
Cc: gdb-patches ml <gdb-patches@sourceware.org>
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On Mon, Jul 13, 2009 at 08:34, Michael Snyder<msnyder@vmware.com> wrote:
> Hui Zhu wrote:
>>
>> Because AMD64 instruction set is the extend of I386 instruction set.
>> So I update the function i386_process_record to make it support AMD64
>> instruction set. =A0some of other software do something like it.
>> 2009-07-07 =A0Hui Zhu =A0<teawater@gmail.com>
>>
>> =A0 =A0 =A0 =A0Add AMD64 process record instruction set support.
>>
>> =A0 =A0 =A0 =A0* i386-tdep.h (gdbarch_tdep): Add record_regmap for regis=
ters
>> =A0 =A0 =A0 =A0because the AMD64's registers order in GDB is not same wi=
th
>> =A0 =A0 =A0 =A0I386 instructions.
>> =A0 =A0 =A0 =A0Add i386_syscall_record to be the syscall function handle
>> =A0 =A0 =A0 =A0interface.
>> =A0 =A0 =A0 =A0(record_i386_regnum): Number for record_regmap.
>> =A0 =A0 =A0 =A0* i386-tdep.c (OT_QUAD): For 64 bits.
>> =A0 =A0 =A0 =A0(i386_record_s): Add rex_x, rex_b, rip_offset and
>> =A0 =A0 =A0 =A0popl_esp_hack for AMD64 instruction set. And regmap for
>> =A0 =A0 =A0 =A0record_regmap.
>> =A0 =A0 =A0 =A0(i386_record_lea_modrm_addr): Support AMD64 instruction s=
et
>> =A0 =A0 =A0 =A064 bits lea.
>> =A0 =A0 =A0 =A0(i386_record_lea_modrm): Ditto.
>> =A0 =A0 =A0 =A0(i386_record_push): New function. =A0Record the execution=
 log
>> =A0 =A0 =A0 =A0of push.
>> =A0 =A0 =A0 =A0(I386_RECORD_ARCH_LIST_ADD_REG): New macro to record the
>> =A0 =A0 =A0 =A0register.
>> =A0 =A0 =A0 =A0(i386_process_record): Support AMD64 instruction set.
>> =A0 =A0 =A0 =A0amd64-tdep.c (amd64_record_regmap): For record_regmap.
>> =A0 =A0 =A0 =A0(amd64_init_abi): Set amd64_record_regmap to record_regma=
p.
>
> OK, this is kind of preliminary -- mostly concerned with
> whitespace / formatting. =A0I'll try to do more later.
>
>
>> @@ -2859,7 +2868,7 @@ i386_record_lea_modrm_addr (struct i386_
>> =A0 =A0 =A0 =A0 =A0if ((base & 7) =3D=3D 5)
>> =A0 =A0 =A0 =A0 =A0 =A0{
>> =A0 =A0 =A0 =A0 =A0 =A0 =A0base =3D 0xff;
>> - =A0 =A0 =A0 =A0 =A0 =A0 if (target_read_memory (irp->addr, (gdb_byte *=
) addr, 4))
>> + =A0 =A0 =A0 =A0 =A0 =A0 if (target_read_memory (irp->addr, (gdb_byte *=
)&tmpi32, 4))
>
> Space after a cast, please. =A0There are many instances of this,
> I won't try to note them all.
>
>> @@ -2884,10 +2896,10 @@ i386_record_lea_modrm_addr (struct i386_
>> =A0 =A0 =A0 =A0 =A0 =A0 =A0return -1;
>> =A0 =A0 =A0 =A0 =A0 =A0}
>> =A0 =A0 =A0 =A0 =A0irp->addr++;
>> - =A0 =A0 =A0 =A0 *addr =3D (int8_t) tmpu8;
>> + =A0 =A0 =A0 =A0 *addr =3D (int8_t)tmpu8;
>
> Space after cast
>
>> @@ -2949,10 +2974,10 @@ i386_record_lea_modrm_addr (struct i386_
>> =A0 =A0 =A0 =A0 =A0 =A0 =A0return -1;
>> =A0 =A0 =A0 =A0 =A0 =A0}
>> =A0 =A0 =A0 =A0 =A0irp->addr++;
>> - =A0 =A0 =A0 =A0 *addr =3D (int8_t) tmpu8;
>> + =A0 =A0 =A0 =A0 *addr =3D (int8_t)tmpu8;
>> =A0 =A0 =A0 =A0 =A0break;
>> =A0 =A0 =A0 =A0case 2:
>> - =A0 =A0 =A0 =A0 if (target_read_memory (irp->addr, (gdb_byte *) & tmpu=
16, 2))
>> + =A0 =A0 =A0 =A0 if (target_read_memory (irp->addr, (gdb_byte *) & tmpi=
16, 2))
>
> No space after '&' operator. =A0In general, we use a space
> both before and after a binary operator (such as 'plus'),
> but no space after a unary operator such as '&', '*' or '-'.
>
>> + =A0 =A0 =A0 =A0 if (ir.aflag =3D=3D 2)
>> + =A0 =A0 =A0 =A0 =A0 {
>> + =A0 =A0 =A0 =A0 =A0 =A0 =A0if (target_read_memory
>> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 (ir.addr, (gdb_byte *)&addr, 8))
>
> Please try to avoid doing this (putting the left-paren of a
> function call on the next line). =A0Occasionally when a line gets
> really long I tend to overlook it, but in this case it would
> be really easy to divide the line up like this:
>
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 if (target_read_memory (ir.addr,
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 (gdb_byte *) &addr, 8))
>
>> + =A0 =A0 =A0 =A0 =A0if (ir.mod =3D=3D3)
>
> Space after =3D=3D
>
>> + =A0 =A0 =A0 =A0 =A0switch (ir.dflag)
>> + =A0 =A0 =A0 =A0 =A0 =A0{
>> + =A0 =A0 =A0 =A0 =A0 =A0case 0:
>> + =A0 =A0 =A0 =A0 =A0 =A0 =A0tmpu64 +=3D ((int16_t)tmpulongest >> 4)<< 4;
>
> Space before <<, space after cast.
>
>> + =A0 =A0 =A0 =A0 =A0 =A0 =A0break;
>> + =A0 =A0 =A0 =A0 =A0 =A0case 1:
>> + =A0 =A0 =A0 =A0 =A0 =A0 =A0tmpu64 +=3D ((int32_t)tmpulongest >> 5)<< 5;
>
> Ditto
>
>> + =A0 =A0 =A0 =A0 =A0 =A0 =A0break;
>> + =A0 =A0 =A0 =A0 =A0 =A0case 2:
>> + =A0 =A0 =A0 =A0 =A0 =A0 =A0tmpu64 +=3D ((int64_t)tmpulongest >> 6)<< 6;
>
> Ditto
>
>> + =A0/* The map for registers because the AMD64's registers order in GDB=
 is
>> not
>> + =A0 =A0 same with I386 instructions. =A0*/
>
> "same as". =A0And could you shorten the first line please?
>
>
>

Thanks Michael,

I updated all the AMD64 patches.  Please help me review it.

Thanks,
Hui

2009-07-17  Hui Zhu  <teawater@gmail.com>

	Add AMD64 process record instruction set support.

	* i386-tdep.h (gdbarch_tdep): Add record_regmap for registers
	because the AMD64's registers order in GDB is not same with
	I386 instructions.
	Add i386_syscall_record to be the syscall function handle
	interface.
	(record_i386_regnum): Number for record_regmap.
	* i386-tdep.c (OT_QUAD): For 64 bits.
	(i386_record_s): Add rex_x, rex_b, rip_offset and
	popl_esp_hack for AMD64 instruction set. And regmap for
	record_regmap.
	(i386_record_lea_modrm_addr): Support AMD64 instruction set
	64 bits lea.
	(i386_record_lea_modrm): Ditto.
	(i386_record_push): New function.  Record the execution log
	of push.
	(I386_RECORD_ARCH_LIST_ADD_REG): New macro to record the
	register.
	(i386_process_record): Support AMD64 instruction set.
	amd64-tdep.c (amd64_record_regmap): For record_regmap.
	(amd64_init_abi): Set amd64_record_regmap to record_regmap.

---
 amd64-tdep.c |   12
 i386-tdep.c  | 1437 +++++++++++++++++++++++++++++++-----------------------=
-----
 i386-tdep.h  |   35 +
 3 files changed, 825 insertions(+), 659 deletions(-)

--- a/amd64-tdep.c
+++ b/amd64-tdep.c
@@ -1989,6 +1989,16 @@ amd64_get_longjmp_target (struct frame_i
   return 1;
 }

+static const int amd64_record_regmap[] =3D
+{
+  AMD64_RAX_REGNUM, AMD64_RCX_REGNUM, AMD64_RDX_REGNUM, AMD64_RBX_REGNUM,
+  AMD64_RSP_REGNUM, AMD64_RBP_REGNUM, AMD64_RSI_REGNUM, AMD64_RDI_REGNUM,
+  AMD64_R8_REGNUM, AMD64_R9_REGNUM, AMD64_R10_REGNUM, AMD64_R11_REGNUM,
+  AMD64_R12_REGNUM, AMD64_R13_REGNUM, AMD64_R14_REGNUM, AMD64_R15_REGNUM,
+  AMD64_RIP_REGNUM, AMD64_EFLAGS_REGNUM, AMD64_CS_REGNUM, AMD64_SS_REGNUM,
+  AMD64_DS_REGNUM, AMD64_ES_REGNUM, AMD64_FS_REGNUM, AMD64_GS_REGNUM
+};
+
 void
 amd64_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch)
 {
@@ -2051,6 +2061,8 @@ amd64_init_abi (struct gdbarch_info info
   set_gdbarch_num_pseudo_regs (gdbarch, 0);
   tdep->mm0_regnum =3D -1;

+  tdep->record_regmap =3D amd64_record_regmap;
+
   set_gdbarch_dummy_id (gdbarch, amd64_dummy_id);

   frame_unwind_append_unwinder (gdbarch, &amd64_sigtramp_frame_unwind);
--- a/i386-tdep.c
+++ b/i386-tdep.c
@@ -2847,6 +2847,7 @@ enum
   OT_BYTE =3D 0,
   OT_WORD,
   OT_LONG,
+  OT_QUAD,
 };

 /* i386 arith/logic operations */
@@ -2864,6 +2865,7 @@ enum

 struct i386_record_s
 {
+  struct gdbarch *gdbarch;
   struct regcache *regcache;
   CORE_ADDR addr;
   int aflag;
@@ -2872,6 +2874,11 @@ struct i386_record_s
   uint8_t modrm;
   uint8_t mod, reg, rm;
   int ot;
+  uint8_t rex_x;
+  uint8_t rex_b;
+  int rip_offset;
+  int popl_esp_hack;
+  const int *regmap;
 };

 /* Parse "modrm" part in current memory address that irp->addr point to
@@ -2880,7 +2887,7 @@ struct i386_record_s
 static int
 i386_record_modrm (struct i386_record_s *irp)
 {
-  struct gdbarch *gdbarch =3D get_regcache_arch (irp->regcache);
+  struct gdbarch *gdbarch =3D irp->gdbarch;

   if (target_read_memory (irp->addr, &irp->modrm, 1))
     {
@@ -2903,12 +2910,13 @@ i386_record_modrm (struct i386_record_s
    Return -1 if something wrong. */

 static int
-i386_record_lea_modrm_addr (struct i386_record_s *irp, uint32_t * addr)
+i386_record_lea_modrm_addr (struct i386_record_s *irp, uint64_t *addr)
 {
-  struct gdbarch *gdbarch =3D get_regcache_arch (irp->regcache);
+  struct gdbarch *gdbarch =3D irp->gdbarch;
   uint8_t tmpu8;
-  uint16_t tmpu16;
-  uint32_t tmpu32;
+  int16_t tmpi16;
+  int32_t tmpi32;
+  ULONGEST tmpulongest;

   *addr =3D 0;
   if (irp->aflag)
@@ -2932,9 +2940,10 @@ i386_record_lea_modrm_addr (struct i386_
 	    }
 	  irp->addr++;
 	  scale =3D (tmpu8 >> 6) & 3;
-	  index =3D ((tmpu8 >> 3) & 7);
+	  index =3D ((tmpu8 >> 3) & 7) | irp->rex_x;
 	  base =3D (tmpu8 & 7);
 	}
+      base |=3D irp->rex_b;

       switch (irp->mod)
 	{
@@ -2942,7 +2951,7 @@ i386_record_lea_modrm_addr (struct i386_
 	  if ((base & 7) =3D=3D 5)
 	    {
 	      base =3D 0xff;
-	      if (target_read_memory (irp->addr, (gdb_byte *) addr, 4))
+	      if (target_read_memory (irp->addr, (gdb_byte *) &tmpi32, 4))
 		{
 		  if (record_debug)
 		    printf_unfiltered (_("Process record: error reading "
@@ -2951,6 +2960,9 @@ i386_record_lea_modrm_addr (struct i386_
 		  return -1;
 		}
 	      irp->addr +=3D 4;
+	      *addr =3D tmpi32;
+	      if (irp->regmap[X86_RECORD_R8_REGNUM] && !havesib)
+		*addr +=3D irp->addr + irp->rip_offset;
 	    }
 	  else
 	    {
@@ -2970,7 +2982,7 @@ i386_record_lea_modrm_addr (struct i386_
 	  *addr =3D (int8_t) tmpu8;
 	  break;
 	case 2:
-	  if (target_read_memory (irp->addr, (gdb_byte *) addr, 4))
+	  if (target_read_memory (irp->addr, (gdb_byte *) &tmpi32, 4))
 	    {
 	      if (record_debug)
 		printf_unfiltered (_("Process record: error reading memory "
@@ -2978,21 +2990,34 @@ i386_record_lea_modrm_addr (struct i386_
 				   paddress (gdbarch, irp->addr));
 	      return -1;
 	    }
+	  *addr =3D tmpi32;
 	  irp->addr +=3D 4;
 	  break;
 	}

+      tmpulongest =3D 0;
       if (base !=3D 0xff)
-	{
-	  regcache_raw_read (irp->regcache, base, (gdb_byte *) & tmpu32);
-	  *addr +=3D tmpu32;
+        {
+	  if (base =3D=3D 4 && irp->popl_esp_hack)
+	    *addr +=3D irp->popl_esp_hack;
+	  regcache_raw_read_unsigned (irp->regcache, irp->regmap[base],
+                                      &tmpulongest);
 	}
+      if (irp->aflag =3D=3D 2)
+        {
+	  *addr +=3D tmpulongest;
+        }
+      else
+        *addr =3D (uint32_t) (tmpulongest + *addr);

-      /* XXX: index =3D=3D 4 is always invalid */
       if (havesib && (index !=3D 4 || scale !=3D 0))
 	{
-	  regcache_raw_read (irp->regcache, index, (gdb_byte *) & tmpu32);
-	  *addr +=3D tmpu32 << scale;
+	  regcache_raw_read_unsigned (irp->regcache, irp->regmap[index],
+                                      &tmpulongest);
+	  if (irp->aflag =3D=3D 2)
+	    *addr +=3D tmpulongest << scale;
+	  else
+	    *addr =3D (uint32_t) (*addr + (tmpulongest << scale));
 	}
     }
   else
@@ -3004,7 +3029,7 @@ i386_record_lea_modrm_addr (struct i386_
 	  if (irp->rm =3D=3D 6)
 	    {
 	      if (target_read_memory
-		  (irp->addr, (gdb_byte *) & tmpu16, 2))
+		  (irp->addr, (gdb_byte *) &tmpi16, 2))
 		{
 		  if (record_debug)
 		    printf_unfiltered (_("Process record: error reading "
@@ -3013,7 +3038,7 @@ i386_record_lea_modrm_addr (struct i386_
 		  return -1;
 		}
 	      irp->addr +=3D 2;
-	      *addr =3D (int16_t) tmpu16;
+	      *addr =3D tmpi16;
 	      irp->rm =3D 0;
 	      goto no_rm;
 	    }
@@ -3035,7 +3060,7 @@ i386_record_lea_modrm_addr (struct i386_
 	  *addr =3D (int8_t) tmpu8;
 	  break;
 	case 2:
-	  if (target_read_memory (irp->addr, (gdb_byte *) & tmpu16, 2))
+	  if (target_read_memory (irp->addr, (gdb_byte *) &tmpi16, 2))
 	    {
 	      if (record_debug)
 		printf_unfiltered (_("Process record: error reading memory "
@@ -3044,63 +3069,75 @@ i386_record_lea_modrm_addr (struct i386_
 	      return -1;
 	    }
 	  irp->addr +=3D 2;
-	  *addr =3D (int16_t) tmpu16;
+	  *addr =3D tmpi16;
 	  break;
 	}

       switch (irp->rm)
 	{
 	case 0:
-	  regcache_raw_read (irp->regcache, I386_EBX_REGNUM,
-			     (gdb_byte *) & tmpu32);
-	  *addr +=3D tmpu32;
-	  regcache_raw_read (irp->regcache, I386_ESI_REGNUM,
-			     (gdb_byte *) & tmpu32);
-	  *addr +=3D tmpu32;
+	  regcache_raw_read_unsigned (irp->regcache,
+				      irp->regmap[X86_RECORD_REBX_REGNUM],
+                                      &tmpulongest);
+	  *addr =3D (uint32_t) (*addr + tmpulongest);
+	  regcache_raw_read_unsigned (irp->regcache,
+				      irp->regmap[X86_RECORD_RESI_REGNUM],
+                                      &tmpulongest);
+	  *addr =3D (uint32_t) (*addr + tmpulongest);
 	  break;
 	case 1:
-	  regcache_raw_read (irp->regcache, I386_EBX_REGNUM,
-			     (gdb_byte *) & tmpu32);
-	  *addr +=3D tmpu32;
-	  regcache_raw_read (irp->regcache, I386_EDI_REGNUM,
-			     (gdb_byte *) & tmpu32);
-	  *addr +=3D tmpu32;
+	  regcache_raw_read_unsigned (irp->regcache,
+				      irp->regmap[X86_RECORD_REBX_REGNUM],
+                                      &tmpulongest);
+	  *addr =3D (uint32_t) (*addr + tmpulongest);
+	  regcache_raw_read_unsigned (irp->regcache,
+				      irp->regmap[X86_RECORD_REDI_REGNUM],
+                                      &tmpulongest);
+	  *addr =3D (uint32_t) (*addr + tmpulongest);
 	  break;
 	case 2:
-	  regcache_raw_read (irp->regcache, I386_EBP_REGNUM,
-			     (gdb_byte *) & tmpu32);
-	  *addr +=3D tmpu32;
-	  regcache_raw_read (irp->regcache, I386_ESI_REGNUM,
-			     (gdb_byte *) & tmpu32);
-	  *addr +=3D tmpu32;
+	  regcache_raw_read_unsigned (irp->regcache,
+				      irp->regmap[X86_RECORD_REBP_REGNUM],
+                                      &tmpulongest);
+	  *addr =3D (uint32_t) (*addr + tmpulongest);
+	  regcache_raw_read_unsigned (irp->regcache,
+				      irp->regmap[X86_RECORD_RESI_REGNUM],
+                                      &tmpulongest);
+	  *addr =3D (uint32_t) (*addr + tmpulongest);
 	  break;
 	case 3:
-	  regcache_raw_read (irp->regcache, I386_EBP_REGNUM,
-			     (gdb_byte *) & tmpu32);
-	  *addr +=3D tmpu32;
-	  regcache_raw_read (irp->regcache, I386_EDI_REGNUM,
-			     (gdb_byte *) & tmpu32);
-	  *addr +=3D tmpu32;
+	  regcache_raw_read_unsigned (irp->regcache,
+				      irp->regmap[X86_RECORD_REBP_REGNUM],
+                                      &tmpulongest);
+	  *addr =3D (uint32_t) (*addr + tmpulongest);
+	  regcache_raw_read_unsigned (irp->regcache,
+				      irp->regmap[X86_RECORD_REDI_REGNUM],
+                                      &tmpulongest);
+	  *addr =3D (uint32_t) (*addr + tmpulongest);
 	  break;
 	case 4:
-	  regcache_raw_read (irp->regcache, I386_ESI_REGNUM,
-			     (gdb_byte *) & tmpu32);
-	  *addr +=3D tmpu32;
+	  regcache_raw_read_unsigned (irp->regcache,
+				      irp->regmap[X86_RECORD_RESI_REGNUM],
+                                      &tmpulongest);
+	  *addr =3D (uint32_t) (*addr + tmpulongest);
 	  break;
 	case 5:
-	  regcache_raw_read (irp->regcache, I386_EDI_REGNUM,
-			     (gdb_byte *) & tmpu32);
-	  *addr +=3D tmpu32;
+	  regcache_raw_read_unsigned (irp->regcache,
+				      irp->regmap[X86_RECORD_REDI_REGNUM],
+                                      &tmpulongest);
+	  *addr =3D (uint32_t) (*addr + tmpulongest);
 	  break;
 	case 6:
-	  regcache_raw_read (irp->regcache, I386_EBP_REGNUM,
-			     (gdb_byte *) & tmpu32);
-	  *addr +=3D tmpu32;
+	  regcache_raw_read_unsigned (irp->regcache,
+				      irp->regmap[X86_RECORD_REBP_REGNUM],
+                                      &tmpulongest);
+	  *addr =3D (uint32_t) (*addr + tmpulongest);
 	  break;
 	case 7:
-	  regcache_raw_read (irp->regcache, I386_EBX_REGNUM,
-			     (gdb_byte *) & tmpu32);
-	  *addr +=3D tmpu32;
+	  regcache_raw_read_unsigned (irp->regcache,
+				      irp->regmap[X86_RECORD_REBX_REGNUM],
+                                      &tmpulongest);
+	  *addr =3D (uint32_t) (*addr + tmpulongest);
 	  break;
 	}
       *addr &=3D 0xffff;
@@ -3117,10 +3154,10 @@ no_rm:
 static int
 i386_record_lea_modrm (struct i386_record_s *irp)
 {
-  struct gdbarch *gdbarch =3D get_regcache_arch (irp->regcache);
-  uint32_t addr;
+  struct gdbarch *gdbarch =3D irp->gdbarch;
+  uint64_t addr;

-  if (irp->override)
+  if (irp->override >=3D 0)
     {
       if (record_debug)
 	printf_unfiltered (_("Process record ignores the memory change "
@@ -3139,10 +3176,36 @@ i386_record_lea_modrm (struct i386_recor
   return 0;
 }

+/* Record the push operation to "record_arch_list".
+   Return -1 if something wrong. */
+
+static int
+i386_record_push (struct i386_record_s *irp, int size)
+{
+  ULONGEST tmpulongest;
+
+  if (record_arch_list_add_reg (irp->regcache,
+				irp->regmap[X86_RECORD_RESP_REGNUM]))
+    return -1;
+  regcache_raw_read_unsigned (irp->regcache,
+			      irp->regmap[X86_RECORD_RESP_REGNUM],
+			      &tmpulongest);
+  if (record_arch_list_add_mem ((CORE_ADDR) tmpulongest - size, size))
+    return -1;
+
+  return 0;
+}
+
 /* Parse the current instruction and record the values of the registers and
    memory that will be changed in current instruction to "record_arch_list=
".
    Return -1 if something wrong. */

+#define I386_RECORD_ARCH_LIST_ADD_REG(regnum) \
+    do { \
+         if (record_arch_list_add_reg (ir.regcache, ir.regmap[(regnum)])) \
+         return -1; \
+       } while (0)
+
 int
 i386_process_record (struct gdbarch *gdbarch, struct regcache *regcache,
 		     CORE_ADDR addr)
@@ -3151,14 +3214,21 @@ i386_process_record (struct gdbarch *gdb
   uint8_t tmpu8;
   uint16_t tmpu16;
   uint32_t tmpu32;
+  ULONGEST tmpulongest;
   uint32_t opcode;
   struct i386_record_s ir;
+  int rex =3D 0;
+  uint8_t rex_w =3D -1;
+  uint8_t rex_r =3D 0;

   memset (&ir, 0, sizeof (struct i386_record_s));
   ir.regcache =3D regcache;
   ir.addr =3D addr;
   ir.aflag =3D 1;
   ir.dflag =3D 1;
+  ir.override =3D -1;
+  ir.regmap =3D gdbarch_tdep (gdbarch)->record_regmap;
+  ir.gdbarch =3D gdbarch;

   if (record_debug > 1)
     fprintf_unfiltered (gdb_stdlog, "Process record: i386_process_record "
@@ -3189,22 +3259,22 @@ i386_process_record (struct gdbarch *gdb
 	  prefixes |=3D PREFIX_LOCK;
 	  break;
 	case 0x2e:
-	  ir.override =3D I386_CS_REGNUM;
+	  ir.override =3D X86_RECORD_CS_REGNUM;
 	  break;
 	case 0x36:
-	  ir.override =3D I386_SS_REGNUM;
+	  ir.override =3D X86_RECORD_SS_REGNUM;
 	  break;
 	case 0x3e:
-	  ir.override =3D I386_DS_REGNUM;
+	  ir.override =3D X86_RECORD_DS_REGNUM;
 	  break;
 	case 0x26:
-	  ir.override =3D I386_ES_REGNUM;
+	  ir.override =3D X86_RECORD_ES_REGNUM;
 	  break;
 	case 0x64:
-	  ir.override =3D I386_FS_REGNUM;
+	  ir.override =3D X86_RECORD_FS_REGNUM;
 	  break;
 	case 0x65:
-	  ir.override =3D I386_GS_REGNUM;
+	  ir.override =3D X86_RECORD_GS_REGNUM;
 	  break;
 	case 0x66:
 	  prefixes |=3D PREFIX_DATA;
@@ -3212,16 +3282,51 @@ i386_process_record (struct gdbarch *gdb
 	case 0x67:
 	  prefixes |=3D PREFIX_ADDR;
 	  break;
+        case 0x40:
+        case 0x41:
+        case 0x42:
+        case 0x43:
+        case 0x44:
+        case 0x45:
+        case 0x46:
+        case 0x47:
+        case 0x48:
+        case 0x49:
+        case 0x4a:
+        case 0x4b:
+        case 0x4c:
+        case 0x4d:
+        case 0x4e:
+        case 0x4f:
+          if (ir.regmap[X86_RECORD_R8_REGNUM])
+            {
+               /* REX */
+               rex =3D 1;
+               rex_w =3D (tmpu8 >> 3) & 1;
+               rex_r =3D (tmpu8 & 0x4) << 1;
+               ir.rex_x =3D (tmpu8 & 0x2) << 2;
+               ir.rex_b =3D (tmpu8 & 0x1) << 3;
+            }
+          break;
 	default:
 	  goto out_prefixes;
 	  break;
 	}
     }
 out_prefixes:
-  if (prefixes & PREFIX_DATA)
-    ir.dflag ^=3D 1;
+  if (ir.regmap[X86_RECORD_R8_REGNUM] && rex_w =3D=3D 1)
+    {
+      ir.dflag =3D 2;
+    }
+  else
+    {
+      if (prefixes & PREFIX_DATA)
+        ir.dflag ^=3D 1;
+    }
   if (prefixes & PREFIX_ADDR)
     ir.aflag ^=3D 1;
+  else if (ir.regmap[X86_RECORD_R8_REGNUM])
+    ir.aflag =3D 2;

   /* now check op code */
   opcode =3D (uint32_t) tmpu8;
@@ -3311,30 +3416,28 @@ reswitch:
 		}
 	      else
 		{
-		  if (ir.ot =3D=3D OT_BYTE)
+                  ir.rm |=3D ir.rex_b;
+		  if (ir.ot =3D=3D OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
 		    ir.rm &=3D 0x3;
-		  if (record_arch_list_add_reg (ir.regcache, ir.rm))
-		    return -1;
+		  I386_RECORD_ARCH_LIST_ADD_REG (ir.rm);
 		}
 	      break;
 	      /* OP Gv, Ev */
 	    case 1:
 	      if (i386_record_modrm (&ir))
 		return -1;
-	      if (ir.ot =3D=3D OT_BYTE)
+              ir.reg |=3D rex_r;
+	      if (ir.ot =3D=3D OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
 		ir.reg &=3D 0x3;
-	      if (record_arch_list_add_reg (ir.regcache, ir.reg))
-		return -1;
+	      I386_RECORD_ARCH_LIST_ADD_REG (ir.reg);
 	      break;
 	      /* OP A, Iv */
 	    case 2:
-	      if (record_arch_list_add_reg (ir.regcache, I386_EAX_REGNUM))
-		return -1;
+	      I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
 	      break;
 	    }
 	}
-      if (record_arch_list_add_reg (ir.regcache, I386_EFLAGS_REGNUM))
-	return -1;
+      I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
       break;

       /* GRP1 */
@@ -3354,17 +3457,17 @@ reswitch:

 	  if (ir.mod !=3D 3)
 	    {
+              if (opcode =3D=3D 0x83)
+                ir.rip_offset =3D 1;
+              else
+                ir.rip_offset =3D (ir.ot > OT_LONG) ? 4 : (1 << ir.ot);
 	      if (i386_record_lea_modrm (&ir))
 		return -1;
 	    }
 	  else
-	    {
-	      if (record_arch_list_add_reg (ir.regcache, ir.rm))
-		return -1;
-	    }
+	    I386_RECORD_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b);
 	}
-      if (record_arch_list_add_reg (ir.regcache, I386_EFLAGS_REGNUM))
-	return -1;
+      I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
       break;

       /* inv */
@@ -3385,10 +3488,8 @@ reswitch:
     case 0x4d:
     case 0x4e:
     case 0x4f:
-      if (record_arch_list_add_reg (ir.regcache, opcode & 7))
-	return -1;
-      if (record_arch_list_add_reg (ir.regcache, I386_EFLAGS_REGNUM))
-	return -1;
+      I386_RECORD_ARCH_LIST_ADD_REG (opcode & 7);
+      I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
       break;

       /* GRP3 */
@@ -3401,28 +3502,17 @@ reswitch:
       if (i386_record_modrm (&ir))
 	return -1;

+      if (ir.mod !=3D 3 && ir.reg =3D=3D 0)
+        ir.rip_offset =3D (ir.ot > OT_LONG) ? 4 : (1 << ir.ot);
+
       switch (ir.reg)
 	{
 	  /* test */
 	case 0:
-	  if (record_arch_list_add_reg (ir.regcache, I386_EFLAGS_REGNUM))
-	    return -1;
+	  I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
 	  break;
 	  /* not */
 	case 2:
-	  if (ir.mod !=3D 3)
-	    {
-	      if (i386_record_lea_modrm (&ir))
-		return -1;
-	    }
-	  else
-	    {
-	      if (ir.ot =3D=3D OT_BYTE)
-		ir.rm &=3D 0x3;
-	      if (record_arch_list_add_reg (ir.regcache, ir.rm))
-		return -1;
-	    }
-	  break;
 	  /* neg */
 	case 3:
 	  if (ir.mod !=3D 3)
@@ -3432,13 +3522,14 @@ reswitch:
 	    }
 	  else
 	    {
-	      if (ir.ot =3D=3D OT_BYTE)
+              ir.rm |=3D ir.rex_b;
+	      if (ir.ot =3D=3D OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
 		ir.rm &=3D 0x3;
-	      if (record_arch_list_add_reg (ir.regcache, ir.rm))
-		return -1;
+	      I386_RECORD_ARCH_LIST_ADD_REG (ir.rm);
 	    }
-	  if (record_arch_list_add_reg (ir.regcache, I386_EFLAGS_REGNUM))
-	    return -1;
+	  /* neg */
+	  if (ir.reg =3D=3D 3)
+	    I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
 	  break;
 	  /* mul */
 	case 4:
@@ -3448,15 +3539,10 @@ reswitch:
 	case 6:
 	  /* idiv */
 	case 7:
-	  if (record_arch_list_add_reg (ir.regcache, I386_EAX_REGNUM))
-	    return -1;
+	  I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
 	  if (ir.ot !=3D OT_BYTE)
-	    {
-	      if (record_arch_list_add_reg (ir.regcache, I386_EDX_REGNUM))
-		return -1;
-	    }
-	  if (record_arch_list_add_reg (ir.regcache, I386_EFLAGS_REGNUM))
-	    return -1;
+	    I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM);
+	  I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
 	  break;
 	default:
 	  ir.addr -=3D 2;
@@ -3470,10 +3556,6 @@ reswitch:
     case 0xfe:
       /* GRP5 */
     case 0xff:
-      if ((opcode & 1) =3D=3D 0)
-	ir.ot =3D OT_BYTE;
-      else
-	ir.ot =3D ir.dflag + OT_WORD;
       if (i386_record_modrm (&ir))
 	return -1;
       if (ir.reg >=3D 2 && opcode =3D=3D 0xfe)
@@ -3482,13 +3564,16 @@ reswitch:
 	  opcode =3D opcode << 8 | ir.modrm;
 	  goto no_support;
 	}
-
       switch (ir.reg)
 	{
 	  /* inc */
 	case 0:
 	  /* dec */
 	case 1:
+          if ((opcode & 1) =3D=3D 0)
+	    ir.ot =3D OT_BYTE;
+          else
+	    ir.ot =3D ir.dflag + OT_WORD;
 	  if (ir.mod !=3D 3)
 	    {
 	      if (i386_record_lea_modrm (&ir))
@@ -3496,42 +3581,40 @@ reswitch:
 	    }
 	  else
 	    {
-	      if (ir.ot =3D=3D OT_BYTE)
+	      ir.rm |=3D ir.rex_b;
+	      if (ir.ot =3D=3D OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
 		ir.rm &=3D 0x3;
-	      if (record_arch_list_add_reg (ir.regcache, ir.rm))
-		return -1;
+	      I386_RECORD_ARCH_LIST_ADD_REG (ir.rm);
 	    }
-	  if (record_arch_list_add_reg (ir.regcache, I386_EFLAGS_REGNUM))
-	    return -1;
+	  I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
 	  break;
 	  /* call */
 	case 2:
-	  /* push */
-	case 6:
-	  if (record_arch_list_add_reg (ir.regcache, I386_ESP_REGNUM))
-	    return -1;
-	  regcache_raw_read (ir.regcache, I386_ESP_REGNUM,
-			     (gdb_byte *) & tmpu32);
-	  if (record_arch_list_add_mem
-	      ((CORE_ADDR) tmpu32 - (1 << (ir.dflag + 1)), (1 << (ir.dflag + 1))))
+          if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag)
+            ir.dflag =3D 2;
+	  if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
 	    return -1;
+	  I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
 	  break;
 	  /* lcall */
 	case 3:
-	  if (record_arch_list_add_reg (ir.regcache, I386_ESP_REGNUM))
-	    return -1;
-	  if (record_arch_list_add_reg (ir.regcache, I386_CS_REGNUM))
-	    return -1;
-	  regcache_raw_read (ir.regcache, I386_ESP_REGNUM,
-			     (gdb_byte *) & tmpu32);
-	  if (record_arch_list_add_mem
-	      ((CORE_ADDR) tmpu32 - (1 << (ir.dflag + 2)), (1 << (ir.dflag + 2))))
+	  I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM);
+	  if (i386_record_push (&ir, 1 << (ir.dflag + 2)))
 	    return -1;
+	  I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
 	  break;
 	  /* jmp */
 	case 4:
 	  /* ljmp */
 	case 5:
+	  I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
+	  break;
+	  /* push */
+	case 6:
+          if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag)
+            ir.dflag =3D 2;
+	  if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
+	    return -1;
 	  break;
 	default:
 	  ir.addr -=3D 2;
@@ -3546,22 +3629,18 @@ reswitch:
     case 0x85:
     case 0xa8:
     case 0xa9:
-      if (record_arch_list_add_reg (ir.regcache, I386_EFLAGS_REGNUM))
-	return -1;
+      I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
       break;

       /* CWDE/CBW */
     case 0x98:
-      if (record_arch_list_add_reg (ir.regcache, I386_EAX_REGNUM))
-	return -1;
+      I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
       break;

       /* CDQ/CWD */
     case 0x99:
-      if (record_arch_list_add_reg (ir.regcache, I386_EAX_REGNUM))
-	return -1;
-      if (record_arch_list_add_reg (ir.regcache, I386_EDX_REGNUM))
-	return -1;
+      I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
+      I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM);
       break;

       /* imul */
@@ -3571,12 +3650,15 @@ reswitch:
       ir.ot =3D ir.dflag + OT_WORD;
       if (i386_record_modrm (&ir))
 	return -1;
-      if (ir.ot =3D=3D OT_BYTE)
+      if (opcode =3D=3D 0x69)
+        ir.rip_offset =3D (ir.ot > OT_LONG) ? 4 : (1 << ir.ot);
+      else if (opcode =3D=3D 0x6b)
+        ir.rip_offset =3D 1;
+      ir.reg |=3D rex_r;
+      if (ir.ot =3D=3D OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
 	ir.reg &=3D 0x3;
-      if (record_arch_list_add_reg (ir.regcache, ir.reg))
-	return -1;
-      if (record_arch_list_add_reg (ir.regcache, I386_EFLAGS_REGNUM))
-	return -1;
+      I386_RECORD_ARCH_LIST_ADD_REG (ir.reg);
+      I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
       break;

       /* xadd */
@@ -3588,28 +3670,25 @@ reswitch:
 	ir.ot =3D ir.dflag + OT_WORD;
       if (i386_record_modrm (&ir))
 	return -1;
+      ir.reg |=3D rex_r;
       if (ir.mod =3D=3D 3)
 	{
-	  if (ir.ot =3D=3D OT_BYTE)
+	  if (ir.ot =3D=3D OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
 	    ir.reg &=3D 0x3;
-	  if (record_arch_list_add_reg (ir.regcache, ir.reg))
-	    return -1;
-	  if (ir.ot =3D=3D OT_BYTE)
+	  I386_RECORD_ARCH_LIST_ADD_REG (ir.reg);
+	  if (ir.ot =3D=3D OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
 	    ir.rm &=3D 0x3;
-	  if (record_arch_list_add_reg (ir.regcache, ir.rm))
-	    return -1;
+	  I386_RECORD_ARCH_LIST_ADD_REG (ir.rm);
 	}
       else
 	{
 	  if (i386_record_lea_modrm (&ir))
 	    return -1;
-	  if (ir.ot =3D=3D OT_BYTE)
+	  if (ir.ot =3D=3D OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
 	    ir.reg &=3D 0x3;
-	  if (record_arch_list_add_reg (ir.regcache, ir.reg))
-	    return -1;
+	  I386_RECORD_ARCH_LIST_ADD_REG (ir.reg);
 	}
-      if (record_arch_list_add_reg (ir.regcache, I386_EFLAGS_REGNUM))
-	return -1;
+      I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
       break;

       /* cmpxchg */
@@ -3623,22 +3702,19 @@ reswitch:
 	return -1;
       if (ir.mod =3D=3D 3)
 	{
-	  if (record_arch_list_add_reg (ir.regcache, I386_EAX_REGNUM))
-	    return -1;
-	  if (ir.ot =3D=3D OT_BYTE)
+          ir.reg |=3D rex_r;
+	  I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
+	  if (ir.ot =3D=3D OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
 	    ir.reg &=3D 0x3;
-	  if (record_arch_list_add_reg (ir.regcache, ir.reg))
-	    return -1;
+	  I386_RECORD_ARCH_LIST_ADD_REG (ir.reg);
 	}
       else
 	{
-	  if (record_arch_list_add_reg (ir.regcache, I386_EAX_REGNUM))
-	    return -1;
+	  I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
 	  if (i386_record_lea_modrm (&ir))
 	    return -1;
 	}
-      if (record_arch_list_add_reg (ir.regcache, I386_EFLAGS_REGNUM))
-	return -1;
+      I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
       break;

       /* cmpxchg8b */
@@ -3651,14 +3727,11 @@ reswitch:
 	  opcode =3D opcode << 8 | ir.modrm;
 	  goto no_support;
 	}
-      if (record_arch_list_add_reg (ir.regcache, I386_EAX_REGNUM))
-	return -1;
-      if (record_arch_list_add_reg (ir.regcache, I386_EDX_REGNUM))
-	return -1;
+      I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
+      I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM);
       if (i386_record_lea_modrm (&ir))
 	return -1;
-      if (record_arch_list_add_reg (ir.regcache, I386_EFLAGS_REGNUM))
-	return -1;
+      I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
       break;

       /* push */
@@ -3672,6 +3745,12 @@ reswitch:
     case 0x57:
     case 0x68:
     case 0x6a:
+      if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag)
+        ir.dflag =3D 2;
+      if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
+	return -1;
+      break;
+
       /* push es */
     case 0x06:
       /* push cs */
@@ -3680,16 +3759,36 @@ reswitch:
     case 0x16:
       /* push ds */
     case 0x1e:
+      if (ir.regmap[X86_RECORD_R8_REGNUM])
+        {
+	  ir.addr -=3D 1;
+	  goto no_support;
+	}
+      if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
+	return -1;
+      break;
+
       /* push fs */
     case 0x0fa0:
       /* push gs */
     case 0x0fa8:
-      if (record_arch_list_add_reg (ir.regcache, I386_ESP_REGNUM))
+      if (ir.regmap[X86_RECORD_R8_REGNUM])
+        {
+	  ir.addr -=3D 2;
+	  goto no_support;
+	}
+      if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
 	return -1;
-      regcache_raw_read (ir.regcache, I386_ESP_REGNUM,
-			 (gdb_byte *) & tmpu32);
-      if (record_arch_list_add_mem
-	  ((CORE_ADDR) tmpu32 - (1 << (ir.dflag + 1)), (1 << (ir.dflag + 1))))
+      break;
+
+      /* pusha */
+    case 0x60:
+      if (ir.regmap[X86_RECORD_R8_REGNUM])
+        {
+	  ir.addr -=3D 1;
+	  goto no_support;
+	}
+      if (i386_record_push (&ir, 1 << (ir.dflag + 4)))
 	return -1;
       break;

@@ -3702,113 +3801,103 @@ reswitch:
     case 0x5d:
     case 0x5e:
     case 0x5f:
-      ir.ot =3D ir.dflag + OT_WORD;
-      if (record_arch_list_add_reg (ir.regcache, I386_ESP_REGNUM))
-	return -1;
-      if (ir.ot =3D=3D OT_BYTE)
-	opcode &=3D 0x3;
-      if (record_arch_list_add_reg (ir.regcache, opcode & 0x7))
-	return -1;
-      break;
-
-      /* pusha */
-    case 0x60:
-      if (record_arch_list_add_reg (ir.regcache, I386_ESP_REGNUM))
-	return -1;
-      regcache_raw_read (ir.regcache, I386_ESP_REGNUM,
-			 (gdb_byte *) & tmpu32);
-      if (record_arch_list_add_mem
-	  ((CORE_ADDR) tmpu32 - (1 << (ir.dflag + 4)), (1 << (ir.dflag + 4))))
-	return -1;
+      I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
+      I386_RECORD_ARCH_LIST_ADD_REG ((opcode & 0x7) | ir.rex_b);
       break;

       /* popa */
     case 0x61:
-      for (tmpu8 =3D I386_EAX_REGNUM; tmpu8 <=3D I386_EDI_REGNUM; tmpu8++)
-	{
-	  if (record_arch_list_add_reg (ir.regcache, tmpu8))
-	    return -1;
+      if (ir.regmap[X86_RECORD_R8_REGNUM])
+        {
+	  ir.addr -=3D 1;
+	  goto no_support;
 	}
+      for (tmpu8 =3D X86_RECORD_REAX_REGNUM; tmpu8 <=3D X86_RECORD_REDI_RE=
GNUM;
+	   tmpu8++)
+	I386_RECORD_ARCH_LIST_ADD_REG (tmpu8);
       break;

       /* pop */
     case 0x8f:
-      ir.ot =3D ir.dflag + OT_WORD;
+      if (ir.regmap[X86_RECORD_R8_REGNUM])
+	ir.ot =3D ir.dflag ? OT_QUAD : OT_WORD;
+      else
+        ir.ot =3D ir.dflag + OT_WORD;
       if (i386_record_modrm (&ir))
 	return -1;
       if (ir.mod =3D=3D 3)
-	{
-	  if (record_arch_list_add_reg (ir.regcache, ir.rm))
-	    return -1;
-	}
+	I386_RECORD_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b);
       else
 	{
 	  if (i386_record_lea_modrm (&ir))
 	    return -1;
 	}
-      if (record_arch_list_add_reg (ir.regcache, I386_ESP_REGNUM))
-	return -1;
+      I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
       break;

       /* enter */
     case 0xc8:
-      if (record_arch_list_add_reg (ir.regcache, I386_ESP_REGNUM))
-	return -1;
-      if (record_arch_list_add_reg (ir.regcache, I386_EBP_REGNUM))
-	return -1;
-      regcache_raw_read (ir.regcache, I386_ESP_REGNUM,
-			 (gdb_byte *) & tmpu32);
-      if (record_arch_list_add_mem
-	  ((CORE_ADDR) tmpu32 - (1 << (ir.dflag + 1)), (1 << (ir.dflag + 1))))
+      I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM);
+      if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag)
+        ir.dflag =3D 2;
+      if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
 	return -1;
       break;

       /* leave */
     case 0xc9:
-      if (record_arch_list_add_reg (ir.regcache, I386_ESP_REGNUM))
-	return -1;
-      if (record_arch_list_add_reg (ir.regcache, I386_EBP_REGNUM))
-	return -1;
+      I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
+      I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM);
       break;

       /* pop es */
     case 0x07:
-      if (record_arch_list_add_reg (ir.regcache, I386_ESP_REGNUM))
-	return -1;
-      if (record_arch_list_add_reg (ir.regcache, I386_ES_REGNUM))
-	return -1;
+      if (ir.regmap[X86_RECORD_R8_REGNUM])
+        {
+	  ir.addr -=3D 1;
+	  goto no_support;
+	}
+      I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
+      I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_ES_REGNUM);
+      I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
       break;

       /* pop ss */
     case 0x17:
-      if (record_arch_list_add_reg (ir.regcache, I386_ESP_REGNUM))
-	return -1;
-      if (record_arch_list_add_reg (ir.regcache, I386_SS_REGNUM))
-	return -1;
+      if (ir.regmap[X86_RECORD_R8_REGNUM])
+        {
+	  ir.addr -=3D 1;
+	  goto no_support;
+	}
+      I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
+      I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_SS_REGNUM);
+      I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
       break;

       /* pop ds */
     case 0x1f:
-      if (record_arch_list_add_reg (ir.regcache, I386_ESP_REGNUM))
-	return -1;
-      if (record_arch_list_add_reg (ir.regcache, I386_DS_REGNUM))
-	return -1;
+      if (ir.regmap[X86_RECORD_R8_REGNUM])
+        {
+	  ir.addr -=3D 1;
+	  goto no_support;
+	}
+      I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
+      I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_DS_REGNUM);
+      I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
       break;

       /* pop fs */
     case 0x0fa1:
-      if (record_arch_list_add_reg (ir.regcache, I386_ESP_REGNUM))
-	return -1;
-      if (record_arch_list_add_reg (ir.regcache, I386_FS_REGNUM))
-	return -1;
+      I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
+      I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_FS_REGNUM);
+      I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
       break;

       /* pop gs */
     case 0x0fa9:
-      if (record_arch_list_add_reg (ir.regcache, I386_ESP_REGNUM))
-	return -1;
-      if (record_arch_list_add_reg (ir.regcache, I386_GS_REGNUM))
-	return -1;
+      I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
+      I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_GS_REGNUM);
+      I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
       break;

       /* mov */
@@ -3826,19 +3915,21 @@ reswitch:

       if (ir.mod !=3D 3)
 	{
+          if (opcode =3D=3D 0xc6 || opcode =3D=3D 0xc7)
+	    ir.rip_offset =3D (ir.ot > OT_LONG) ? 4 : (1 << ir.ot);
 	  if (i386_record_lea_modrm (&ir))
 	    return -1;
 	}
       else
 	{
-	  if (ir.ot =3D=3D OT_BYTE)
+          if (opcode =3D=3D 0xc6 || opcode =3D=3D 0xc7)
+	    ir.rm |=3D ir.rex_b;
+	  if (ir.ot =3D=3D OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
 	    ir.rm &=3D 0x3;
-	  if (record_arch_list_add_reg (ir.regcache, ir.rm))
-	    return -1;
+	  I386_RECORD_ARCH_LIST_ADD_REG (ir.rm);
 	}
-      if (record_arch_list_add_reg (ir.regcache, I386_EFLAGS_REGNUM))
-	return -1;
       break;
+
       /* mov */
     case 0x8a:
     case 0x8b:
@@ -3846,40 +3937,55 @@ reswitch:
 	ir.ot =3D OT_BYTE;
       else
 	ir.ot =3D ir.dflag + OT_WORD;
-
       if (i386_record_modrm (&ir))
 	return -1;
-
-      if (ir.ot =3D=3D OT_BYTE)
+      ir.reg |=3D rex_r;
+      if (ir.ot =3D=3D OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
 	ir.reg &=3D 0x3;
-      if (record_arch_list_add_reg (ir.regcache, ir.reg))
-	return -1;
+      I386_RECORD_ARCH_LIST_ADD_REG (ir.reg);
+      break;

-      if (record_arch_list_add_reg (ir.regcache, I386_EFLAGS_REGNUM))
+      /* mov seg */
+    case 0x8c:
+      if (i386_record_modrm (&ir))
 	return -1;
+      if (ir.reg > 5)
+	{
+	  ir.addr -=3D 2;
+	  opcode =3D opcode << 8 | ir.modrm;
+	  goto no_support;
+	}
+
+      if (ir.mod =3D=3D 3)
+	I386_RECORD_ARCH_LIST_ADD_REG (ir.rm);
+      else
+	{
+	  ir.ot =3D OT_WORD;
+	  if (i386_record_lea_modrm (&ir))
+	    return -1;
+	}
       break;

       /* mov seg */
     case 0x8e:
       if (i386_record_modrm (&ir))
 	return -1;
-
       switch (ir.reg)
 	{
 	case 0:
-	  tmpu8 =3D I386_ES_REGNUM;
+	  tmpu8 =3D X86_RECORD_ES_REGNUM;
 	  break;
 	case 2:
-	  tmpu8 =3D I386_SS_REGNUM;
+	  tmpu8 =3D X86_RECORD_SS_REGNUM;
 	  break;
 	case 3:
-	  tmpu8 =3D I386_DS_REGNUM;
+	  tmpu8 =3D X86_RECORD_DS_REGNUM;
 	  break;
 	case 4:
-	  tmpu8 =3D I386_FS_REGNUM;
+	  tmpu8 =3D X86_RECORD_FS_REGNUM;
 	  break;
 	case 5:
-	  tmpu8 =3D I386_GS_REGNUM;
+	  tmpu8 =3D X86_RECORD_GS_REGNUM;
 	  break;
 	default:
 	  ir.addr -=3D 2;
@@ -3887,38 +3993,8 @@ reswitch:
 	  goto no_support;
 	  break;
 	}
-      if (record_arch_list_add_reg (ir.regcache, tmpu8))
-	return -1;
-
-      if (record_arch_list_add_reg (ir.regcache, I386_EFLAGS_REGNUM))
-	return -1;
-      break;
-
-      /* mov seg */
-    case 0x8c:
-      if (i386_record_modrm (&ir))
-	return -1;
-      if (ir.reg > 5)
-	{
-	  ir.addr -=3D 2;
-	  opcode =3D opcode << 8 | ir.modrm;
-	  goto no_support;
-	}
-
-      if (ir.mod =3D=3D 3)
-	{
-	  if (record_arch_list_add_reg (ir.regcache, ir.rm))
-	    return -1;
-	}
-      else
-	{
-	  ir.ot =3D OT_WORD;
-	  if (i386_record_lea_modrm (&ir))
-	    return -1;
-	}
-
-      if (record_arch_list_add_reg (ir.regcache, I386_EFLAGS_REGNUM))
-	return -1;
+      I386_RECORD_ARCH_LIST_ADD_REG (tmpu8);
+      I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
       break;

       /* movzbS */
@@ -3931,8 +4007,7 @@ reswitch:
     case 0x0fbf:
       if (i386_record_modrm (&ir))
 	return -1;
-      if (record_arch_list_add_reg (ir.regcache, ir.reg))
-	return -1;
+      I386_RECORD_ARCH_LIST_ADD_REG (ir.reg | rex_r);
       break;

       /* lea */
@@ -3945,12 +4020,11 @@ reswitch:
 	  opcode =3D opcode << 8 | ir.modrm;
 	  goto no_support;
 	}
-
       ir.ot =3D ir.dflag;
-      if (ir.ot =3D=3D OT_BYTE)
+      ir.reg |=3D rex_r;
+      if (ir.ot =3D=3D OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
 	ir.reg &=3D 0x3;
-      if (record_arch_list_add_reg (ir.regcache, ir.reg))
-	return -1;
+      I386_RECORD_ARCH_LIST_ADD_REG (ir.reg);
       break;

       /* mov EAX */
@@ -3958,62 +4032,68 @@ reswitch:
     case 0xa1:
       /* xlat */
     case 0xd7:
-      if (record_arch_list_add_reg (ir.regcache, I386_EAX_REGNUM))
-	return -1;
+      I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
       break;

       /* mov EAX */
     case 0xa2:
     case 0xa3:
-      {
-	uint32_t addr;
-
-	if (ir.override)
-	  {
-	    if (record_debug)
-	      printf_unfiltered (_("Process record ignores the memory change "
-				   "of instruction at address %s because "
-				   "it can't get the value of the segment "
-				   "register.\n"),
-				 paddress (gdbarch, ir.addr));
-	  }
-	else
-	  {
-	    if ((opcode & 1) =3D=3D 0)
-	      ir.ot =3D OT_BYTE;
-	    else
-	      ir.ot =3D ir.dflag + OT_WORD;
-	    if (ir.aflag)
-	      {
-		if (target_read_memory
-		    (ir.addr, (gdb_byte *) & addr, 4))
-		  {
-		    if (record_debug)
-		      printf_unfiltered (_("Process record: error reading "
-					   "memory at addr %s len =3D 4.\n"),
-					 paddress (gdbarch, ir.addr));
-		    return -1;
-		  }
-		ir.addr +=3D 4;
-	      }
-	    else
-	      {
-		if (target_read_memory
-		    (ir.addr, (gdb_byte *) & tmpu16, 4))
-		  {
-		    if (record_debug)
-		      printf_unfiltered (_("Process record: error reading "
-					   "memory at addr %s len =3D 4.\n"),
-					 paddress (gdbarch, ir.addr));
-		    return -1;
-		  }
-		ir.addr +=3D 2;
-		addr =3D tmpu16;
-	      }
-	    if (record_arch_list_add_mem (addr, 1 << ir.ot))
-	      return -1;
-	  }
-      }
+      if (ir.override >=3D 0)
+        {
+	  if (record_debug)
+	    printf_unfiltered (_("Process record ignores the memory change "
+				 "of instruction at address 0x%s because "
+				 "it can't get the value of the segment "
+				 "register.\n"),
+			       paddress (gdbarch, ir.addr));
+	}
+      else
+	{
+          if ((opcode & 1) =3D=3D 0)
+	    ir.ot =3D OT_BYTE;
+	  else
+	    ir.ot =3D ir.dflag + OT_WORD;
+	  if (ir.aflag =3D=3D 2)
+	    {
+              if (target_read_memory (ir.addr, (gdb_byte *) &addr, 8))
+		{
+	          if (record_debug)
+		    printf_unfiltered (_("Process record: error reading "
+	                    		 "memory at addr 0x%s len =3D 8.\n"),
+				       paddress (gdbarch, ir.addr));
+		  return -1;
+		}
+	      ir.addr +=3D 8;
+	    }
+          else if (ir.aflag)
+	    {
+              if (target_read_memory (ir.addr, (gdb_byte *) &tmpu32, 4))
+		{
+	          if (record_debug)
+		    printf_unfiltered (_("Process record: error reading "
+	                    		 "memory at addr 0x%s len =3D 4.\n"),
+				       paddress (gdbarch, ir.addr));
+		  return -1;
+		}
+	      ir.addr +=3D 4;
+              addr =3D tmpu32;
+	    }
+          else
+	    {
+              if (target_read_memory (ir.addr, (gdb_byte *) &tmpu16, 2))
+		{
+	          if (record_debug)
+		    printf_unfiltered (_("Process record: error reading "
+	                    		 "memory at addr 0x%s len =3D 2.\n"),
+				       paddress (gdbarch, ir.addr));
+		  return -1;
+		}
+	      ir.addr +=3D 2;
+              addr =3D tmpu16;
+	    }
+	  if (record_arch_list_add_mem (addr, 1 << ir.ot))
+	    return -1;
+        }
       break;

       /* mov R, Ib */
@@ -4025,8 +4105,9 @@ reswitch:
     case 0xb5:
     case 0xb6:
     case 0xb7:
-      if (record_arch_list_add_reg (ir.regcache, (opcode & 0x7) & 0x3))
-	return -1;
+      I386_RECORD_ARCH_LIST_ADD_REG ((ir.regmap[X86_RECORD_R8_REGNUM]) ?
+				     ((opcode & 0x7) | ir.rex_b) :
+				     ((opcode & 0x7) & 0x3));
       break;

       /* mov R, Iv */
@@ -4038,8 +4119,7 @@ reswitch:
     case 0xbd:
     case 0xbe:
     case 0xbf:
-      if (record_arch_list_add_reg (ir.regcache, opcode & 0x7))
-	return -1;
+      I386_RECORD_ARCH_LIST_ADD_REG ((opcode & 0x7) | ir.rex_b);
       break;

       /* xchg R, EAX */
@@ -4050,10 +4130,8 @@ reswitch:
     case 0x95:
     case 0x96:
     case 0x97:
-      if (record_arch_list_add_reg (ir.regcache, I386_EAX_REGNUM))
-	return -1;
-      if (record_arch_list_add_reg (ir.regcache, opcode & 0x7))
-	return -1;
+      I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
+      I386_RECORD_ARCH_LIST_ADD_REG (opcode & 0x7);
       break;

       /* xchg Ev, Gv */
@@ -4063,33 +4141,35 @@ reswitch:
 	ir.ot =3D OT_BYTE;
       else
 	ir.ot =3D ir.dflag + OT_WORD;
-
       if (i386_record_modrm (&ir))
 	return -1;
-
       if (ir.mod =3D=3D 3)
 	{
-	  if (ir.ot =3D=3D OT_BYTE)
+	  ir.rm !=3D ir.rex_b;
+	  if (ir.ot =3D=3D OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
 	    ir.rm &=3D 0x3;
-	  if (record_arch_list_add_reg (ir.regcache, ir.rm))
-	    return -1;
+	  I386_RECORD_ARCH_LIST_ADD_REG (ir.rm);
 	}
       else
 	{
 	  if (i386_record_lea_modrm (&ir))
 	    return -1;
 	}
-
-      if (ir.ot =3D=3D OT_BYTE)
+      ir.reg |=3D rex_r;
+      if (ir.ot =3D=3D OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
 	ir.reg &=3D 0x3;
-      if (record_arch_list_add_reg (ir.regcache, ir.reg))
-	return -1;
+      I386_RECORD_ARCH_LIST_ADD_REG (ir.reg);
       break;

       /* les Gv */
     case 0xc4:
       /* lds Gv */
     case 0xc5:
+      if (ir.regmap[X86_RECORD_R8_REGNUM])
+        {
+	  ir.addr -=3D 1;
+	  goto no_support;
+	}
       /* lss Gv */
     case 0x0fb2:
       /* lfs Gv */
@@ -4107,35 +4187,32 @@ reswitch:
 	  opcode =3D opcode << 8 | ir.modrm;
 	  goto no_support;
 	}
-
       switch (opcode)
 	{
 	  /* les Gv */
 	case 0xc4:
-	  tmpu8 =3D I386_ES_REGNUM;
+	  tmpu8 =3D X86_RECORD_ES_REGNUM;
 	  break;
 	  /* lds Gv */
 	case 0xc5:
-	  tmpu8 =3D I386_DS_REGNUM;
+	  tmpu8 =3D X86_RECORD_DS_REGNUM;
 	  break;
 	  /* lss Gv */
 	case 0x0fb2:
-	  tmpu8 =3D I386_SS_REGNUM;
+	  tmpu8 =3D X86_RECORD_SS_REGNUM;
 	  break;
 	  /* lfs Gv */
 	case 0x0fb4:
-	  tmpu8 =3D I386_FS_REGNUM;
+	  tmpu8 =3D X86_RECORD_FS_REGNUM;
 	  break;
 	  /* lgs Gv */
 	case 0x0fb5:
-	  tmpu8 =3D I386_GS_REGNUM;
+	  tmpu8 =3D X86_RECORD_GS_REGNUM;
 	  break;
 	}
-      if (record_arch_list_add_reg (ir.regcache, tmpu8))
-	return -1;
-
-      if (record_arch_list_add_reg (ir.regcache, ir.reg))
-	return -1;
+      I386_RECORD_ARCH_LIST_ADD_REG (tmpu8);
+      I386_RECORD_ARCH_LIST_ADD_REG (ir.reg | rex_r);
+      I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
       break;

       /* shifts */
@@ -4149,10 +4226,8 @@ reswitch:
 	ir.ot =3D OT_BYTE;
       else
 	ir.ot =3D ir.dflag + OT_WORD;
-
       if (i386_record_modrm (&ir))
 	return -1;
-
       if (ir.mod !=3D 3 && (opcode =3D=3D 0xd2 || opcode =3D=3D 0xd3))
 	{
 	  if (i386_record_lea_modrm (&ir))
@@ -4160,14 +4235,12 @@ reswitch:
 	}
       else
 	{
-	  if (ir.ot =3D=3D OT_BYTE)
+	  ir.rm |=3D ir.rex_b;
+	  if (ir.ot =3D=3D OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
 	    ir.rm &=3D 0x3;
-	  if (record_arch_list_add_reg (ir.regcache, ir.rm))
-	    return -1;
+	  I386_RECORD_ARCH_LIST_ADD_REG (ir.rm);
 	}
-
-      if (record_arch_list_add_reg (ir.regcache, I386_EFLAGS_REGNUM))
-	return -1;
+      I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
       break;

     case 0x0fa4:
@@ -4204,9 +4277,9 @@ reswitch:
       if (ir.mod !=3D 3)
 	{
 	  /* memory */
-	  uint32_t addr;
+	  uint64_t tmpu64;

-	  if (i386_record_lea_modrm_addr (&ir, &addr))
+	  if (i386_record_lea_modrm_addr (&ir, &tmpu64))
 	    return -1;
 	  switch (ir.reg)
 	    {
@@ -4266,16 +4339,16 @@ reswitch:
 		  switch (ir.reg >> 4)
 		    {
 		    case 0:
-		      if (record_arch_list_add_mem (addr, 4))
+		      if (record_arch_list_add_mem (tmpu64, 4))
 			return -1;
 		      break;
 		    case 2:
-		      if (record_arch_list_add_mem (addr, 8))
+		      if (record_arch_list_add_mem (tmpu64, 8))
 			return -1;
 		      break;
 		    case 3:
 		    default:
-		      if (record_arch_list_add_mem (addr, 2))
+		      if (record_arch_list_add_mem (tmpu64, 2))
 			return -1;
 		      break;
 		    }
@@ -4285,16 +4358,16 @@ reswitch:
 		    {
 		    case 0:
 		    case 1:
-		      if (record_arch_list_add_mem (addr, 4))
+		      if (record_arch_list_add_mem (tmpu64, 4))
 			return -1;
 		      break;
 		    case 2:
-		      if (record_arch_list_add_mem (addr, 8))
+		      if (record_arch_list_add_mem (tmpu64, 8))
 			return -1;
 		      break;
 		    case 3:
 		    default:
-		      if (record_arch_list_add_mem (addr, 2))
+		      if (record_arch_list_add_mem (tmpu64, 2))
 			return -1;
 		      break;
 		    }
@@ -4311,43 +4384,43 @@ reswitch:
 	    case 0x0e:
 	      if (ir.dflag)
 		{
-		  if (record_arch_list_add_mem (addr, 28))
+		  if (record_arch_list_add_mem (tmpu64, 28))
 		    return -1;
 		}
 	      else
 		{
-		  if (record_arch_list_add_mem (addr, 14))
+		  if (record_arch_list_add_mem (tmpu64, 14))
 		    return -1;
 		}
 	      break;
 	    case 0x0f:
 	    case 0x2f:
-	      if (record_arch_list_add_mem (addr, 2))
+	      if (record_arch_list_add_mem (tmpu64, 2))
 		return -1;
 	      break;
 	    case 0x1f:
 	    case 0x3e:
-	      if (record_arch_list_add_mem (addr, 10))
+	      if (record_arch_list_add_mem (tmpu64, 10))
 		return -1;
 	      break;
 	    case 0x2e:
 	      if (ir.dflag)
 		{
-		  if (record_arch_list_add_mem (addr, 28))
+		  if (record_arch_list_add_mem (tmpu64, 28))
 		    return -1;
-		  addr +=3D 28;
+		  tmpu64 +=3D 28;
 		}
 	      else
 		{
-		  if (record_arch_list_add_mem (addr, 14))
+		  if (record_arch_list_add_mem (tmpu64, 14))
 		    return -1;
-		  addr +=3D 14;
+		  tmpu64 +=3D 14;
 		}
-	      if (record_arch_list_add_mem (addr, 80))
+	      if (record_arch_list_add_mem (tmpu64, 80))
 		return -1;
 	      break;
 	    case 0x3f:
-	      if (record_arch_list_add_mem (addr, 8))
+	      if (record_arch_list_add_mem (tmpu64, 8))
 		return -1;
 	      break;
 	    default:
@@ -4369,123 +4442,88 @@ reswitch:
       /* insS */
     case 0x6c:
     case 0x6d:
-      {
-	uint32_t addr;
-
-	if ((opcode & 1) =3D=3D 0)
-	  ir.ot =3D OT_BYTE;
-	else
-	  ir.ot =3D ir.dflag + OT_WORD;
-	if (opcode =3D=3D 0xa4 || opcode =3D=3D 0xa5)
-	  {
-	    if (record_arch_list_add_reg (ir.regcache, I386_ESI_REGNUM))
-	      return -1;
-	  }
-	if (record_arch_list_add_reg (ir.regcache, I386_EDI_REGNUM))
-	  return -1;
-
-	regcache_raw_read (ir.regcache, I386_EDI_REGNUM,
-			   (gdb_byte *) & addr);
-	if (!ir.aflag)
-	  {
-	    addr &=3D 0xffff;
-	    /* addr +=3D ((uint32_t)read_register (I386_ES_REGNUM)) << 4; */
-	    if (record_debug)
-	      printf_unfiltered (_("Process record ignores the memory change "
-				   "of instruction at address %s because "
-				   "it can't get the value of the segment "
-				   "register.\n"),
-				 paddress (gdbarch, ir.addr));
-	  }
-
-	if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ))
-	  {
-	    uint32_t count;
-
-	    regcache_raw_read (ir.regcache, I386_ECX_REGNUM,
-			       (gdb_byte *) & count);
-	    if (!ir.aflag)
-	      count &=3D 0xffff;
-
-	    regcache_raw_read (ir.regcache, I386_EFLAGS_REGNUM,
-			       (gdb_byte *) & tmpu32);
-	    if ((tmpu32 >> 10) & 0x1)
-	      addr -=3D (count - 1) * (1 << ir.ot);
-
-	    if (ir.aflag)
-	      {
-		if (record_arch_list_add_mem (addr, count * (1 << ir.ot)))
-		  return -1;
-	      }
+      if ((opcode & 1) =3D=3D 0)
+	ir.ot =3D OT_BYTE;
+      else
+	ir.ot =3D ir.dflag + OT_WORD;
+      regcache_raw_read_unsigned (ir.regcache,
+                                  ir.regmap[X86_RECORD_REDI_REGNUM],
+                                  &tmpulongest);
+      if (!ir.aflag)
+        {
+          tmpulongest &=3D 0xffff;
+          /* addr +=3D ((uint32_t) read_register (I386_ES_REGNUM)) << 4; */
+          if (record_debug)
+            printf_unfiltered (_("Process record ignores the memory change=
 "
+                                 "of instruction at address 0x%s because "
+                                 "it can't get the value of the segment "
+                                 "register.\n"),
+                               paddress (gdbarch, ir.addr));
+        }
+      if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ))
+        {
+          ULONGEST count, eflags;
+          regcache_raw_read_unsigned (ir.regcache,
+                                      ir.regmap[X86_RECORD_REDI_REGNUM],
+                                      &count);
+          if (!ir.aflag)
+            count &=3D 0xffff;
+          regcache_raw_read_unsigned (ir.regcache,
+                                      ir.regmap[X86_RECORD_EFLAGS_REGNUM],
+                                      &eflags);
+          if ((eflags >> 10) & 0x1)
+            tmpulongest -=3D (count - 1) * (1 << ir.ot);
+          if (record_arch_list_add_mem (tmpulongest, count * (1 << ir.ot)))
+            return -1;
+          I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM);
+        }
+      else
+        {
+          if (record_arch_list_add_mem (tmpulongest, 1 << ir.ot))
+            return -1;
+        }
+      if (opcode =3D=3D 0xa4 || opcode =3D=3D 0xa5)
+        I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM);
+      I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM);
+      I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
+      break;

-	    if (record_arch_list_add_reg (ir.regcache, I386_ECX_REGNUM))
-	      return -1;
-	  }
-	else
-	  {
-	    if (ir.aflag)
-	      {
-		if (record_arch_list_add_mem (addr, 1 << ir.ot))
-		  return -1;
-	      }
-	  }
-      }
+      /* cmpsS */
+    case 0xa6:
+    case 0xa7:
+      I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM);
+      I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM);
+      if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ))
+        I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM);
+      I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
       break;

       /* lodsS */
     case 0xac:
     case 0xad:
-      if (record_arch_list_add_reg (ir.regcache, I386_EAX_REGNUM))
-	return -1;
-      if (record_arch_list_add_reg (ir.regcache, I386_ESI_REGNUM))
-	return -1;
-      if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ))
-	{
-	  if (record_arch_list_add_reg (ir.regcache, I386_ECX_REGNUM))
-	    return -1;
-	}
-      break;
-
-      /* outsS */
-    case 0x6e:
-    case 0x6f:
-      if (record_arch_list_add_reg (ir.regcache, I386_ESI_REGNUM))
-	return -1;
+      I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
+      I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM);
       if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ))
-	{
-	  if (record_arch_list_add_reg (ir.regcache, I386_ECX_REGNUM))
-	    return -1;
-	}
+        I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM);
+      I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
       break;

       /* scasS */
     case 0xae:
     case 0xaf:
-      if (record_arch_list_add_reg (ir.regcache, I386_EDI_REGNUM))
-	return -1;
+      I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM);
       if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ))
-	{
-	  if (record_arch_list_add_reg (ir.regcache, I386_ECX_REGNUM))
-	    return -1;
-	}
-      if (record_arch_list_add_reg (ir.regcache, I386_EFLAGS_REGNUM))
-	return -1;
+        I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM);
+      I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
       break;

-      /* cmpsS */
-    case 0xa6:
-    case 0xa7:
-      if (record_arch_list_add_reg (ir.regcache, I386_EDI_REGNUM))
-	return -1;
-      if (record_arch_list_add_reg (ir.regcache, I386_ESI_REGNUM))
-	return -1;
+      /* outsS */
+    case 0x6e:
+    case 0x6f:
+      I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM);
       if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ))
-	{
-	  if (record_arch_list_add_reg (ir.regcache, I386_ECX_REGNUM))
-	    return -1;
-	}
-      if (record_arch_list_add_reg (ir.regcache, I386_EFLAGS_REGNUM))
-	return -1;
+        I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM);
+      I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
       break;

       /* port I/O */
@@ -4493,8 +4531,8 @@ reswitch:
     case 0xe5:
     case 0xec:
     case 0xed:
-      if (record_arch_list_add_reg (ir.regcache, I386_EAX_REGNUM))
-	return -1;
+      I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
+      I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
       break;

     case 0xe6:
@@ -4508,48 +4546,32 @@ reswitch:
     case 0xc2:
       /* ret */
     case 0xc3:
+      I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
+      I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
+      break;
+
       /* lret im */
     case 0xca:
       /* lret */
     case 0xcb:
-      if (record_arch_list_add_reg (ir.regcache, I386_ESP_REGNUM))
-	return -1;
-      if (record_arch_list_add_reg (ir.regcache, I386_CS_REGNUM))
-	return -1;
-      break;
-
       /* iret */
     case 0xcf:
-      if (record_arch_list_add_reg (ir.regcache, I386_ESP_REGNUM))
-	return -1;
-      if (record_arch_list_add_reg (ir.regcache, I386_CS_REGNUM))
-	return -1;
-      if (record_arch_list_add_reg (ir.regcache, I386_EFLAGS_REGNUM))
-	return -1;
+      I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM);
+      I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
+      I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
       break;

       /* call im */
     case 0xe8:
-      if (record_arch_list_add_reg (ir.regcache, I386_ESP_REGNUM))
-	return -1;
-      regcache_raw_read (ir.regcache, I386_ESP_REGNUM,
-			 (gdb_byte *) & tmpu32);
-      if (record_arch_list_add_mem
-	  ((CORE_ADDR) tmpu32 - (1 << (ir.dflag + 1)), (1 << (ir.dflag + 1))))
-	return -1;
+      if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
+        return -1;
       break;

       /* lcall im */
     case 0x9a:
-      if (record_arch_list_add_reg (ir.regcache, I386_CS_REGNUM))
-	return -1;
-      if (record_arch_list_add_reg (ir.regcache, I386_ESP_REGNUM))
-	return -1;
-      regcache_raw_read (ir.regcache, I386_ESP_REGNUM,
-			 (gdb_byte *) & tmpu32);
-      if (record_arch_list_add_mem
-	  ((CORE_ADDR) tmpu32 - (1 << (ir.dflag + 2)), (1 << (ir.dflag + 2))))
-	return -1;
+      I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM);
+      if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
+        return -1;
       break;

       /* jmp im */
@@ -4611,14 +4633,13 @@ reswitch:
     case 0x0f9d:
     case 0x0f9e:
     case 0x0f9f:
+      I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
       ir.ot =3D OT_BYTE;
       if (i386_record_modrm (&ir))
 	return -1;
       if (ir.mod =3D=3D 3)
-	{
-	  if (record_arch_list_add_reg (ir.regcache, ir.rm & 0x3))
-	    return -1;
-	}
+        I386_RECORD_ARCH_LIST_ADD_REG (ir.rex_b ? (ir.rm | ir.rex_b):
+                                                  (ir.rm & 0x3));
       else
 	{
 	  if (i386_record_lea_modrm (&ir))
@@ -4645,34 +4666,33 @@ reswitch:
     case 0x0f4f:
       if (i386_record_modrm (&ir))
 	return -1;
+      ir.reg |=3D rex_r;
       if (ir.dflag =3D=3D OT_BYTE)
 	ir.reg &=3D 0x3;
-      if (record_arch_list_add_reg (ir.regcache, ir.reg & 0x3))
-	return -1;
+      I386_RECORD_ARCH_LIST_ADD_REG (ir.reg);
       break;

       /* flags */
       /* pushf */
     case 0x9c:
-      if (record_arch_list_add_reg (ir.regcache, I386_ESP_REGNUM))
-	return -1;
-      regcache_raw_read (ir.regcache, I386_ESP_REGNUM,
-			 (gdb_byte *) & tmpu32);
-      if (record_arch_list_add_mem
-	  ((CORE_ADDR) tmpu32 - (1 << (ir.dflag + 1)), (1 << (ir.dflag + 1))))
-	return -1;
+      I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
+      if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
+        return -1;
       break;

       /* popf */
     case 0x9d:
-      if (record_arch_list_add_reg (ir.regcache, I386_ESP_REGNUM))
-	return -1;
-      if (record_arch_list_add_reg (ir.regcache, I386_EFLAGS_REGNUM))
-	return -1;
+      I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
+      I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
       break;

       /* sahf */
     case 0x9e:
+      if (ir.regmap[X86_RECORD_R8_REGNUM])
+        {
+          ir.addr -=3D 1;
+          goto no_support;
+        }
       /* cmc */
     case 0xf5:
       /* clc */
@@ -4683,66 +4703,95 @@ reswitch:
     case 0xfc:
       /* std */
     case 0xfd:
-      if (record_arch_list_add_reg (ir.regcache, I386_EFLAGS_REGNUM))
-	return -1;
+      I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
       break;

       /* lahf */
     case 0x9f:
-      if (record_arch_list_add_reg (ir.regcache, I386_EAX_REGNUM))
-	return -1;
+      if (ir.regmap[X86_RECORD_R8_REGNUM])
+        {
+          ir.addr -=3D 1;
+          goto no_support;
+        }
+      I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
+      I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
       break;

       /* bit operations */
       /* bt/bts/btr/btc Gv, im */
     case 0x0fba:
-      /* bts */
-    case 0x0fab:
-      /* btr */
-    case 0x0fb3:
-      /* btc */
-    case 0x0fbb:
       ir.ot =3D ir.dflag + OT_WORD;
       if (i386_record_modrm (&ir))
 	return -1;
       if (ir.reg < 4)
 	{
-	  ir.addr -=3D 3;
+	  ir.addr -=3D 2;
 	  opcode =3D opcode << 8 | ir.modrm;
 	  goto no_support;
 	}
-      ir.reg -=3D 4;
-      if (ir.reg !=3D 0)
+      if (ir.reg !=3D 4)
 	{
-	  if (ir.mod !=3D 3)
-	    {
-	      if (i386_record_lea_modrm (&ir))
-		return -1;
-	    }
+          if (ir.mod =3D=3D 3)
+            I386_RECORD_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b);
 	  else
 	    {
-	      if (record_arch_list_add_reg (ir.regcache, ir.rm))
+	      if (i386_record_lea_modrm (&ir))
 		return -1;
 	    }
 	}
-      if (record_arch_list_add_reg (ir.regcache, I386_EFLAGS_REGNUM))
-	return -1;
+      I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
       break;

       /* bt Gv, Ev */
     case 0x0fa3:
-      if (record_arch_list_add_reg (ir.regcache, I386_EFLAGS_REGNUM))
-	return -1;
+      I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
+      break;
+
+      /* bts */
+    case 0x0fab:
+      /* btr */
+    case 0x0fb3:
+      /* btc */
+    case 0x0fbb:
+      ir.ot =3D ir.dflag + OT_WORD;
+      if (i386_record_modrm (&ir))
+        return -1;
+      if (ir.mod =3D=3D 3)
+        I386_RECORD_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b);
+      else
+        {
+          uint64_t tmpu64;
+          if (i386_record_lea_modrm_addr (&ir, &tmpu64))
+            return -1;
+          regcache_raw_read_unsigned (ir.regcache,
+                                      ir.regmap[ir.reg | rex_r],
+                                      &tmpulongest);
+          switch (ir.dflag)
+            {
+            case 0:
+              tmpu64 +=3D ((int16_t) tmpulongest >> 4) << 4;
+              break;
+            case 1:
+              tmpu64 +=3D ((int32_t) tmpulongest >> 5) << 5;
+              break;
+            case 2:
+              tmpu64 +=3D ((int64_t) tmpulongest >> 6) << 6;
+              break;
+            }
+          if (record_arch_list_add_mem (tmpu64, 1 << ir.ot))
+            return -1;
+          if (i386_record_lea_modrm (&ir))
+            return -1;
+        }
+      I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
       break;

       /* bsf */
     case 0x0fbc:
       /* bsr */
     case 0x0fbd:
-      if (record_arch_list_add_reg (ir.regcache, ir.reg))
-	return -1;
-      if (record_arch_list_add_reg (ir.regcache, I386_EFLAGS_REGNUM))
-	return -1;
+      I386_RECORD_ARCH_LIST_ADD_REG (ir.reg | rex_r);
+      I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
       break;

       /* bcd */
@@ -4758,10 +4807,13 @@ reswitch:
     case 0xd4:
       /* aad */
     case 0xd5:
-      if (record_arch_list_add_reg (ir.regcache, I386_EAX_REGNUM))
-	return -1;
-      if (record_arch_list_add_reg (ir.regcache, I386_EFLAGS_REGNUM))
-	return -1;
+      if (ir.regmap[X86_RECORD_R8_REGNUM])
+        {
+          ir.addr -=3D 1;
+          goto no_support;
+        }
+      I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
+      I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
       break;

       /* misc */
@@ -4853,16 +4905,18 @@ reswitch:
     case 0x0fcd:
     case 0x0fce:
     case 0x0fcf:
-      if (record_arch_list_add_reg (ir.regcache, opcode & 7))
-	return -1;
+      I386_RECORD_ARCH_LIST_ADD_REG ((opcode & 7) | ir.rex_b);
       break;

       /* salc */
     case 0xd6:
-      if (record_arch_list_add_reg (ir.regcache, I386_EAX_REGNUM))
-	return -1;
-      if (record_arch_list_add_reg (ir.regcache, I386_EFLAGS_REGNUM))
-	return -1;
+      if (ir.regmap[X86_RECORD_R8_REGNUM])
+        {
+          ir.addr -=3D 1;
+          goto no_support;
+        }
+      I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
+      I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
       break;

       /* loopnz */
@@ -4873,8 +4927,8 @@ reswitch:
     case 0xe2:
       /* jecxz */
     case 0xe3:
-      if (record_arch_list_add_reg (ir.regcache, I386_ECX_REGNUM))
-	return -1;
+      I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM);
+      I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
       break;

       /* wrmsr */
@@ -4905,6 +4959,11 @@ reswitch:
     case 0x0f34:
       {
 	int ret;
+        if (ir.regmap[X86_RECORD_R8_REGNUM])
+          {
+            ir.addr -=3D 2;
+            goto no_support;
+          }
 	if (gdbarch_tdep (gdbarch)->i386_sysenter_record =3D=3D NULL)
 	  {
 	    printf_unfiltered (_("Process record doesn't support "
@@ -4926,16 +4985,37 @@ reswitch:
       goto no_support;
       break;

+      /* syscall */
+    case 0x0f05:
+      {
+	int ret;
+	if (gdbarch_tdep (gdbarch)->i386_syscall_record =3D=3D NULL)
+	  {
+	    printf_unfiltered (_("Process record doesn't support "
+				 "instruction syscall.\n"));
+	    ir.addr -=3D 2;
+	    goto no_support;
+	  }
+	ret =3D gdbarch_tdep (gdbarch)->i386_syscall_record (ir.regcache);
+	if (ret)
+	  return ret;
+      }
+      break;
+
+      /* sysret */
+    case 0x0f07:
+      printf_unfiltered (_("Process record doesn't support "
+                           "instruction sysret.\n"));
+      ir.addr -=3D 2;
+      goto no_support;
+      break;
+
       /* cpuid */
     case 0x0fa2:
-      if (record_arch_list_add_reg (ir.regcache, I386_EAX_REGNUM))
-	return -1;
-      if (record_arch_list_add_reg (ir.regcache, I386_ECX_REGNUM))
-	return -1;
-      if (record_arch_list_add_reg (ir.regcache, I386_EDX_REGNUM))
-	return -1;
-      if (record_arch_list_add_reg (ir.regcache, I386_EBX_REGNUM))
-	return -1;
+      I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
+      I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM);
+      I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM);
+      I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBX_REGNUM);
       break;

       /* hlt */
@@ -4956,10 +5036,7 @@ reswitch:
 	  /* str */
 	case 1:
 	  if (ir.mod =3D=3D 3)
-	    {
-	      if (record_arch_list_add_reg (ir.regcache, ir.rm))
-		return -1;
-	    }
+            I386_RECORD_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b);
 	  else
 	    {
 	      ir.ot =3D OT_WORD;
@@ -4976,8 +5053,7 @@ reswitch:
 	case 4:
 	  /* verw */
 	case 5:
-	  if (record_arch_list_add_reg (ir.regcache, I386_EFLAGS_REGNUM))
-	    return -1;
+          I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
 	  break;
 	default:
 	  ir.addr -=3D 3;
@@ -4995,7 +5071,7 @@ reswitch:
 	  /* sgdt */
 	case 0:
 	  {
-	    uint32_t addr;
+	    uint64_t tmpu64;

 	    if (ir.mod =3D=3D 3)
 	      {
@@ -5003,8 +5079,7 @@ reswitch:
 		opcode =3D opcode << 8 | ir.modrm;
 		goto no_support;
 	      }
-
-	    if (ir.override)
+	    if (ir.override >=3D 0)
 	      {
 		if (record_debug)
 		  printf_unfiltered (_("Process record ignores the memory "
@@ -5016,13 +5091,21 @@ reswitch:
 	      }
 	    else
 	      {
-		if (i386_record_lea_modrm_addr (&ir, &addr))
-		  return -1;
-		if (record_arch_list_add_mem (addr, 2))
+		if (i386_record_lea_modrm_addr (&ir, &tmpu64))
 		  return -1;
-		addr +=3D 2;
-		if (record_arch_list_add_mem (addr, 4))
+		if (record_arch_list_add_mem (tmpu64, 2))
 		  return -1;
+		tmpu64 +=3D 2;
+                if (ir.regmap[X86_RECORD_R8_REGNUM])
+                  {
+                    if (record_arch_list_add_mem (tmpu64, 8))
+		      return -1;
+                  }
+                else
+                  {
+                    if (record_arch_list_add_mem (tmpu64, 4))
+		      return -1;
+                  }
 	      }
 	  }
 	  break;
@@ -5036,8 +5119,7 @@ reswitch:
 		  break;
 		  /* mwait */
 		case 1:
-		  if (record_arch_list_add_reg (ir.regcache, I386_EFLAGS_REGNUM))
-		    return -1;
+		  I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
 		  break;
 		default:
 		  ir.addr -=3D 3;
@@ -5049,7 +5131,7 @@ reswitch:
 	  else
 	    {
 	      /* sidt */
-	      if (ir.override)
+	      if (ir.override >=3D 0)
 		{
 		  if (record_debug)
 		    printf_unfiltered (_("Process record ignores the memory "
@@ -5061,15 +5143,23 @@ reswitch:
 		}
 	      else
 		{
-		  uint32_t addr;
+		  uint64_t tmpu64;

-		  if (i386_record_lea_modrm_addr (&ir, &addr))
+		  if (i386_record_lea_modrm_addr (&ir, &tmpu64))
 		    return -1;
-		  if (record_arch_list_add_mem (addr, 2))
+		  if (record_arch_list_add_mem (tmpu64, 2))
 		    return -1;
 		  addr +=3D 2;
-		  if (record_arch_list_add_mem (addr, 4))
-		    return -1;
+                  if (ir.regmap[X86_RECORD_R8_REGNUM])
+                    {
+                      if (record_arch_list_add_mem (tmpu64, 8))
+		        return -1;
+                    }
+                  else
+                    {
+                      if (record_arch_list_add_mem (tmpu64, 4))
+		        return -1;
+                    }
 		}
 	    }
 	  break;
@@ -5077,9 +5167,6 @@ reswitch:
 	case 2:
 	  /* lidt */
 	case 3:
-	  /* invlpg */
-	case 7:
-	default:
 	  if (ir.mod =3D=3D 3)
 	    {
 	      ir.addr -=3D 3;
@@ -5091,7 +5178,7 @@ reswitch:
 	case 4:
 	  if (ir.mod =3D=3D 3)
 	    {
-	      if (record_arch_list_add_reg (ir.regcache, ir.rm))
+	      if (record_arch_list_add_reg (ir.regcache, ir.rm | ir.rex_b))
 		return -1;
 	    }
 	  else
@@ -5100,9 +5187,32 @@ reswitch:
 	      if (i386_record_lea_modrm (&ir))
 		return -1;
 	    }
+	  I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
 	  break;
 	  /* lmsw */
 	case 6:
+	  I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
+	  break;
+	  /* invlpg */
+	case 7:
+	  if (ir.mod =3D=3D 3)
+	    {
+	      if (ir.rm =3D=3D 0 && ir.regmap[X86_RECORD_R8_REGNUM])
+	        I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_GS_REGNUM);
+	      else
+	        {
+	          ir.addr -=3D 3;
+	          opcode =3D opcode << 8 | ir.modrm;
+	          goto no_support;
+	        }
+	    }
+	  else
+	    I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
+	  break;
+	default:
+	  ir.addr -=3D 3;
+	  opcode =3D opcode << 8 | ir.modrm;
+	  goto no_support;
 	  break;
 	}
       break;
@@ -5115,21 +5225,21 @@ reswitch:

       /* arpl */
     case 0x63:
-      ir.ot =3D ir.dflag ? OT_LONG : OT_WORD;
       if (i386_record_modrm (&ir))
 	return -1;
-      if (ir.mod !=3D 3)
-	{
-	  if (i386_record_lea_modrm (&ir))
-	    return -1;
-	}
+      if (ir.mod =3D=3D 3 || ir.regmap[X86_RECORD_R8_REGNUM])
+        {
+          I386_RECORD_ARCH_LIST_ADD_REG (ir.regmap[X86_RECORD_R8_REGNUM]?
+                                           (ir.reg | rex_r) : ir.rm);
+        }
       else
-	{
-	  if (record_arch_list_add_reg (ir.regcache, ir.rm))
-	    return -1;
-	}
-      if (record_arch_list_add_reg (ir.regcache, I386_EFLAGS_REGNUM))
-	return -1;
+        {
+          ir.ot =3D ir.dflag ? OT_LONG : OT_WORD;
+          if (i386_record_lea_modrm (&ir))
+            return -1;
+        }
+      if (!ir.regmap[X86_RECORD_R8_REGNUM])
+        I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
       break;

       /* lar */
@@ -5138,13 +5248,19 @@ reswitch:
     case 0x0f03:
       if (i386_record_modrm (&ir))
 	return -1;
-      if (record_arch_list_add_reg (ir.regcache, ir.reg))
-	return -1;
-      if (record_arch_list_add_reg (ir.regcache, I386_EFLAGS_REGNUM))
-	return -1;
+      I386_RECORD_ARCH_LIST_ADD_REG (ir.reg | rex_r);
+      I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
       break;

     case 0x0f18:
+      if (i386_record_modrm (&ir))
+	return -1;
+      if (ir.mod =3D=3D 3 && ir.reg =3D=3D 3)
+        {
+	  ir.addr -=3D 3;
+	  opcode =3D opcode << 8 | ir.modrm;
+	  goto no_support;
+	}
       break;

       /* nop (multi byte) */
@@ -5165,7 +5281,7 @@ reswitch:
 	return -1;
       if ((ir.modrm & 0xc0) !=3D 0xc0)
 	{
-	  ir.addr -=3D 2;
+	  ir.addr -=3D 3;
 	  opcode =3D opcode << 8 | ir.modrm;
 	  goto no_support;
 	}
@@ -5177,16 +5293,12 @@ reswitch:
 	case 4:
 	case 8:
 	  if (opcode & 2)
-	    {
-	    }
+	    I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
 	  else
-	    {
-	      if (record_arch_list_add_reg (ir.regcache, ir.rm))
-		return -1;
-	    }
+            I386_RECORD_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b);
 	  break;
 	default:
-	  ir.addr -=3D 2;
+	  ir.addr -=3D 3;
 	  opcode =3D opcode << 8 | ir.modrm;
 	  goto no_support;
 	  break;
@@ -5202,22 +5314,19 @@ reswitch:
       if ((ir.modrm & 0xc0) !=3D 0xc0 || ir.reg =3D=3D 4
 	  || ir.reg =3D=3D 5 || ir.reg >=3D 8)
 	{
-	  ir.addr -=3D 2;
+	  ir.addr -=3D 3;
 	  opcode =3D opcode << 8 | ir.modrm;
 	  goto no_support;
 	}
       if (opcode & 2)
-	{
-	}
+        I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
       else
-	{
-	  if (record_arch_list_add_reg (ir.regcache, ir.rm))
-	    return -1;
-	}
+	I386_RECORD_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b);
       break;

       /* clts */
     case 0x0f06:
+      I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
       break;

       /* MMX/SSE/SSE2/PNI support */
@@ -5232,9 +5341,8 @@ reswitch:
       break;
     }

-/* In the future, Maybe still need to deal with need_dasm */
-  if (record_arch_list_add_reg (ir.regcache, I386_EIP_REGNUM))
-    return -1;
+  /* In the future, Maybe still need to deal with need_dasm */
+  I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REIP_REGNUM);
   if (record_arch_list_add_end ())
     return -1;

@@ -5247,6 +5355,15 @@ no_support:
   return -1;
 }

+static const int i386_record_regmap[] =3D
+{
+  I386_EAX_REGNUM, I386_ECX_REGNUM, I386_EDX_REGNUM, I386_EBX_REGNUM,
+  I386_ESP_REGNUM, I386_EBP_REGNUM, I386_ESI_REGNUM, I386_EDI_REGNUM,
+  0, 0, 0, 0, 0, 0, 0, 0,
+  I386_EIP_REGNUM, I386_EFLAGS_REGNUM, I386_CS_REGNUM, I386_SS_REGNUM,
+  I386_DS_REGNUM, I386_ES_REGNUM, I386_FS_REGNUM, I386_GS_REGNUM
+};
+

 static struct gdbarch *
 i386_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
@@ -5307,6 +5424,8 @@ i386_gdbarch_init (struct gdbarch_info i
   tdep->sc_pc_offset =3D -1;
   tdep->sc_sp_offset =3D -1;

+  tdep->record_regmap =3D i386_record_regmap;
+
   /* The format used for `long double' on almost all i386 targets is
      the i387 extended floating-point format.  In fact, of all targets
      in the GCC 2.95 tree, only OSF/1 does it different, and insists
--- a/i386-tdep.h
+++ b/i386-tdep.h
@@ -111,10 +111,15 @@ struct gdbarch_tdep
   struct type *i387_ext_type;

   /* Process record/replay target.  */
+  /* The map for registers because the AMD64's registers order
+     in GDB is not same as I386 instructions.  */
+  const int *record_regmap;
   /* Parse intx80 args.  */
   int (*i386_intx80_record) (struct regcache *regcache);
   /* Parse sysenter args.  */
   int (*i386_sysenter_record) (struct regcache *regcache);
+  /* Parse syscall args.  */
+  int (*i386_syscall_record) (struct regcache *regcache);
 };

 /* Floating-point registers.  */
@@ -151,6 +156,36 @@ enum i386_regnum
   I386_ST0_REGNUM		/* %st(0) */
 };

+/* Register numbers of RECORD_REGMAP.  */
+
+enum record_i386_regnum
+{
+  X86_RECORD_REAX_REGNUM,
+  X86_RECORD_RECX_REGNUM,
+  X86_RECORD_REDX_REGNUM,
+  X86_RECORD_REBX_REGNUM,
+  X86_RECORD_RESP_REGNUM,
+  X86_RECORD_REBP_REGNUM,
+  X86_RECORD_RESI_REGNUM,
+  X86_RECORD_REDI_REGNUM,
+  X86_RECORD_R8_REGNUM,
+  X86_RECORD_R9_REGNUM,
+  X86_RECORD_R10_REGNUM,
+  X86_RECORD_R11_REGNUM,
+  X86_RECORD_R12_REGNUM,
+  X86_RECORD_R13_REGNUM,
+  X86_RECORD_R14_REGNUM,
+  X86_RECORD_R15_REGNUM,
+  X86_RECORD_REIP_REGNUM,
+  X86_RECORD_EFLAGS_REGNUM,
+  X86_RECORD_CS_REGNUM,
+  X86_RECORD_SS_REGNUM,
+  X86_RECORD_DS_REGNUM,
+  X86_RECORD_ES_REGNUM,
+  X86_RECORD_FS_REGNUM,
+  X86_RECORD_GS_REGNUM,
+};
+
 #define I386_NUM_GREGS	16
 #define I386_NUM_FREGS	16
 #define I386_NUM_XREGS  9

--000e0cd14940469c15046ee2d3e5
Content-Type: text/plain; charset=US-ASCII; name="prec_amd64_tdep.txt"
Content-Disposition: attachment; filename="prec_amd64_tdep.txt"
Content-Transfer-Encoding: base64
X-Attachment-Id: f_fx8o4uh30
Content-length: 95905

LS0tCiBhbWQ2NC10ZGVwLmMgfCAgIDEyIAogaTM4Ni10ZGVwLmMgIHwgMTQz
NyArKysrKysrKysrKysrKysrKysrKysrKysrKysrKysrLS0tLS0tLS0tLS0t
LS0tLS0tLS0tLS0tLS0tLQogaTM4Ni10ZGVwLmggIHwgICAzNSArCiAzIGZp
bGVzIGNoYW5nZWQsIDgyNSBpbnNlcnRpb25zKCspLCA2NTkgZGVsZXRpb25z
KC0pCgotLS0gYS9hbWQ2NC10ZGVwLmMKKysrIGIvYW1kNjQtdGRlcC5jCkBA
IC0xOTg5LDYgKzE5ODksMTYgQEAgYW1kNjRfZ2V0X2xvbmdqbXBfdGFyZ2V0
IChzdHJ1Y3QgZnJhbWVfaQogICByZXR1cm4gMTsKIH0KIAorc3RhdGljIGNv
bnN0IGludCBhbWQ2NF9yZWNvcmRfcmVnbWFwW10gPQoreworICBBTUQ2NF9S
QVhfUkVHTlVNLCBBTUQ2NF9SQ1hfUkVHTlVNLCBBTUQ2NF9SRFhfUkVHTlVN
LCBBTUQ2NF9SQlhfUkVHTlVNLAorICBBTUQ2NF9SU1BfUkVHTlVNLCBBTUQ2
NF9SQlBfUkVHTlVNLCBBTUQ2NF9SU0lfUkVHTlVNLCBBTUQ2NF9SRElfUkVH
TlVNLAorICBBTUQ2NF9SOF9SRUdOVU0sIEFNRDY0X1I5X1JFR05VTSwgQU1E
NjRfUjEwX1JFR05VTSwgQU1ENjRfUjExX1JFR05VTSwKKyAgQU1ENjRfUjEy
X1JFR05VTSwgQU1ENjRfUjEzX1JFR05VTSwgQU1ENjRfUjE0X1JFR05VTSwg
QU1ENjRfUjE1X1JFR05VTSwKKyAgQU1ENjRfUklQX1JFR05VTSwgQU1ENjRf
RUZMQUdTX1JFR05VTSwgQU1ENjRfQ1NfUkVHTlVNLCBBTUQ2NF9TU19SRUdO
VU0sCisgIEFNRDY0X0RTX1JFR05VTSwgQU1ENjRfRVNfUkVHTlVNLCBBTUQ2
NF9GU19SRUdOVU0sIEFNRDY0X0dTX1JFR05VTQorfTsKKwogdm9pZAogYW1k
NjRfaW5pdF9hYmkgKHN0cnVjdCBnZGJhcmNoX2luZm8gaW5mbywgc3RydWN0
IGdkYmFyY2ggKmdkYmFyY2gpCiB7CkBAIC0yMDUxLDYgKzIwNjEsOCBAQCBh
bWQ2NF9pbml0X2FiaSAoc3RydWN0IGdkYmFyY2hfaW5mbyBpbmZvCiAgIHNl
dF9nZGJhcmNoX251bV9wc2V1ZG9fcmVncyAoZ2RiYXJjaCwgMCk7CiAgIHRk
ZXAtPm1tMF9yZWdudW0gPSAtMTsKIAorICB0ZGVwLT5yZWNvcmRfcmVnbWFw
ID0gYW1kNjRfcmVjb3JkX3JlZ21hcDsKKwogICBzZXRfZ2RiYXJjaF9kdW1t
eV9pZCAoZ2RiYXJjaCwgYW1kNjRfZHVtbXlfaWQpOwogCiAgIGZyYW1lX3Vu
d2luZF9hcHBlbmRfdW53aW5kZXIgKGdkYmFyY2gsICZhbWQ2NF9zaWd0cmFt
cF9mcmFtZV91bndpbmQpOwotLS0gYS9pMzg2LXRkZXAuYworKysgYi9pMzg2
LXRkZXAuYwpAQCAtMjg0Nyw2ICsyODQ3LDcgQEAgZW51bQogICBPVF9CWVRF
ID0gMCwKICAgT1RfV09SRCwKICAgT1RfTE9ORywKKyAgT1RfUVVBRCwKIH07
CiAKIC8qIGkzODYgYXJpdGgvbG9naWMgb3BlcmF0aW9ucyAqLwpAQCAtMjg2
NCw2ICsyODY1LDcgQEAgZW51bQogCiBzdHJ1Y3QgaTM4Nl9yZWNvcmRfcwog
eworICBzdHJ1Y3QgZ2RiYXJjaCAqZ2RiYXJjaDsKICAgc3RydWN0IHJlZ2Nh
Y2hlICpyZWdjYWNoZTsKICAgQ09SRV9BRERSIGFkZHI7CiAgIGludCBhZmxh
ZzsKQEAgLTI4NzIsNiArMjg3NCwxMSBAQCBzdHJ1Y3QgaTM4Nl9yZWNvcmRf
cwogICB1aW50OF90IG1vZHJtOwogICB1aW50OF90IG1vZCwgcmVnLCBybTsK
ICAgaW50IG90OworICB1aW50OF90IHJleF94OworICB1aW50OF90IHJleF9i
OworICBpbnQgcmlwX29mZnNldDsKKyAgaW50IHBvcGxfZXNwX2hhY2s7Cisg
IGNvbnN0IGludCAqcmVnbWFwOwogfTsKIAogLyogUGFyc2UgIm1vZHJtIiBw
YXJ0IGluIGN1cnJlbnQgbWVtb3J5IGFkZHJlc3MgdGhhdCBpcnAtPmFkZHIg
cG9pbnQgdG8KQEAgLTI4ODAsNyArMjg4Nyw3IEBAIHN0cnVjdCBpMzg2X3Jl
Y29yZF9zCiBzdGF0aWMgaW50CiBpMzg2X3JlY29yZF9tb2RybSAoc3RydWN0
IGkzODZfcmVjb3JkX3MgKmlycCkKIHsKLSAgc3RydWN0IGdkYmFyY2ggKmdk
YmFyY2ggPSBnZXRfcmVnY2FjaGVfYXJjaCAoaXJwLT5yZWdjYWNoZSk7Cisg
IHN0cnVjdCBnZGJhcmNoICpnZGJhcmNoID0gaXJwLT5nZGJhcmNoOwogCiAg
IGlmICh0YXJnZXRfcmVhZF9tZW1vcnkgKGlycC0+YWRkciwgJmlycC0+bW9k
cm0sIDEpKQogICAgIHsKQEAgLTI5MDMsMTIgKzI5MTAsMTMgQEAgaTM4Nl9y
ZWNvcmRfbW9kcm0gKHN0cnVjdCBpMzg2X3JlY29yZF9zIAogICAgUmV0dXJu
IC0xIGlmIHNvbWV0aGluZyB3cm9uZy4gKi8KIAogc3RhdGljIGludAotaTM4
Nl9yZWNvcmRfbGVhX21vZHJtX2FkZHIgKHN0cnVjdCBpMzg2X3JlY29yZF9z
ICppcnAsIHVpbnQzMl90ICogYWRkcikKK2kzODZfcmVjb3JkX2xlYV9tb2Ry
bV9hZGRyIChzdHJ1Y3QgaTM4Nl9yZWNvcmRfcyAqaXJwLCB1aW50NjRfdCAq
YWRkcikKIHsKLSAgc3RydWN0IGdkYmFyY2ggKmdkYmFyY2ggPSBnZXRfcmVn
Y2FjaGVfYXJjaCAoaXJwLT5yZWdjYWNoZSk7CisgIHN0cnVjdCBnZGJhcmNo
ICpnZGJhcmNoID0gaXJwLT5nZGJhcmNoOwogICB1aW50OF90IHRtcHU4Owot
ICB1aW50MTZfdCB0bXB1MTY7Ci0gIHVpbnQzMl90IHRtcHUzMjsKKyAgaW50
MTZfdCB0bXBpMTY7CisgIGludDMyX3QgdG1waTMyOworICBVTE9OR0VTVCB0
bXB1bG9uZ2VzdDsKIAogICAqYWRkciA9IDA7CiAgIGlmIChpcnAtPmFmbGFn
KQpAQCAtMjkzMiw5ICsyOTQwLDEwIEBAIGkzODZfcmVjb3JkX2xlYV9tb2Ry
bV9hZGRyIChzdHJ1Y3QgaTM4Nl8KIAkgICAgfQogCSAgaXJwLT5hZGRyKys7
CiAJICBzY2FsZSA9ICh0bXB1OCA+PiA2KSAmIDM7Ci0JICBpbmRleCA9ICgo
dG1wdTggPj4gMykgJiA3KTsKKwkgIGluZGV4ID0gKCh0bXB1OCA+PiAzKSAm
IDcpIHwgaXJwLT5yZXhfeDsKIAkgIGJhc2UgPSAodG1wdTggJiA3KTsKIAl9
CisgICAgICBiYXNlIHw9IGlycC0+cmV4X2I7CiAKICAgICAgIHN3aXRjaCAo
aXJwLT5tb2QpCiAJewpAQCAtMjk0Miw3ICsyOTUxLDcgQEAgaTM4Nl9yZWNv
cmRfbGVhX21vZHJtX2FkZHIgKHN0cnVjdCBpMzg2XwogCSAgaWYgKChiYXNl
ICYgNykgPT0gNSkKIAkgICAgewogCSAgICAgIGJhc2UgPSAweGZmOwotCSAg
ICAgIGlmICh0YXJnZXRfcmVhZF9tZW1vcnkgKGlycC0+YWRkciwgKGdkYl9i
eXRlICopIGFkZHIsIDQpKQorCSAgICAgIGlmICh0YXJnZXRfcmVhZF9tZW1v
cnkgKGlycC0+YWRkciwgKGdkYl9ieXRlICopICZ0bXBpMzIsIDQpKQogCQl7
CiAJCSAgaWYgKHJlY29yZF9kZWJ1ZykKIAkJICAgIHByaW50Zl91bmZpbHRl
cmVkIChfKCJQcm9jZXNzIHJlY29yZDogZXJyb3IgcmVhZGluZyAiCkBAIC0y
OTUxLDYgKzI5NjAsOSBAQCBpMzg2X3JlY29yZF9sZWFfbW9kcm1fYWRkciAo
c3RydWN0IGkzODZfCiAJCSAgcmV0dXJuIC0xOwogCQl9CiAJICAgICAgaXJw
LT5hZGRyICs9IDQ7CisJICAgICAgKmFkZHIgPSB0bXBpMzI7CisJICAgICAg
aWYgKGlycC0+cmVnbWFwW1g4Nl9SRUNPUkRfUjhfUkVHTlVNXSAmJiAhaGF2
ZXNpYikKKwkJKmFkZHIgKz0gaXJwLT5hZGRyICsgaXJwLT5yaXBfb2Zmc2V0
OwogCSAgICB9CiAJICBlbHNlCiAJICAgIHsKQEAgLTI5NzAsNyArMjk4Miw3
IEBAIGkzODZfcmVjb3JkX2xlYV9tb2RybV9hZGRyIChzdHJ1Y3QgaTM4Nl8K
IAkgICphZGRyID0gKGludDhfdCkgdG1wdTg7CiAJICBicmVhazsKIAljYXNl
IDI6Ci0JICBpZiAodGFyZ2V0X3JlYWRfbWVtb3J5IChpcnAtPmFkZHIsIChn
ZGJfYnl0ZSAqKSBhZGRyLCA0KSkKKwkgIGlmICh0YXJnZXRfcmVhZF9tZW1v
cnkgKGlycC0+YWRkciwgKGdkYl9ieXRlICopICZ0bXBpMzIsIDQpKQogCSAg
ICB7CiAJICAgICAgaWYgKHJlY29yZF9kZWJ1ZykKIAkJcHJpbnRmX3VuZmls
dGVyZWQgKF8oIlByb2Nlc3MgcmVjb3JkOiBlcnJvciByZWFkaW5nIG1lbW9y
eSAiCkBAIC0yOTc4LDIxICsyOTkwLDM0IEBAIGkzODZfcmVjb3JkX2xlYV9t
b2RybV9hZGRyIChzdHJ1Y3QgaTM4Nl8KIAkJCQkgICBwYWRkcmVzcyAoZ2Ri
YXJjaCwgaXJwLT5hZGRyKSk7CiAJICAgICAgcmV0dXJuIC0xOwogCSAgICB9
CisJICAqYWRkciA9IHRtcGkzMjsKIAkgIGlycC0+YWRkciArPSA0OwogCSAg
YnJlYWs7CiAJfQogCisgICAgICB0bXB1bG9uZ2VzdCA9IDA7CiAgICAgICBp
ZiAoYmFzZSAhPSAweGZmKQotCXsKLQkgIHJlZ2NhY2hlX3Jhd19yZWFkIChp
cnAtPnJlZ2NhY2hlLCBiYXNlLCAoZ2RiX2J5dGUgKikgJiB0bXB1MzIpOwot
CSAgKmFkZHIgKz0gdG1wdTMyOworICAgICAgICB7CisJICBpZiAoYmFzZSA9
PSA0ICYmIGlycC0+cG9wbF9lc3BfaGFjaykKKwkgICAgKmFkZHIgKz0gaXJw
LT5wb3BsX2VzcF9oYWNrOworCSAgcmVnY2FjaGVfcmF3X3JlYWRfdW5zaWdu
ZWQgKGlycC0+cmVnY2FjaGUsIGlycC0+cmVnbWFwW2Jhc2VdLAorICAgICAg
ICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAmdG1wdWxvbmdlc3Qp
OwogCX0KKyAgICAgIGlmIChpcnAtPmFmbGFnID09IDIpCisgICAgICAgIHsK
KwkgICphZGRyICs9IHRtcHVsb25nZXN0OworICAgICAgICB9CisgICAgICBl
bHNlCisgICAgICAgICphZGRyID0gKHVpbnQzMl90KSAodG1wdWxvbmdlc3Qg
KyAqYWRkcik7CiAKLSAgICAgIC8qIFhYWDogaW5kZXggPT0gNCBpcyBhbHdh
eXMgaW52YWxpZCAqLwogICAgICAgaWYgKGhhdmVzaWIgJiYgKGluZGV4ICE9
IDQgfHwgc2NhbGUgIT0gMCkpCiAJewotCSAgcmVnY2FjaGVfcmF3X3JlYWQg
KGlycC0+cmVnY2FjaGUsIGluZGV4LCAoZ2RiX2J5dGUgKikgJiB0bXB1MzIp
OwotCSAgKmFkZHIgKz0gdG1wdTMyIDw8IHNjYWxlOworCSAgcmVnY2FjaGVf
cmF3X3JlYWRfdW5zaWduZWQgKGlycC0+cmVnY2FjaGUsIGlycC0+cmVnbWFw
W2luZGV4XSwKKyAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAg
ICAgJnRtcHVsb25nZXN0KTsKKwkgIGlmIChpcnAtPmFmbGFnID09IDIpCisJ
ICAgICphZGRyICs9IHRtcHVsb25nZXN0IDw8IHNjYWxlOworCSAgZWxzZQor
CSAgICAqYWRkciA9ICh1aW50MzJfdCkgKCphZGRyICsgKHRtcHVsb25nZXN0
IDw8IHNjYWxlKSk7CiAJfQogICAgIH0KICAgZWxzZQpAQCAtMzAwNCw3ICsz
MDI5LDcgQEAgaTM4Nl9yZWNvcmRfbGVhX21vZHJtX2FkZHIgKHN0cnVjdCBp
Mzg2XwogCSAgaWYgKGlycC0+cm0gPT0gNikKIAkgICAgewogCSAgICAgIGlm
ICh0YXJnZXRfcmVhZF9tZW1vcnkKLQkJICAoaXJwLT5hZGRyLCAoZ2RiX2J5
dGUgKikgJiB0bXB1MTYsIDIpKQorCQkgIChpcnAtPmFkZHIsIChnZGJfYnl0
ZSAqKSAmdG1waTE2LCAyKSkKIAkJewogCQkgIGlmIChyZWNvcmRfZGVidWcp
CiAJCSAgICBwcmludGZfdW5maWx0ZXJlZCAoXygiUHJvY2VzcyByZWNvcmQ6
IGVycm9yIHJlYWRpbmcgIgpAQCAtMzAxMyw3ICszMDM4LDcgQEAgaTM4Nl9y
ZWNvcmRfbGVhX21vZHJtX2FkZHIgKHN0cnVjdCBpMzg2XwogCQkgIHJldHVy
biAtMTsKIAkJfQogCSAgICAgIGlycC0+YWRkciArPSAyOwotCSAgICAgICph
ZGRyID0gKGludDE2X3QpIHRtcHUxNjsKKwkgICAgICAqYWRkciA9IHRtcGkx
NjsKIAkgICAgICBpcnAtPnJtID0gMDsKIAkgICAgICBnb3RvIG5vX3JtOwog
CSAgICB9CkBAIC0zMDM1LDcgKzMwNjAsNyBAQCBpMzg2X3JlY29yZF9sZWFf
bW9kcm1fYWRkciAoc3RydWN0IGkzODZfCiAJICAqYWRkciA9IChpbnQ4X3Qp
IHRtcHU4OwogCSAgYnJlYWs7CiAJY2FzZSAyOgotCSAgaWYgKHRhcmdldF9y
ZWFkX21lbW9yeSAoaXJwLT5hZGRyLCAoZ2RiX2J5dGUgKikgJiB0bXB1MTYs
IDIpKQorCSAgaWYgKHRhcmdldF9yZWFkX21lbW9yeSAoaXJwLT5hZGRyLCAo
Z2RiX2J5dGUgKikgJnRtcGkxNiwgMikpCiAJICAgIHsKIAkgICAgICBpZiAo
cmVjb3JkX2RlYnVnKQogCQlwcmludGZfdW5maWx0ZXJlZCAoXygiUHJvY2Vz
cyByZWNvcmQ6IGVycm9yIHJlYWRpbmcgbWVtb3J5ICIKQEAgLTMwNDQsNjMg
KzMwNjksNzUgQEAgaTM4Nl9yZWNvcmRfbGVhX21vZHJtX2FkZHIgKHN0cnVj
dCBpMzg2XwogCSAgICAgIHJldHVybiAtMTsKIAkgICAgfQogCSAgaXJwLT5h
ZGRyICs9IDI7Ci0JICAqYWRkciA9IChpbnQxNl90KSB0bXB1MTY7CisJICAq
YWRkciA9IHRtcGkxNjsKIAkgIGJyZWFrOwogCX0KIAogICAgICAgc3dpdGNo
IChpcnAtPnJtKQogCXsKIAljYXNlIDA6Ci0JICByZWdjYWNoZV9yYXdfcmVh
ZCAoaXJwLT5yZWdjYWNoZSwgSTM4Nl9FQlhfUkVHTlVNLAotCQkJICAgICAo
Z2RiX2J5dGUgKikgJiB0bXB1MzIpOwotCSAgKmFkZHIgKz0gdG1wdTMyOwot
CSAgcmVnY2FjaGVfcmF3X3JlYWQgKGlycC0+cmVnY2FjaGUsIEkzODZfRVNJ
X1JFR05VTSwKLQkJCSAgICAgKGdkYl9ieXRlICopICYgdG1wdTMyKTsKLQkg
ICphZGRyICs9IHRtcHUzMjsKKwkgIHJlZ2NhY2hlX3Jhd19yZWFkX3Vuc2ln
bmVkIChpcnAtPnJlZ2NhY2hlLAorCQkJCSAgICAgIGlycC0+cmVnbWFwW1g4
Nl9SRUNPUkRfUkVCWF9SRUdOVU1dLAorICAgICAgICAgICAgICAgICAgICAg
ICAgICAgICAgICAgICAgICAmdG1wdWxvbmdlc3QpOworCSAgKmFkZHIgPSAo
dWludDMyX3QpICgqYWRkciArIHRtcHVsb25nZXN0KTsKKwkgIHJlZ2NhY2hl
X3Jhd19yZWFkX3Vuc2lnbmVkIChpcnAtPnJlZ2NhY2hlLAorCQkJCSAgICAg
IGlycC0+cmVnbWFwW1g4Nl9SRUNPUkRfUkVTSV9SRUdOVU1dLAorICAgICAg
ICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAmdG1wdWxvbmdlc3Qp
OworCSAgKmFkZHIgPSAodWludDMyX3QpICgqYWRkciArIHRtcHVsb25nZXN0
KTsKIAkgIGJyZWFrOwogCWNhc2UgMToKLQkgIHJlZ2NhY2hlX3Jhd19yZWFk
IChpcnAtPnJlZ2NhY2hlLCBJMzg2X0VCWF9SRUdOVU0sCi0JCQkgICAgIChn
ZGJfYnl0ZSAqKSAmIHRtcHUzMik7Ci0JICAqYWRkciArPSB0bXB1MzI7Ci0J
ICByZWdjYWNoZV9yYXdfcmVhZCAoaXJwLT5yZWdjYWNoZSwgSTM4Nl9FRElf
UkVHTlVNLAotCQkJICAgICAoZ2RiX2J5dGUgKikgJiB0bXB1MzIpOwotCSAg
KmFkZHIgKz0gdG1wdTMyOworCSAgcmVnY2FjaGVfcmF3X3JlYWRfdW5zaWdu
ZWQgKGlycC0+cmVnY2FjaGUsCisJCQkJICAgICAgaXJwLT5yZWdtYXBbWDg2
X1JFQ09SRF9SRUJYX1JFR05VTV0sCisgICAgICAgICAgICAgICAgICAgICAg
ICAgICAgICAgICAgICAgICZ0bXB1bG9uZ2VzdCk7CisJICAqYWRkciA9ICh1
aW50MzJfdCkgKCphZGRyICsgdG1wdWxvbmdlc3QpOworCSAgcmVnY2FjaGVf
cmF3X3JlYWRfdW5zaWduZWQgKGlycC0+cmVnY2FjaGUsCisJCQkJICAgICAg
aXJwLT5yZWdtYXBbWDg2X1JFQ09SRF9SRURJX1JFR05VTV0sCisgICAgICAg
ICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICZ0bXB1bG9uZ2VzdCk7
CisJICAqYWRkciA9ICh1aW50MzJfdCkgKCphZGRyICsgdG1wdWxvbmdlc3Qp
OwogCSAgYnJlYWs7CiAJY2FzZSAyOgotCSAgcmVnY2FjaGVfcmF3X3JlYWQg
KGlycC0+cmVnY2FjaGUsIEkzODZfRUJQX1JFR05VTSwKLQkJCSAgICAgKGdk
Yl9ieXRlICopICYgdG1wdTMyKTsKLQkgICphZGRyICs9IHRtcHUzMjsKLQkg
IHJlZ2NhY2hlX3Jhd19yZWFkIChpcnAtPnJlZ2NhY2hlLCBJMzg2X0VTSV9S
RUdOVU0sCi0JCQkgICAgIChnZGJfYnl0ZSAqKSAmIHRtcHUzMik7Ci0JICAq
YWRkciArPSB0bXB1MzI7CisJICByZWdjYWNoZV9yYXdfcmVhZF91bnNpZ25l
ZCAoaXJwLT5yZWdjYWNoZSwKKwkJCQkgICAgICBpcnAtPnJlZ21hcFtYODZf
UkVDT1JEX1JFQlBfUkVHTlVNXSwKKyAgICAgICAgICAgICAgICAgICAgICAg
ICAgICAgICAgICAgICAgJnRtcHVsb25nZXN0KTsKKwkgICphZGRyID0gKHVp
bnQzMl90KSAoKmFkZHIgKyB0bXB1bG9uZ2VzdCk7CisJICByZWdjYWNoZV9y
YXdfcmVhZF91bnNpZ25lZCAoaXJwLT5yZWdjYWNoZSwKKwkJCQkgICAgICBp
cnAtPnJlZ21hcFtYODZfUkVDT1JEX1JFU0lfUkVHTlVNXSwKKyAgICAgICAg
ICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgJnRtcHVsb25nZXN0KTsK
KwkgICphZGRyID0gKHVpbnQzMl90KSAoKmFkZHIgKyB0bXB1bG9uZ2VzdCk7
CiAJICBicmVhazsKIAljYXNlIDM6Ci0JICByZWdjYWNoZV9yYXdfcmVhZCAo
aXJwLT5yZWdjYWNoZSwgSTM4Nl9FQlBfUkVHTlVNLAotCQkJICAgICAoZ2Ri
X2J5dGUgKikgJiB0bXB1MzIpOwotCSAgKmFkZHIgKz0gdG1wdTMyOwotCSAg
cmVnY2FjaGVfcmF3X3JlYWQgKGlycC0+cmVnY2FjaGUsIEkzODZfRURJX1JF
R05VTSwKLQkJCSAgICAgKGdkYl9ieXRlICopICYgdG1wdTMyKTsKLQkgICph
ZGRyICs9IHRtcHUzMjsKKwkgIHJlZ2NhY2hlX3Jhd19yZWFkX3Vuc2lnbmVk
IChpcnAtPnJlZ2NhY2hlLAorCQkJCSAgICAgIGlycC0+cmVnbWFwW1g4Nl9S
RUNPUkRfUkVCUF9SRUdOVU1dLAorICAgICAgICAgICAgICAgICAgICAgICAg
ICAgICAgICAgICAgICAmdG1wdWxvbmdlc3QpOworCSAgKmFkZHIgPSAodWlu
dDMyX3QpICgqYWRkciArIHRtcHVsb25nZXN0KTsKKwkgIHJlZ2NhY2hlX3Jh
d19yZWFkX3Vuc2lnbmVkIChpcnAtPnJlZ2NhY2hlLAorCQkJCSAgICAgIGly
cC0+cmVnbWFwW1g4Nl9SRUNPUkRfUkVESV9SRUdOVU1dLAorICAgICAgICAg
ICAgICAgICAgICAgICAgICAgICAgICAgICAgICAmdG1wdWxvbmdlc3QpOwor
CSAgKmFkZHIgPSAodWludDMyX3QpICgqYWRkciArIHRtcHVsb25nZXN0KTsK
IAkgIGJyZWFrOwogCWNhc2UgNDoKLQkgIHJlZ2NhY2hlX3Jhd19yZWFkIChp
cnAtPnJlZ2NhY2hlLCBJMzg2X0VTSV9SRUdOVU0sCi0JCQkgICAgIChnZGJf
Ynl0ZSAqKSAmIHRtcHUzMik7Ci0JICAqYWRkciArPSB0bXB1MzI7CisJICBy
ZWdjYWNoZV9yYXdfcmVhZF91bnNpZ25lZCAoaXJwLT5yZWdjYWNoZSwKKwkJ
CQkgICAgICBpcnAtPnJlZ21hcFtYODZfUkVDT1JEX1JFU0lfUkVHTlVNXSwK
KyAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgJnRtcHVs
b25nZXN0KTsKKwkgICphZGRyID0gKHVpbnQzMl90KSAoKmFkZHIgKyB0bXB1
bG9uZ2VzdCk7CiAJICBicmVhazsKIAljYXNlIDU6Ci0JICByZWdjYWNoZV9y
YXdfcmVhZCAoaXJwLT5yZWdjYWNoZSwgSTM4Nl9FRElfUkVHTlVNLAotCQkJ
ICAgICAoZ2RiX2J5dGUgKikgJiB0bXB1MzIpOwotCSAgKmFkZHIgKz0gdG1w
dTMyOworCSAgcmVnY2FjaGVfcmF3X3JlYWRfdW5zaWduZWQgKGlycC0+cmVn
Y2FjaGUsCisJCQkJICAgICAgaXJwLT5yZWdtYXBbWDg2X1JFQ09SRF9SRURJ
X1JFR05VTV0sCisgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAg
ICAgICZ0bXB1bG9uZ2VzdCk7CisJICAqYWRkciA9ICh1aW50MzJfdCkgKCph
ZGRyICsgdG1wdWxvbmdlc3QpOwogCSAgYnJlYWs7CiAJY2FzZSA2OgotCSAg
cmVnY2FjaGVfcmF3X3JlYWQgKGlycC0+cmVnY2FjaGUsIEkzODZfRUJQX1JF
R05VTSwKLQkJCSAgICAgKGdkYl9ieXRlICopICYgdG1wdTMyKTsKLQkgICph
ZGRyICs9IHRtcHUzMjsKKwkgIHJlZ2NhY2hlX3Jhd19yZWFkX3Vuc2lnbmVk
IChpcnAtPnJlZ2NhY2hlLAorCQkJCSAgICAgIGlycC0+cmVnbWFwW1g4Nl9S
RUNPUkRfUkVCUF9SRUdOVU1dLAorICAgICAgICAgICAgICAgICAgICAgICAg
ICAgICAgICAgICAgICAmdG1wdWxvbmdlc3QpOworCSAgKmFkZHIgPSAodWlu
dDMyX3QpICgqYWRkciArIHRtcHVsb25nZXN0KTsKIAkgIGJyZWFrOwogCWNh
c2UgNzoKLQkgIHJlZ2NhY2hlX3Jhd19yZWFkIChpcnAtPnJlZ2NhY2hlLCBJ
Mzg2X0VCWF9SRUdOVU0sCi0JCQkgICAgIChnZGJfYnl0ZSAqKSAmIHRtcHUz
Mik7Ci0JICAqYWRkciArPSB0bXB1MzI7CisJICByZWdjYWNoZV9yYXdfcmVh
ZF91bnNpZ25lZCAoaXJwLT5yZWdjYWNoZSwKKwkJCQkgICAgICBpcnAtPnJl
Z21hcFtYODZfUkVDT1JEX1JFQlhfUkVHTlVNXSwKKyAgICAgICAgICAgICAg
ICAgICAgICAgICAgICAgICAgICAgICAgJnRtcHVsb25nZXN0KTsKKwkgICph
ZGRyID0gKHVpbnQzMl90KSAoKmFkZHIgKyB0bXB1bG9uZ2VzdCk7CiAJICBi
cmVhazsKIAl9CiAgICAgICAqYWRkciAmPSAweGZmZmY7CkBAIC0zMTE3LDEw
ICszMTU0LDEwIEBAIG5vX3JtOgogc3RhdGljIGludAogaTM4Nl9yZWNvcmRf
bGVhX21vZHJtIChzdHJ1Y3QgaTM4Nl9yZWNvcmRfcyAqaXJwKQogewotICBz
dHJ1Y3QgZ2RiYXJjaCAqZ2RiYXJjaCA9IGdldF9yZWdjYWNoZV9hcmNoIChp
cnAtPnJlZ2NhY2hlKTsKLSAgdWludDMyX3QgYWRkcjsKKyAgc3RydWN0IGdk
YmFyY2ggKmdkYmFyY2ggPSBpcnAtPmdkYmFyY2g7CisgIHVpbnQ2NF90IGFk
ZHI7CiAKLSAgaWYgKGlycC0+b3ZlcnJpZGUpCisgIGlmIChpcnAtPm92ZXJy
aWRlID49IDApCiAgICAgewogICAgICAgaWYgKHJlY29yZF9kZWJ1ZykKIAlw
cmludGZfdW5maWx0ZXJlZCAoXygiUHJvY2VzcyByZWNvcmQgaWdub3JlcyB0
aGUgbWVtb3J5IGNoYW5nZSAiCkBAIC0zMTM5LDEwICszMTc2LDM2IEBAIGkz
ODZfcmVjb3JkX2xlYV9tb2RybSAoc3RydWN0IGkzODZfcmVjb3IKICAgcmV0
dXJuIDA7CiB9CiAKKy8qIFJlY29yZCB0aGUgcHVzaCBvcGVyYXRpb24gdG8g
InJlY29yZF9hcmNoX2xpc3QiLgorICAgUmV0dXJuIC0xIGlmIHNvbWV0aGlu
ZyB3cm9uZy4gKi8KKworc3RhdGljIGludAoraTM4Nl9yZWNvcmRfcHVzaCAo
c3RydWN0IGkzODZfcmVjb3JkX3MgKmlycCwgaW50IHNpemUpCit7CisgIFVM
T05HRVNUIHRtcHVsb25nZXN0OworCisgIGlmIChyZWNvcmRfYXJjaF9saXN0
X2FkZF9yZWcgKGlycC0+cmVnY2FjaGUsCisJCQkJaXJwLT5yZWdtYXBbWDg2
X1JFQ09SRF9SRVNQX1JFR05VTV0pKQorICAgIHJldHVybiAtMTsKKyAgcmVn
Y2FjaGVfcmF3X3JlYWRfdW5zaWduZWQgKGlycC0+cmVnY2FjaGUsCisJCQkg
ICAgICBpcnAtPnJlZ21hcFtYODZfUkVDT1JEX1JFU1BfUkVHTlVNXSwKKwkJ
CSAgICAgICZ0bXB1bG9uZ2VzdCk7CisgIGlmIChyZWNvcmRfYXJjaF9saXN0
X2FkZF9tZW0gKChDT1JFX0FERFIpIHRtcHVsb25nZXN0IC0gc2l6ZSwgc2l6
ZSkpCisgICAgcmV0dXJuIC0xOworCisgIHJldHVybiAwOworfQorCiAvKiBQ
YXJzZSB0aGUgY3VycmVudCBpbnN0cnVjdGlvbiBhbmQgcmVjb3JkIHRoZSB2
YWx1ZXMgb2YgdGhlIHJlZ2lzdGVycyBhbmQKICAgIG1lbW9yeSB0aGF0IHdp
bGwgYmUgY2hhbmdlZCBpbiBjdXJyZW50IGluc3RydWN0aW9uIHRvICJyZWNv
cmRfYXJjaF9saXN0Ii4KICAgIFJldHVybiAtMSBpZiBzb21ldGhpbmcgd3Jv
bmcuICovCiAKKyNkZWZpbmUgSTM4Nl9SRUNPUkRfQVJDSF9MSVNUX0FERF9S
RUcocmVnbnVtKSBcCisgICAgZG8geyBcCisgICAgICAgICBpZiAocmVjb3Jk
X2FyY2hfbGlzdF9hZGRfcmVnIChpci5yZWdjYWNoZSwgaXIucmVnbWFwWyhy
ZWdudW0pXSkpIFwKKyAgICAgICAgIHJldHVybiAtMTsgXAorICAgICAgIH0g
d2hpbGUgKDApCisKIGludAogaTM4Nl9wcm9jZXNzX3JlY29yZCAoc3RydWN0
IGdkYmFyY2ggKmdkYmFyY2gsIHN0cnVjdCByZWdjYWNoZSAqcmVnY2FjaGUs
CiAJCSAgICAgQ09SRV9BRERSIGFkZHIpCkBAIC0zMTUxLDE0ICszMjE0LDIx
IEBAIGkzODZfcHJvY2Vzc19yZWNvcmQgKHN0cnVjdCBnZGJhcmNoICpnZGIK
ICAgdWludDhfdCB0bXB1ODsKICAgdWludDE2X3QgdG1wdTE2OwogICB1aW50
MzJfdCB0bXB1MzI7CisgIFVMT05HRVNUIHRtcHVsb25nZXN0OwogICB1aW50
MzJfdCBvcGNvZGU7CiAgIHN0cnVjdCBpMzg2X3JlY29yZF9zIGlyOworICBp
bnQgcmV4ID0gMDsKKyAgdWludDhfdCByZXhfdyA9IC0xOworICB1aW50OF90
IHJleF9yID0gMDsKIAogICBtZW1zZXQgKCZpciwgMCwgc2l6ZW9mIChzdHJ1
Y3QgaTM4Nl9yZWNvcmRfcykpOwogICBpci5yZWdjYWNoZSA9IHJlZ2NhY2hl
OwogICBpci5hZGRyID0gYWRkcjsKICAgaXIuYWZsYWcgPSAxOwogICBpci5k
ZmxhZyA9IDE7CisgIGlyLm92ZXJyaWRlID0gLTE7CisgIGlyLnJlZ21hcCA9
IGdkYmFyY2hfdGRlcCAoZ2RiYXJjaCktPnJlY29yZF9yZWdtYXA7CisgIGly
LmdkYmFyY2ggPSBnZGJhcmNoOwogCiAgIGlmIChyZWNvcmRfZGVidWcgPiAx
KQogICAgIGZwcmludGZfdW5maWx0ZXJlZCAoZ2RiX3N0ZGxvZywgIlByb2Nl
c3MgcmVjb3JkOiBpMzg2X3Byb2Nlc3NfcmVjb3JkICIKQEAgLTMxODksMjIg
KzMyNTksMjIgQEAgaTM4Nl9wcm9jZXNzX3JlY29yZCAoc3RydWN0IGdkYmFy
Y2ggKmdkYgogCSAgcHJlZml4ZXMgfD0gUFJFRklYX0xPQ0s7CiAJICBicmVh
azsKIAljYXNlIDB4MmU6Ci0JICBpci5vdmVycmlkZSA9IEkzODZfQ1NfUkVH
TlVNOworCSAgaXIub3ZlcnJpZGUgPSBYODZfUkVDT1JEX0NTX1JFR05VTTsK
IAkgIGJyZWFrOwogCWNhc2UgMHgzNjoKLQkgIGlyLm92ZXJyaWRlID0gSTM4
Nl9TU19SRUdOVU07CisJICBpci5vdmVycmlkZSA9IFg4Nl9SRUNPUkRfU1Nf
UkVHTlVNOwogCSAgYnJlYWs7CiAJY2FzZSAweDNlOgotCSAgaXIub3ZlcnJp
ZGUgPSBJMzg2X0RTX1JFR05VTTsKKwkgIGlyLm92ZXJyaWRlID0gWDg2X1JF
Q09SRF9EU19SRUdOVU07CiAJICBicmVhazsKIAljYXNlIDB4MjY6Ci0JICBp
ci5vdmVycmlkZSA9IEkzODZfRVNfUkVHTlVNOworCSAgaXIub3ZlcnJpZGUg
PSBYODZfUkVDT1JEX0VTX1JFR05VTTsKIAkgIGJyZWFrOwogCWNhc2UgMHg2
NDoKLQkgIGlyLm92ZXJyaWRlID0gSTM4Nl9GU19SRUdOVU07CisJICBpci5v
dmVycmlkZSA9IFg4Nl9SRUNPUkRfRlNfUkVHTlVNOwogCSAgYnJlYWs7CiAJ
Y2FzZSAweDY1OgotCSAgaXIub3ZlcnJpZGUgPSBJMzg2X0dTX1JFR05VTTsK
KwkgIGlyLm92ZXJyaWRlID0gWDg2X1JFQ09SRF9HU19SRUdOVU07CiAJICBi
cmVhazsKIAljYXNlIDB4NjY6CiAJICBwcmVmaXhlcyB8PSBQUkVGSVhfREFU
QTsKQEAgLTMyMTIsMTYgKzMyODIsNTEgQEAgaTM4Nl9wcm9jZXNzX3JlY29y
ZCAoc3RydWN0IGdkYmFyY2ggKmdkYgogCWNhc2UgMHg2NzoKIAkgIHByZWZp
eGVzIHw9IFBSRUZJWF9BRERSOwogCSAgYnJlYWs7CisgICAgICAgIGNhc2Ug
MHg0MDoKKyAgICAgICAgY2FzZSAweDQxOgorICAgICAgICBjYXNlIDB4NDI6
CisgICAgICAgIGNhc2UgMHg0MzoKKyAgICAgICAgY2FzZSAweDQ0OgorICAg
ICAgICBjYXNlIDB4NDU6CisgICAgICAgIGNhc2UgMHg0NjoKKyAgICAgICAg
Y2FzZSAweDQ3OgorICAgICAgICBjYXNlIDB4NDg6CisgICAgICAgIGNhc2Ug
MHg0OToKKyAgICAgICAgY2FzZSAweDRhOgorICAgICAgICBjYXNlIDB4NGI6
CisgICAgICAgIGNhc2UgMHg0YzoKKyAgICAgICAgY2FzZSAweDRkOgorICAg
ICAgICBjYXNlIDB4NGU6CisgICAgICAgIGNhc2UgMHg0ZjoKKyAgICAgICAg
ICBpZiAoaXIucmVnbWFwW1g4Nl9SRUNPUkRfUjhfUkVHTlVNXSkKKyAgICAg
ICAgICAgIHsKKyAgICAgICAgICAgICAgIC8qIFJFWCAqLworICAgICAgICAg
ICAgICAgcmV4ID0gMTsKKyAgICAgICAgICAgICAgIHJleF93ID0gKHRtcHU4
ID4+IDMpICYgMTsKKyAgICAgICAgICAgICAgIHJleF9yID0gKHRtcHU4ICYg
MHg0KSA8PCAxOworICAgICAgICAgICAgICAgaXIucmV4X3ggPSAodG1wdTgg
JiAweDIpIDw8IDI7CisgICAgICAgICAgICAgICBpci5yZXhfYiA9ICh0bXB1
OCAmIDB4MSkgPDwgMzsKKyAgICAgICAgICAgIH0KKyAgICAgICAgICBicmVh
azsKIAlkZWZhdWx0OgogCSAgZ290byBvdXRfcHJlZml4ZXM7CiAJICBicmVh
azsKIAl9CiAgICAgfQogb3V0X3ByZWZpeGVzOgotICBpZiAocHJlZml4ZXMg
JiBQUkVGSVhfREFUQSkKLSAgICBpci5kZmxhZyBePSAxOworICBpZiAoaXIu
cmVnbWFwW1g4Nl9SRUNPUkRfUjhfUkVHTlVNXSAmJiByZXhfdyA9PSAxKQor
ICAgIHsKKyAgICAgIGlyLmRmbGFnID0gMjsKKyAgICB9CisgIGVsc2UKKyAg
ICB7CisgICAgICBpZiAocHJlZml4ZXMgJiBQUkVGSVhfREFUQSkKKyAgICAg
ICAgaXIuZGZsYWcgXj0gMTsKKyAgICB9CiAgIGlmIChwcmVmaXhlcyAmIFBS
RUZJWF9BRERSKQogICAgIGlyLmFmbGFnIF49IDE7CisgIGVsc2UgaWYgKGly
LnJlZ21hcFtYODZfUkVDT1JEX1I4X1JFR05VTV0pCisgICAgaXIuYWZsYWcg
PSAyOwogCiAgIC8qIG5vdyBjaGVjayBvcCBjb2RlICovCiAgIG9wY29kZSA9
ICh1aW50MzJfdCkgdG1wdTg7CkBAIC0zMzExLDMwICszNDE2LDI4IEBAIHJl
c3dpdGNoOgogCQl9CiAJICAgICAgZWxzZQogCQl7Ci0JCSAgaWYgKGlyLm90
ID09IE9UX0JZVEUpCisgICAgICAgICAgICAgICAgICBpci5ybSB8PSBpci5y
ZXhfYjsKKwkJICBpZiAoaXIub3QgPT0gT1RfQllURSAmJiAhaXIucmVnbWFw
W1g4Nl9SRUNPUkRfUjhfUkVHTlVNXSkKIAkJICAgIGlyLnJtICY9IDB4MzsK
LQkJICBpZiAocmVjb3JkX2FyY2hfbGlzdF9hZGRfcmVnIChpci5yZWdjYWNo
ZSwgaXIucm0pKQotCQkgICAgcmV0dXJuIC0xOworCQkgIEkzODZfUkVDT1JE
X0FSQ0hfTElTVF9BRERfUkVHIChpci5ybSk7CiAJCX0KIAkgICAgICBicmVh
azsKIAkgICAgICAvKiBPUCBHdiwgRXYgKi8KIAkgICAgY2FzZSAxOgogCSAg
ICAgIGlmIChpMzg2X3JlY29yZF9tb2RybSAoJmlyKSkKIAkJcmV0dXJuIC0x
OwotCSAgICAgIGlmIChpci5vdCA9PSBPVF9CWVRFKQorICAgICAgICAgICAg
ICBpci5yZWcgfD0gcmV4X3I7CisJICAgICAgaWYgKGlyLm90ID09IE9UX0JZ
VEUgJiYgIWlyLnJlZ21hcFtYODZfUkVDT1JEX1I4X1JFR05VTV0pCiAJCWly
LnJlZyAmPSAweDM7Ci0JICAgICAgaWYgKHJlY29yZF9hcmNoX2xpc3RfYWRk
X3JlZyAoaXIucmVnY2FjaGUsIGlyLnJlZykpCi0JCXJldHVybiAtMTsKKwkg
ICAgICBJMzg2X1JFQ09SRF9BUkNIX0xJU1RfQUREX1JFRyAoaXIucmVnKTsK
IAkgICAgICBicmVhazsKIAkgICAgICAvKiBPUCBBLCBJdiAqLwogCSAgICBj
YXNlIDI6Ci0JICAgICAgaWYgKHJlY29yZF9hcmNoX2xpc3RfYWRkX3JlZyAo
aXIucmVnY2FjaGUsIEkzODZfRUFYX1JFR05VTSkpCi0JCXJldHVybiAtMTsK
KwkgICAgICBJMzg2X1JFQ09SRF9BUkNIX0xJU1RfQUREX1JFRyAoWDg2X1JF
Q09SRF9SRUFYX1JFR05VTSk7CiAJICAgICAgYnJlYWs7CiAJICAgIH0KIAl9
Ci0gICAgICBpZiAocmVjb3JkX2FyY2hfbGlzdF9hZGRfcmVnIChpci5yZWdj
YWNoZSwgSTM4Nl9FRkxBR1NfUkVHTlVNKSkKLQlyZXR1cm4gLTE7CisgICAg
ICBJMzg2X1JFQ09SRF9BUkNIX0xJU1RfQUREX1JFRyAoWDg2X1JFQ09SRF9F
RkxBR1NfUkVHTlVNKTsKICAgICAgIGJyZWFrOwogCiAgICAgICAvKiBHUlAx
ICovCkBAIC0zMzU0LDE3ICszNDU3LDE3IEBAIHJlc3dpdGNoOgogCiAJICBp
ZiAoaXIubW9kICE9IDMpCiAJICAgIHsKKyAgICAgICAgICAgICAgaWYgKG9w
Y29kZSA9PSAweDgzKQorICAgICAgICAgICAgICAgIGlyLnJpcF9vZmZzZXQg
PSAxOworICAgICAgICAgICAgICBlbHNlCisgICAgICAgICAgICAgICAgaXIu
cmlwX29mZnNldCA9IChpci5vdCA+IE9UX0xPTkcpID8gNCA6ICgxIDw8IGly
Lm90KTsKIAkgICAgICBpZiAoaTM4Nl9yZWNvcmRfbGVhX21vZHJtICgmaXIp
KQogCQlyZXR1cm4gLTE7CiAJICAgIH0KIAkgIGVsc2UKLQkgICAgewotCSAg
ICAgIGlmIChyZWNvcmRfYXJjaF9saXN0X2FkZF9yZWcgKGlyLnJlZ2NhY2hl
LCBpci5ybSkpCi0JCXJldHVybiAtMTsKLQkgICAgfQorCSAgICBJMzg2X1JF
Q09SRF9BUkNIX0xJU1RfQUREX1JFRyAoaXIucm0gfCBpci5yZXhfYik7CiAJ
fQotICAgICAgaWYgKHJlY29yZF9hcmNoX2xpc3RfYWRkX3JlZyAoaXIucmVn
Y2FjaGUsIEkzODZfRUZMQUdTX1JFR05VTSkpCi0JcmV0dXJuIC0xOworICAg
ICAgSTM4Nl9SRUNPUkRfQVJDSF9MSVNUX0FERF9SRUcgKFg4Nl9SRUNPUkRf
RUZMQUdTX1JFR05VTSk7CiAgICAgICBicmVhazsKIAogICAgICAgLyogaW52
ICovCkBAIC0zMzg1LDEwICszNDg4LDggQEAgcmVzd2l0Y2g6CiAgICAgY2Fz
ZSAweDRkOgogICAgIGNhc2UgMHg0ZToKICAgICBjYXNlIDB4NGY6Ci0gICAg
ICBpZiAocmVjb3JkX2FyY2hfbGlzdF9hZGRfcmVnIChpci5yZWdjYWNoZSwg
b3Bjb2RlICYgNykpCi0JcmV0dXJuIC0xOwotICAgICAgaWYgKHJlY29yZF9h
cmNoX2xpc3RfYWRkX3JlZyAoaXIucmVnY2FjaGUsIEkzODZfRUZMQUdTX1JF
R05VTSkpCi0JcmV0dXJuIC0xOworICAgICAgSTM4Nl9SRUNPUkRfQVJDSF9M
SVNUX0FERF9SRUcgKG9wY29kZSAmIDcpOworICAgICAgSTM4Nl9SRUNPUkRf
QVJDSF9MSVNUX0FERF9SRUcgKFg4Nl9SRUNPUkRfRUZMQUdTX1JFR05VTSk7
CiAgICAgICBicmVhazsKIAogICAgICAgLyogR1JQMyAqLwpAQCAtMzQwMSwy
OCArMzUwMiwxNyBAQCByZXN3aXRjaDoKICAgICAgIGlmIChpMzg2X3JlY29y
ZF9tb2RybSAoJmlyKSkKIAlyZXR1cm4gLTE7CiAKKyAgICAgIGlmIChpci5t
b2QgIT0gMyAmJiBpci5yZWcgPT0gMCkKKyAgICAgICAgaXIucmlwX29mZnNl
dCA9IChpci5vdCA+IE9UX0xPTkcpID8gNCA6ICgxIDw8IGlyLm90KTsKKwog
ICAgICAgc3dpdGNoIChpci5yZWcpCiAJewogCSAgLyogdGVzdCAqLwogCWNh
c2UgMDoKLQkgIGlmIChyZWNvcmRfYXJjaF9saXN0X2FkZF9yZWcgKGlyLnJl
Z2NhY2hlLCBJMzg2X0VGTEFHU19SRUdOVU0pKQotCSAgICByZXR1cm4gLTE7
CisJICBJMzg2X1JFQ09SRF9BUkNIX0xJU1RfQUREX1JFRyAoWDg2X1JFQ09S
RF9FRkxBR1NfUkVHTlVNKTsKIAkgIGJyZWFrOwogCSAgLyogbm90ICovCiAJ
Y2FzZSAyOgotCSAgaWYgKGlyLm1vZCAhPSAzKQotCSAgICB7Ci0JICAgICAg
aWYgKGkzODZfcmVjb3JkX2xlYV9tb2RybSAoJmlyKSkKLQkJcmV0dXJuIC0x
OwotCSAgICB9Ci0JICBlbHNlCi0JICAgIHsKLQkgICAgICBpZiAoaXIub3Qg
PT0gT1RfQllURSkKLQkJaXIucm0gJj0gMHgzOwotCSAgICAgIGlmIChyZWNv
cmRfYXJjaF9saXN0X2FkZF9yZWcgKGlyLnJlZ2NhY2hlLCBpci5ybSkpCi0J
CXJldHVybiAtMTsKLQkgICAgfQotCSAgYnJlYWs7CiAJICAvKiBuZWcgKi8K
IAljYXNlIDM6CiAJICBpZiAoaXIubW9kICE9IDMpCkBAIC0zNDMyLDEzICsz
NTIyLDE0IEBAIHJlc3dpdGNoOgogCSAgICB9CiAJICBlbHNlCiAJICAgIHsK
LQkgICAgICBpZiAoaXIub3QgPT0gT1RfQllURSkKKyAgICAgICAgICAgICAg
aXIucm0gfD0gaXIucmV4X2I7CisJICAgICAgaWYgKGlyLm90ID09IE9UX0JZ
VEUgJiYgIWlyLnJlZ21hcFtYODZfUkVDT1JEX1I4X1JFR05VTV0pCiAJCWly
LnJtICY9IDB4MzsKLQkgICAgICBpZiAocmVjb3JkX2FyY2hfbGlzdF9hZGRf
cmVnIChpci5yZWdjYWNoZSwgaXIucm0pKQotCQlyZXR1cm4gLTE7CisJICAg
ICAgSTM4Nl9SRUNPUkRfQVJDSF9MSVNUX0FERF9SRUcgKGlyLnJtKTsKIAkg
ICAgfQotCSAgaWYgKHJlY29yZF9hcmNoX2xpc3RfYWRkX3JlZyAoaXIucmVn
Y2FjaGUsIEkzODZfRUZMQUdTX1JFR05VTSkpCi0JICAgIHJldHVybiAtMTsK
KwkgIC8qIG5lZyAqLworCSAgaWYgKGlyLnJlZyA9PSAzKQorCSAgICBJMzg2
X1JFQ09SRF9BUkNIX0xJU1RfQUREX1JFRyAoWDg2X1JFQ09SRF9FRkxBR1Nf
UkVHTlVNKTsKIAkgIGJyZWFrOwogCSAgLyogbXVsICovCiAJY2FzZSA0OgpA
QCAtMzQ0OCwxNSArMzUzOSwxMCBAQCByZXN3aXRjaDoKIAljYXNlIDY6CiAJ
ICAvKiBpZGl2ICovCiAJY2FzZSA3OgotCSAgaWYgKHJlY29yZF9hcmNoX2xp
c3RfYWRkX3JlZyAoaXIucmVnY2FjaGUsIEkzODZfRUFYX1JFR05VTSkpCi0J
ICAgIHJldHVybiAtMTsKKwkgIEkzODZfUkVDT1JEX0FSQ0hfTElTVF9BRERf
UkVHIChYODZfUkVDT1JEX1JFQVhfUkVHTlVNKTsKIAkgIGlmIChpci5vdCAh
PSBPVF9CWVRFKQotCSAgICB7Ci0JICAgICAgaWYgKHJlY29yZF9hcmNoX2xp
c3RfYWRkX3JlZyAoaXIucmVnY2FjaGUsIEkzODZfRURYX1JFR05VTSkpCi0J
CXJldHVybiAtMTsKLQkgICAgfQotCSAgaWYgKHJlY29yZF9hcmNoX2xpc3Rf
YWRkX3JlZyAoaXIucmVnY2FjaGUsIEkzODZfRUZMQUdTX1JFR05VTSkpCi0J
ICAgIHJldHVybiAtMTsKKwkgICAgSTM4Nl9SRUNPUkRfQVJDSF9MSVNUX0FE
RF9SRUcgKFg4Nl9SRUNPUkRfUkVEWF9SRUdOVU0pOworCSAgSTM4Nl9SRUNP
UkRfQVJDSF9MSVNUX0FERF9SRUcgKFg4Nl9SRUNPUkRfRUZMQUdTX1JFR05V
TSk7CiAJICBicmVhazsKIAlkZWZhdWx0OgogCSAgaXIuYWRkciAtPSAyOwpA
QCAtMzQ3MCwxMCArMzU1Niw2IEBAIHJlc3dpdGNoOgogICAgIGNhc2UgMHhm
ZToKICAgICAgIC8qIEdSUDUgKi8KICAgICBjYXNlIDB4ZmY6Ci0gICAgICBp
ZiAoKG9wY29kZSAmIDEpID09IDApCi0JaXIub3QgPSBPVF9CWVRFOwotICAg
ICAgZWxzZQotCWlyLm90ID0gaXIuZGZsYWcgKyBPVF9XT1JEOwogICAgICAg
aWYgKGkzODZfcmVjb3JkX21vZHJtICgmaXIpKQogCXJldHVybiAtMTsKICAg
ICAgIGlmIChpci5yZWcgPj0gMiAmJiBvcGNvZGUgPT0gMHhmZSkKQEAgLTM0
ODIsMTMgKzM1NjQsMTYgQEAgcmVzd2l0Y2g6CiAJICBvcGNvZGUgPSBvcGNv
ZGUgPDwgOCB8IGlyLm1vZHJtOwogCSAgZ290byBub19zdXBwb3J0OwogCX0K
LQogICAgICAgc3dpdGNoIChpci5yZWcpCiAJewogCSAgLyogaW5jICovCiAJ
Y2FzZSAwOgogCSAgLyogZGVjICovCiAJY2FzZSAxOgorICAgICAgICAgIGlm
ICgob3Bjb2RlICYgMSkgPT0gMCkKKwkgICAgaXIub3QgPSBPVF9CWVRFOwor
ICAgICAgICAgIGVsc2UKKwkgICAgaXIub3QgPSBpci5kZmxhZyArIE9UX1dP
UkQ7CiAJICBpZiAoaXIubW9kICE9IDMpCiAJICAgIHsKIAkgICAgICBpZiAo
aTM4Nl9yZWNvcmRfbGVhX21vZHJtICgmaXIpKQpAQCAtMzQ5Niw0MiArMzU4
MSw0MCBAQCByZXN3aXRjaDoKIAkgICAgfQogCSAgZWxzZQogCSAgICB7Ci0J
ICAgICAgaWYgKGlyLm90ID09IE9UX0JZVEUpCisJICAgICAgaXIucm0gfD0g
aXIucmV4X2I7CisJICAgICAgaWYgKGlyLm90ID09IE9UX0JZVEUgJiYgIWly
LnJlZ21hcFtYODZfUkVDT1JEX1I4X1JFR05VTV0pCiAJCWlyLnJtICY9IDB4
MzsKLQkgICAgICBpZiAocmVjb3JkX2FyY2hfbGlzdF9hZGRfcmVnIChpci5y
ZWdjYWNoZSwgaXIucm0pKQotCQlyZXR1cm4gLTE7CisJICAgICAgSTM4Nl9S
RUNPUkRfQVJDSF9MSVNUX0FERF9SRUcgKGlyLnJtKTsKIAkgICAgfQotCSAg
aWYgKHJlY29yZF9hcmNoX2xpc3RfYWRkX3JlZyAoaXIucmVnY2FjaGUsIEkz
ODZfRUZMQUdTX1JFR05VTSkpCi0JICAgIHJldHVybiAtMTsKKwkgIEkzODZf
UkVDT1JEX0FSQ0hfTElTVF9BRERfUkVHIChYODZfUkVDT1JEX0VGTEFHU19S
RUdOVU0pOwogCSAgYnJlYWs7CiAJICAvKiBjYWxsICovCiAJY2FzZSAyOgot
CSAgLyogcHVzaCAqLwotCWNhc2UgNjoKLQkgIGlmIChyZWNvcmRfYXJjaF9s
aXN0X2FkZF9yZWcgKGlyLnJlZ2NhY2hlLCBJMzg2X0VTUF9SRUdOVU0pKQot
CSAgICByZXR1cm4gLTE7Ci0JICByZWdjYWNoZV9yYXdfcmVhZCAoaXIucmVn
Y2FjaGUsIEkzODZfRVNQX1JFR05VTSwKLQkJCSAgICAgKGdkYl9ieXRlICop
ICYgdG1wdTMyKTsKLQkgIGlmIChyZWNvcmRfYXJjaF9saXN0X2FkZF9tZW0K
LQkgICAgICAoKENPUkVfQUREUikgdG1wdTMyIC0gKDEgPDwgKGlyLmRmbGFn
ICsgMSkpLCAoMSA8PCAoaXIuZGZsYWcgKyAxKSkpKQorICAgICAgICAgIGlm
IChpci5yZWdtYXBbWDg2X1JFQ09SRF9SOF9SRUdOVU1dICYmIGlyLmRmbGFn
KQorICAgICAgICAgICAgaXIuZGZsYWcgPSAyOworCSAgaWYgKGkzODZfcmVj
b3JkX3B1c2ggKCZpciwgMSA8PCAoaXIuZGZsYWcgKyAxKSkpCiAJICAgIHJl
dHVybiAtMTsKKwkgIEkzODZfUkVDT1JEX0FSQ0hfTElTVF9BRERfUkVHIChY
ODZfUkVDT1JEX0VGTEFHU19SRUdOVU0pOwogCSAgYnJlYWs7CiAJICAvKiBs
Y2FsbCAqLwogCWNhc2UgMzoKLQkgIGlmIChyZWNvcmRfYXJjaF9saXN0X2Fk
ZF9yZWcgKGlyLnJlZ2NhY2hlLCBJMzg2X0VTUF9SRUdOVU0pKQotCSAgICBy
ZXR1cm4gLTE7Ci0JICBpZiAocmVjb3JkX2FyY2hfbGlzdF9hZGRfcmVnIChp
ci5yZWdjYWNoZSwgSTM4Nl9DU19SRUdOVU0pKQotCSAgICByZXR1cm4gLTE7
Ci0JICByZWdjYWNoZV9yYXdfcmVhZCAoaXIucmVnY2FjaGUsIEkzODZfRVNQ
X1JFR05VTSwKLQkJCSAgICAgKGdkYl9ieXRlICopICYgdG1wdTMyKTsKLQkg
IGlmIChyZWNvcmRfYXJjaF9saXN0X2FkZF9tZW0KLQkgICAgICAoKENPUkVf
QUREUikgdG1wdTMyIC0gKDEgPDwgKGlyLmRmbGFnICsgMikpLCAoMSA8PCAo
aXIuZGZsYWcgKyAyKSkpKQorCSAgSTM4Nl9SRUNPUkRfQVJDSF9MSVNUX0FE
RF9SRUcgKFg4Nl9SRUNPUkRfQ1NfUkVHTlVNKTsKKwkgIGlmIChpMzg2X3Jl
Y29yZF9wdXNoICgmaXIsIDEgPDwgKGlyLmRmbGFnICsgMikpKQogCSAgICBy
ZXR1cm4gLTE7CisJICBJMzg2X1JFQ09SRF9BUkNIX0xJU1RfQUREX1JFRyAo
WDg2X1JFQ09SRF9FRkxBR1NfUkVHTlVNKTsKIAkgIGJyZWFrOwogCSAgLyog
am1wICovCiAJY2FzZSA0OgogCSAgLyogbGptcCAqLwogCWNhc2UgNToKKwkg
IEkzODZfUkVDT1JEX0FSQ0hfTElTVF9BRERfUkVHIChYODZfUkVDT1JEX0VG
TEFHU19SRUdOVU0pOworCSAgYnJlYWs7CisJICAvKiBwdXNoICovCisJY2Fz
ZSA2OgorICAgICAgICAgIGlmIChpci5yZWdtYXBbWDg2X1JFQ09SRF9SOF9S
RUdOVU1dICYmIGlyLmRmbGFnKQorICAgICAgICAgICAgaXIuZGZsYWcgPSAy
OworCSAgaWYgKGkzODZfcmVjb3JkX3B1c2ggKCZpciwgMSA8PCAoaXIuZGZs
YWcgKyAxKSkpCisJICAgIHJldHVybiAtMTsKIAkgIGJyZWFrOwogCWRlZmF1
bHQ6CiAJICBpci5hZGRyIC09IDI7CkBAIC0zNTQ2LDIyICszNjI5LDE4IEBA
IHJlc3dpdGNoOgogICAgIGNhc2UgMHg4NToKICAgICBjYXNlIDB4YTg6CiAg
ICAgY2FzZSAweGE5OgotICAgICAgaWYgKHJlY29yZF9hcmNoX2xpc3RfYWRk
X3JlZyAoaXIucmVnY2FjaGUsIEkzODZfRUZMQUdTX1JFR05VTSkpCi0JcmV0
dXJuIC0xOworICAgICAgSTM4Nl9SRUNPUkRfQVJDSF9MSVNUX0FERF9SRUcg
KFg4Nl9SRUNPUkRfRUZMQUdTX1JFR05VTSk7CiAgICAgICBicmVhazsKIAog
ICAgICAgLyogQ1dERS9DQlcgKi8KICAgICBjYXNlIDB4OTg6Ci0gICAgICBp
ZiAocmVjb3JkX2FyY2hfbGlzdF9hZGRfcmVnIChpci5yZWdjYWNoZSwgSTM4
Nl9FQVhfUkVHTlVNKSkKLQlyZXR1cm4gLTE7CisgICAgICBJMzg2X1JFQ09S
RF9BUkNIX0xJU1RfQUREX1JFRyAoWDg2X1JFQ09SRF9SRUFYX1JFR05VTSk7
CiAgICAgICBicmVhazsKIAogICAgICAgLyogQ0RRL0NXRCAqLwogICAgIGNh
c2UgMHg5OToKLSAgICAgIGlmIChyZWNvcmRfYXJjaF9saXN0X2FkZF9yZWcg
KGlyLnJlZ2NhY2hlLCBJMzg2X0VBWF9SRUdOVU0pKQotCXJldHVybiAtMTsK
LSAgICAgIGlmIChyZWNvcmRfYXJjaF9saXN0X2FkZF9yZWcgKGlyLnJlZ2Nh
Y2hlLCBJMzg2X0VEWF9SRUdOVU0pKQotCXJldHVybiAtMTsKKyAgICAgIEkz
ODZfUkVDT1JEX0FSQ0hfTElTVF9BRERfUkVHIChYODZfUkVDT1JEX1JFQVhf
UkVHTlVNKTsKKyAgICAgIEkzODZfUkVDT1JEX0FSQ0hfTElTVF9BRERfUkVH
IChYODZfUkVDT1JEX1JFRFhfUkVHTlVNKTsKICAgICAgIGJyZWFrOwogCiAg
ICAgICAvKiBpbXVsICovCkBAIC0zNTcxLDEyICszNjUwLDE1IEBAIHJlc3dp
dGNoOgogICAgICAgaXIub3QgPSBpci5kZmxhZyArIE9UX1dPUkQ7CiAgICAg
ICBpZiAoaTM4Nl9yZWNvcmRfbW9kcm0gKCZpcikpCiAJcmV0dXJuIC0xOwot
ICAgICAgaWYgKGlyLm90ID09IE9UX0JZVEUpCisgICAgICBpZiAob3Bjb2Rl
ID09IDB4NjkpCisgICAgICAgIGlyLnJpcF9vZmZzZXQgPSAoaXIub3QgPiBP
VF9MT05HKSA/IDQgOiAoMSA8PCBpci5vdCk7CisgICAgICBlbHNlIGlmIChv
cGNvZGUgPT0gMHg2YikKKyAgICAgICAgaXIucmlwX29mZnNldCA9IDE7Cisg
ICAgICBpci5yZWcgfD0gcmV4X3I7CisgICAgICBpZiAoaXIub3QgPT0gT1Rf
QllURSAmJiAhaXIucmVnbWFwW1g4Nl9SRUNPUkRfUjhfUkVHTlVNXSkKIAlp
ci5yZWcgJj0gMHgzOwotICAgICAgaWYgKHJlY29yZF9hcmNoX2xpc3RfYWRk
X3JlZyAoaXIucmVnY2FjaGUsIGlyLnJlZykpCi0JcmV0dXJuIC0xOwotICAg
ICAgaWYgKHJlY29yZF9hcmNoX2xpc3RfYWRkX3JlZyAoaXIucmVnY2FjaGUs
IEkzODZfRUZMQUdTX1JFR05VTSkpCi0JcmV0dXJuIC0xOworICAgICAgSTM4
Nl9SRUNPUkRfQVJDSF9MSVNUX0FERF9SRUcgKGlyLnJlZyk7CisgICAgICBJ
Mzg2X1JFQ09SRF9BUkNIX0xJU1RfQUREX1JFRyAoWDg2X1JFQ09SRF9FRkxB
R1NfUkVHTlVNKTsKICAgICAgIGJyZWFrOwogCiAgICAgICAvKiB4YWRkICov
CkBAIC0zNTg4LDI4ICszNjcwLDI1IEBAIHJlc3dpdGNoOgogCWlyLm90ID0g
aXIuZGZsYWcgKyBPVF9XT1JEOwogICAgICAgaWYgKGkzODZfcmVjb3JkX21v
ZHJtICgmaXIpKQogCXJldHVybiAtMTsKKyAgICAgIGlyLnJlZyB8PSByZXhf
cjsKICAgICAgIGlmIChpci5tb2QgPT0gMykKIAl7Ci0JICBpZiAoaXIub3Qg
PT0gT1RfQllURSkKKwkgIGlmIChpci5vdCA9PSBPVF9CWVRFICYmICFpci5y
ZWdtYXBbWDg2X1JFQ09SRF9SOF9SRUdOVU1dKQogCSAgICBpci5yZWcgJj0g
MHgzOwotCSAgaWYgKHJlY29yZF9hcmNoX2xpc3RfYWRkX3JlZyAoaXIucmVn
Y2FjaGUsIGlyLnJlZykpCi0JICAgIHJldHVybiAtMTsKLQkgIGlmIChpci5v
dCA9PSBPVF9CWVRFKQorCSAgSTM4Nl9SRUNPUkRfQVJDSF9MSVNUX0FERF9S
RUcgKGlyLnJlZyk7CisJICBpZiAoaXIub3QgPT0gT1RfQllURSAmJiAhaXIu
cmVnbWFwW1g4Nl9SRUNPUkRfUjhfUkVHTlVNXSkKIAkgICAgaXIucm0gJj0g
MHgzOwotCSAgaWYgKHJlY29yZF9hcmNoX2xpc3RfYWRkX3JlZyAoaXIucmVn
Y2FjaGUsIGlyLnJtKSkKLQkgICAgcmV0dXJuIC0xOworCSAgSTM4Nl9SRUNP
UkRfQVJDSF9MSVNUX0FERF9SRUcgKGlyLnJtKTsKIAl9CiAgICAgICBlbHNl
CiAJewogCSAgaWYgKGkzODZfcmVjb3JkX2xlYV9tb2RybSAoJmlyKSkKIAkg
ICAgcmV0dXJuIC0xOwotCSAgaWYgKGlyLm90ID09IE9UX0JZVEUpCisJICBp
ZiAoaXIub3QgPT0gT1RfQllURSAmJiAhaXIucmVnbWFwW1g4Nl9SRUNPUkRf
UjhfUkVHTlVNXSkKIAkgICAgaXIucmVnICY9IDB4MzsKLQkgIGlmIChyZWNv
cmRfYXJjaF9saXN0X2FkZF9yZWcgKGlyLnJlZ2NhY2hlLCBpci5yZWcpKQot
CSAgICByZXR1cm4gLTE7CisJICBJMzg2X1JFQ09SRF9BUkNIX0xJU1RfQURE
X1JFRyAoaXIucmVnKTsKIAl9Ci0gICAgICBpZiAocmVjb3JkX2FyY2hfbGlz
dF9hZGRfcmVnIChpci5yZWdjYWNoZSwgSTM4Nl9FRkxBR1NfUkVHTlVNKSkK
LQlyZXR1cm4gLTE7CisgICAgICBJMzg2X1JFQ09SRF9BUkNIX0xJU1RfQURE
X1JFRyAoWDg2X1JFQ09SRF9FRkxBR1NfUkVHTlVNKTsKICAgICAgIGJyZWFr
OwogCiAgICAgICAvKiBjbXB4Y2hnICovCkBAIC0zNjIzLDIyICszNzAyLDE5
IEBAIHJlc3dpdGNoOgogCXJldHVybiAtMTsKICAgICAgIGlmIChpci5tb2Qg
PT0gMykKIAl7Ci0JICBpZiAocmVjb3JkX2FyY2hfbGlzdF9hZGRfcmVnIChp
ci5yZWdjYWNoZSwgSTM4Nl9FQVhfUkVHTlVNKSkKLQkgICAgcmV0dXJuIC0x
OwotCSAgaWYgKGlyLm90ID09IE9UX0JZVEUpCisgICAgICAgICAgaXIucmVn
IHw9IHJleF9yOworCSAgSTM4Nl9SRUNPUkRfQVJDSF9MSVNUX0FERF9SRUcg
KFg4Nl9SRUNPUkRfUkVBWF9SRUdOVU0pOworCSAgaWYgKGlyLm90ID09IE9U
X0JZVEUgJiYgIWlyLnJlZ21hcFtYODZfUkVDT1JEX1I4X1JFR05VTV0pCiAJ
ICAgIGlyLnJlZyAmPSAweDM7Ci0JICBpZiAocmVjb3JkX2FyY2hfbGlzdF9h
ZGRfcmVnIChpci5yZWdjYWNoZSwgaXIucmVnKSkKLQkgICAgcmV0dXJuIC0x
OworCSAgSTM4Nl9SRUNPUkRfQVJDSF9MSVNUX0FERF9SRUcgKGlyLnJlZyk7
CiAJfQogICAgICAgZWxzZQogCXsKLQkgIGlmIChyZWNvcmRfYXJjaF9saXN0
X2FkZF9yZWcgKGlyLnJlZ2NhY2hlLCBJMzg2X0VBWF9SRUdOVU0pKQotCSAg
ICByZXR1cm4gLTE7CisJICBJMzg2X1JFQ09SRF9BUkNIX0xJU1RfQUREX1JF
RyAoWDg2X1JFQ09SRF9SRUFYX1JFR05VTSk7CiAJICBpZiAoaTM4Nl9yZWNv
cmRfbGVhX21vZHJtICgmaXIpKQogCSAgICByZXR1cm4gLTE7CiAJfQotICAg
ICAgaWYgKHJlY29yZF9hcmNoX2xpc3RfYWRkX3JlZyAoaXIucmVnY2FjaGUs
IEkzODZfRUZMQUdTX1JFR05VTSkpCi0JcmV0dXJuIC0xOworICAgICAgSTM4
Nl9SRUNPUkRfQVJDSF9MSVNUX0FERF9SRUcgKFg4Nl9SRUNPUkRfRUZMQUdT
X1JFR05VTSk7CiAgICAgICBicmVhazsKIAogICAgICAgLyogY21weGNoZzhi
ICovCkBAIC0zNjUxLDE0ICszNzI3LDExIEBAIHJlc3dpdGNoOgogCSAgb3Bj
b2RlID0gb3Bjb2RlIDw8IDggfCBpci5tb2RybTsKIAkgIGdvdG8gbm9fc3Vw
cG9ydDsKIAl9Ci0gICAgICBpZiAocmVjb3JkX2FyY2hfbGlzdF9hZGRfcmVn
IChpci5yZWdjYWNoZSwgSTM4Nl9FQVhfUkVHTlVNKSkKLQlyZXR1cm4gLTE7
Ci0gICAgICBpZiAocmVjb3JkX2FyY2hfbGlzdF9hZGRfcmVnIChpci5yZWdj
YWNoZSwgSTM4Nl9FRFhfUkVHTlVNKSkKLQlyZXR1cm4gLTE7CisgICAgICBJ
Mzg2X1JFQ09SRF9BUkNIX0xJU1RfQUREX1JFRyAoWDg2X1JFQ09SRF9SRUFY
X1JFR05VTSk7CisgICAgICBJMzg2X1JFQ09SRF9BUkNIX0xJU1RfQUREX1JF
RyAoWDg2X1JFQ09SRF9SRURYX1JFR05VTSk7CiAgICAgICBpZiAoaTM4Nl9y
ZWNvcmRfbGVhX21vZHJtICgmaXIpKQogCXJldHVybiAtMTsKLSAgICAgIGlm
IChyZWNvcmRfYXJjaF9saXN0X2FkZF9yZWcgKGlyLnJlZ2NhY2hlLCBJMzg2
X0VGTEFHU19SRUdOVU0pKQotCXJldHVybiAtMTsKKyAgICAgIEkzODZfUkVD
T1JEX0FSQ0hfTElTVF9BRERfUkVHIChYODZfUkVDT1JEX0VGTEFHU19SRUdO
VU0pOwogICAgICAgYnJlYWs7CiAKICAgICAgIC8qIHB1c2ggKi8KQEAgLTM2
NzIsNiArMzc0NSwxMiBAQCByZXN3aXRjaDoKICAgICBjYXNlIDB4NTc6CiAg
ICAgY2FzZSAweDY4OgogICAgIGNhc2UgMHg2YToKKyAgICAgIGlmIChpci5y
ZWdtYXBbWDg2X1JFQ09SRF9SOF9SRUdOVU1dICYmIGlyLmRmbGFnKQorICAg
ICAgICBpci5kZmxhZyA9IDI7CisgICAgICBpZiAoaTM4Nl9yZWNvcmRfcHVz
aCAoJmlyLCAxIDw8IChpci5kZmxhZyArIDEpKSkKKwlyZXR1cm4gLTE7Cisg
ICAgICBicmVhazsKKwogICAgICAgLyogcHVzaCBlcyAqLwogICAgIGNhc2Ug
MHgwNjoKICAgICAgIC8qIHB1c2ggY3MgKi8KQEAgLTM2ODAsMTYgKzM3NTks
MzYgQEAgcmVzd2l0Y2g6CiAgICAgY2FzZSAweDE2OgogICAgICAgLyogcHVz
aCBkcyAqLwogICAgIGNhc2UgMHgxZToKKyAgICAgIGlmIChpci5yZWdtYXBb
WDg2X1JFQ09SRF9SOF9SRUdOVU1dKQorICAgICAgICB7CisJICBpci5hZGRy
IC09IDE7CisJICBnb3RvIG5vX3N1cHBvcnQ7CisJfQorICAgICAgaWYgKGkz
ODZfcmVjb3JkX3B1c2ggKCZpciwgMSA8PCAoaXIuZGZsYWcgKyAxKSkpCisJ
cmV0dXJuIC0xOworICAgICAgYnJlYWs7CisKICAgICAgIC8qIHB1c2ggZnMg
Ki8KICAgICBjYXNlIDB4MGZhMDoKICAgICAgIC8qIHB1c2ggZ3MgKi8KICAg
ICBjYXNlIDB4MGZhODoKLSAgICAgIGlmIChyZWNvcmRfYXJjaF9saXN0X2Fk
ZF9yZWcgKGlyLnJlZ2NhY2hlLCBJMzg2X0VTUF9SRUdOVU0pKQorICAgICAg
aWYgKGlyLnJlZ21hcFtYODZfUkVDT1JEX1I4X1JFR05VTV0pCisgICAgICAg
IHsKKwkgIGlyLmFkZHIgLT0gMjsKKwkgIGdvdG8gbm9fc3VwcG9ydDsKKwl9
CisgICAgICBpZiAoaTM4Nl9yZWNvcmRfcHVzaCAoJmlyLCAxIDw8IChpci5k
ZmxhZyArIDEpKSkKIAlyZXR1cm4gLTE7Ci0gICAgICByZWdjYWNoZV9yYXdf
cmVhZCAoaXIucmVnY2FjaGUsIEkzODZfRVNQX1JFR05VTSwKLQkJCSAoZ2Ri
X2J5dGUgKikgJiB0bXB1MzIpOwotICAgICAgaWYgKHJlY29yZF9hcmNoX2xp
c3RfYWRkX21lbQotCSAgKChDT1JFX0FERFIpIHRtcHUzMiAtICgxIDw8IChp
ci5kZmxhZyArIDEpKSwgKDEgPDwgKGlyLmRmbGFnICsgMSkpKSkKKyAgICAg
IGJyZWFrOworCisgICAgICAvKiBwdXNoYSAqLworICAgIGNhc2UgMHg2MDoK
KyAgICAgIGlmIChpci5yZWdtYXBbWDg2X1JFQ09SRF9SOF9SRUdOVU1dKQor
ICAgICAgICB7CisJICBpci5hZGRyIC09IDE7CisJICBnb3RvIG5vX3N1cHBv
cnQ7CisJfQorICAgICAgaWYgKGkzODZfcmVjb3JkX3B1c2ggKCZpciwgMSA8
PCAoaXIuZGZsYWcgKyA0KSkpCiAJcmV0dXJuIC0xOwogICAgICAgYnJlYWs7
CiAKQEAgLTM3MDIsMTEzICszODAxLDEwMyBAQCByZXN3aXRjaDoKICAgICBj
YXNlIDB4NWQ6CiAgICAgY2FzZSAweDVlOgogICAgIGNhc2UgMHg1ZjoKLSAg
ICAgIGlyLm90ID0gaXIuZGZsYWcgKyBPVF9XT1JEOwotICAgICAgaWYgKHJl
Y29yZF9hcmNoX2xpc3RfYWRkX3JlZyAoaXIucmVnY2FjaGUsIEkzODZfRVNQ
X1JFR05VTSkpCi0JcmV0dXJuIC0xOwotICAgICAgaWYgKGlyLm90ID09IE9U
X0JZVEUpCi0Jb3Bjb2RlICY9IDB4MzsKLSAgICAgIGlmIChyZWNvcmRfYXJj
aF9saXN0X2FkZF9yZWcgKGlyLnJlZ2NhY2hlLCBvcGNvZGUgJiAweDcpKQot
CXJldHVybiAtMTsKLSAgICAgIGJyZWFrOwotCi0gICAgICAvKiBwdXNoYSAq
LwotICAgIGNhc2UgMHg2MDoKLSAgICAgIGlmIChyZWNvcmRfYXJjaF9saXN0
X2FkZF9yZWcgKGlyLnJlZ2NhY2hlLCBJMzg2X0VTUF9SRUdOVU0pKQotCXJl
dHVybiAtMTsKLSAgICAgIHJlZ2NhY2hlX3Jhd19yZWFkIChpci5yZWdjYWNo
ZSwgSTM4Nl9FU1BfUkVHTlVNLAotCQkJIChnZGJfYnl0ZSAqKSAmIHRtcHUz
Mik7Ci0gICAgICBpZiAocmVjb3JkX2FyY2hfbGlzdF9hZGRfbWVtCi0JICAo
KENPUkVfQUREUikgdG1wdTMyIC0gKDEgPDwgKGlyLmRmbGFnICsgNCkpLCAo
MSA8PCAoaXIuZGZsYWcgKyA0KSkpKQotCXJldHVybiAtMTsKKyAgICAgIEkz
ODZfUkVDT1JEX0FSQ0hfTElTVF9BRERfUkVHIChYODZfUkVDT1JEX1JFU1Bf
UkVHTlVNKTsKKyAgICAgIEkzODZfUkVDT1JEX0FSQ0hfTElTVF9BRERfUkVH
ICgob3Bjb2RlICYgMHg3KSB8IGlyLnJleF9iKTsKICAgICAgIGJyZWFrOwog
CiAgICAgICAvKiBwb3BhICovCiAgICAgY2FzZSAweDYxOgotICAgICAgZm9y
ICh0bXB1OCA9IEkzODZfRUFYX1JFR05VTTsgdG1wdTggPD0gSTM4Nl9FRElf
UkVHTlVNOyB0bXB1OCsrKQotCXsKLQkgIGlmIChyZWNvcmRfYXJjaF9saXN0
X2FkZF9yZWcgKGlyLnJlZ2NhY2hlLCB0bXB1OCkpCi0JICAgIHJldHVybiAt
MTsKKyAgICAgIGlmIChpci5yZWdtYXBbWDg2X1JFQ09SRF9SOF9SRUdOVU1d
KQorICAgICAgICB7CisJICBpci5hZGRyIC09IDE7CisJICBnb3RvIG5vX3N1
cHBvcnQ7CiAJfQorICAgICAgZm9yICh0bXB1OCA9IFg4Nl9SRUNPUkRfUkVB
WF9SRUdOVU07IHRtcHU4IDw9IFg4Nl9SRUNPUkRfUkVESV9SRUdOVU07CisJ
ICAgdG1wdTgrKykKKwlJMzg2X1JFQ09SRF9BUkNIX0xJU1RfQUREX1JFRyAo
dG1wdTgpOwogICAgICAgYnJlYWs7CiAKICAgICAgIC8qIHBvcCAqLwogICAg
IGNhc2UgMHg4ZjoKLSAgICAgIGlyLm90ID0gaXIuZGZsYWcgKyBPVF9XT1JE
OworICAgICAgaWYgKGlyLnJlZ21hcFtYODZfUkVDT1JEX1I4X1JFR05VTV0p
CisJaXIub3QgPSBpci5kZmxhZyA/IE9UX1FVQUQgOiBPVF9XT1JEOworICAg
ICAgZWxzZQorICAgICAgICBpci5vdCA9IGlyLmRmbGFnICsgT1RfV09SRDsK
ICAgICAgIGlmIChpMzg2X3JlY29yZF9tb2RybSAoJmlyKSkKIAlyZXR1cm4g
LTE7CiAgICAgICBpZiAoaXIubW9kID09IDMpCi0JewotCSAgaWYgKHJlY29y
ZF9hcmNoX2xpc3RfYWRkX3JlZyAoaXIucmVnY2FjaGUsIGlyLnJtKSkKLQkg
ICAgcmV0dXJuIC0xOwotCX0KKwlJMzg2X1JFQ09SRF9BUkNIX0xJU1RfQURE
X1JFRyAoaXIucm0gfCBpci5yZXhfYik7CiAgICAgICBlbHNlCiAJewogCSAg
aWYgKGkzODZfcmVjb3JkX2xlYV9tb2RybSAoJmlyKSkKIAkgICAgcmV0dXJu
IC0xOwogCX0KLSAgICAgIGlmIChyZWNvcmRfYXJjaF9saXN0X2FkZF9yZWcg
KGlyLnJlZ2NhY2hlLCBJMzg2X0VTUF9SRUdOVU0pKQotCXJldHVybiAtMTsK
KyAgICAgIEkzODZfUkVDT1JEX0FSQ0hfTElTVF9BRERfUkVHIChYODZfUkVD
T1JEX1JFU1BfUkVHTlVNKTsKICAgICAgIGJyZWFrOwogCiAgICAgICAvKiBl
bnRlciAqLwogICAgIGNhc2UgMHhjODoKLSAgICAgIGlmIChyZWNvcmRfYXJj
aF9saXN0X2FkZF9yZWcgKGlyLnJlZ2NhY2hlLCBJMzg2X0VTUF9SRUdOVU0p
KQotCXJldHVybiAtMTsKLSAgICAgIGlmIChyZWNvcmRfYXJjaF9saXN0X2Fk
ZF9yZWcgKGlyLnJlZ2NhY2hlLCBJMzg2X0VCUF9SRUdOVU0pKQotCXJldHVy
biAtMTsKLSAgICAgIHJlZ2NhY2hlX3Jhd19yZWFkIChpci5yZWdjYWNoZSwg
STM4Nl9FU1BfUkVHTlVNLAotCQkJIChnZGJfYnl0ZSAqKSAmIHRtcHUzMik7
Ci0gICAgICBpZiAocmVjb3JkX2FyY2hfbGlzdF9hZGRfbWVtCi0JICAoKENP
UkVfQUREUikgdG1wdTMyIC0gKDEgPDwgKGlyLmRmbGFnICsgMSkpLCAoMSA8
PCAoaXIuZGZsYWcgKyAxKSkpKQorICAgICAgSTM4Nl9SRUNPUkRfQVJDSF9M
SVNUX0FERF9SRUcgKFg4Nl9SRUNPUkRfUkVCUF9SRUdOVU0pOworICAgICAg
aWYgKGlyLnJlZ21hcFtYODZfUkVDT1JEX1I4X1JFR05VTV0gJiYgaXIuZGZs
YWcpCisgICAgICAgIGlyLmRmbGFnID0gMjsKKyAgICAgIGlmIChpMzg2X3Jl
Y29yZF9wdXNoICgmaXIsIDEgPDwgKGlyLmRmbGFnICsgMSkpKQogCXJldHVy
biAtMTsKICAgICAgIGJyZWFrOwogCiAgICAgICAvKiBsZWF2ZSAqLwogICAg
IGNhc2UgMHhjOToKLSAgICAgIGlmIChyZWNvcmRfYXJjaF9saXN0X2FkZF9y
ZWcgKGlyLnJlZ2NhY2hlLCBJMzg2X0VTUF9SRUdOVU0pKQotCXJldHVybiAt
MTsKLSAgICAgIGlmIChyZWNvcmRfYXJjaF9saXN0X2FkZF9yZWcgKGlyLnJl
Z2NhY2hlLCBJMzg2X0VCUF9SRUdOVU0pKQotCXJldHVybiAtMTsKKyAgICAg
IEkzODZfUkVDT1JEX0FSQ0hfTElTVF9BRERfUkVHIChYODZfUkVDT1JEX1JF
U1BfUkVHTlVNKTsKKyAgICAgIEkzODZfUkVDT1JEX0FSQ0hfTElTVF9BRERf
UkVHIChYODZfUkVDT1JEX1JFQlBfUkVHTlVNKTsKICAgICAgIGJyZWFrOwog
CiAgICAgICAvKiBwb3AgZXMgKi8KICAgICBjYXNlIDB4MDc6Ci0gICAgICBp
ZiAocmVjb3JkX2FyY2hfbGlzdF9hZGRfcmVnIChpci5yZWdjYWNoZSwgSTM4
Nl9FU1BfUkVHTlVNKSkKLQlyZXR1cm4gLTE7Ci0gICAgICBpZiAocmVjb3Jk
X2FyY2hfbGlzdF9hZGRfcmVnIChpci5yZWdjYWNoZSwgSTM4Nl9FU19SRUdO
VU0pKQotCXJldHVybiAtMTsKKyAgICAgIGlmIChpci5yZWdtYXBbWDg2X1JF
Q09SRF9SOF9SRUdOVU1dKQorICAgICAgICB7CisJICBpci5hZGRyIC09IDE7
CisJICBnb3RvIG5vX3N1cHBvcnQ7CisJfQorICAgICAgSTM4Nl9SRUNPUkRf
QVJDSF9MSVNUX0FERF9SRUcgKFg4Nl9SRUNPUkRfUkVTUF9SRUdOVU0pOwor
ICAgICAgSTM4Nl9SRUNPUkRfQVJDSF9MSVNUX0FERF9SRUcgKFg4Nl9SRUNP
UkRfRVNfUkVHTlVNKTsKKyAgICAgIEkzODZfUkVDT1JEX0FSQ0hfTElTVF9B
RERfUkVHIChYODZfUkVDT1JEX0VGTEFHU19SRUdOVU0pOwogICAgICAgYnJl
YWs7CiAKICAgICAgIC8qIHBvcCBzcyAqLwogICAgIGNhc2UgMHgxNzoKLSAg
ICAgIGlmIChyZWNvcmRfYXJjaF9saXN0X2FkZF9yZWcgKGlyLnJlZ2NhY2hl
LCBJMzg2X0VTUF9SRUdOVU0pKQotCXJldHVybiAtMTsKLSAgICAgIGlmIChy
ZWNvcmRfYXJjaF9saXN0X2FkZF9yZWcgKGlyLnJlZ2NhY2hlLCBJMzg2X1NT
X1JFR05VTSkpCi0JcmV0dXJuIC0xOworICAgICAgaWYgKGlyLnJlZ21hcFtY
ODZfUkVDT1JEX1I4X1JFR05VTV0pCisgICAgICAgIHsKKwkgIGlyLmFkZHIg
LT0gMTsKKwkgIGdvdG8gbm9fc3VwcG9ydDsKKwl9CisgICAgICBJMzg2X1JF
Q09SRF9BUkNIX0xJU1RfQUREX1JFRyAoWDg2X1JFQ09SRF9SRVNQX1JFR05V
TSk7CisgICAgICBJMzg2X1JFQ09SRF9BUkNIX0xJU1RfQUREX1JFRyAoWDg2
X1JFQ09SRF9TU19SRUdOVU0pOworICAgICAgSTM4Nl9SRUNPUkRfQVJDSF9M
SVNUX0FERF9SRUcgKFg4Nl9SRUNPUkRfRUZMQUdTX1JFR05VTSk7CiAgICAg
ICBicmVhazsKIAogICAgICAgLyogcG9wIGRzICovCiAgICAgY2FzZSAweDFm
OgotICAgICAgaWYgKHJlY29yZF9hcmNoX2xpc3RfYWRkX3JlZyAoaXIucmVn
Y2FjaGUsIEkzODZfRVNQX1JFR05VTSkpCi0JcmV0dXJuIC0xOwotICAgICAg
aWYgKHJlY29yZF9hcmNoX2xpc3RfYWRkX3JlZyAoaXIucmVnY2FjaGUsIEkz
ODZfRFNfUkVHTlVNKSkKLQlyZXR1cm4gLTE7CisgICAgICBpZiAoaXIucmVn
bWFwW1g4Nl9SRUNPUkRfUjhfUkVHTlVNXSkKKyAgICAgICAgeworCSAgaXIu
YWRkciAtPSAxOworCSAgZ290byBub19zdXBwb3J0OworCX0KKyAgICAgIEkz
ODZfUkVDT1JEX0FSQ0hfTElTVF9BRERfUkVHIChYODZfUkVDT1JEX1JFU1Bf
UkVHTlVNKTsKKyAgICAgIEkzODZfUkVDT1JEX0FSQ0hfTElTVF9BRERfUkVH
IChYODZfUkVDT1JEX0RTX1JFR05VTSk7CisgICAgICBJMzg2X1JFQ09SRF9B
UkNIX0xJU1RfQUREX1JFRyAoWDg2X1JFQ09SRF9FRkxBR1NfUkVHTlVNKTsK
ICAgICAgIGJyZWFrOwogCiAgICAgICAvKiBwb3AgZnMgKi8KICAgICBjYXNl
IDB4MGZhMToKLSAgICAgIGlmIChyZWNvcmRfYXJjaF9saXN0X2FkZF9yZWcg
KGlyLnJlZ2NhY2hlLCBJMzg2X0VTUF9SRUdOVU0pKQotCXJldHVybiAtMTsK
LSAgICAgIGlmIChyZWNvcmRfYXJjaF9saXN0X2FkZF9yZWcgKGlyLnJlZ2Nh
Y2hlLCBJMzg2X0ZTX1JFR05VTSkpCi0JcmV0dXJuIC0xOworICAgICAgSTM4
Nl9SRUNPUkRfQVJDSF9MSVNUX0FERF9SRUcgKFg4Nl9SRUNPUkRfUkVTUF9S
RUdOVU0pOworICAgICAgSTM4Nl9SRUNPUkRfQVJDSF9MSVNUX0FERF9SRUcg
KFg4Nl9SRUNPUkRfRlNfUkVHTlVNKTsKKyAgICAgIEkzODZfUkVDT1JEX0FS
Q0hfTElTVF9BRERfUkVHIChYODZfUkVDT1JEX0VGTEFHU19SRUdOVU0pOwog
ICAgICAgYnJlYWs7CiAKICAgICAgIC8qIHBvcCBncyAqLwogICAgIGNhc2Ug
MHgwZmE5OgotICAgICAgaWYgKHJlY29yZF9hcmNoX2xpc3RfYWRkX3JlZyAo
aXIucmVnY2FjaGUsIEkzODZfRVNQX1JFR05VTSkpCi0JcmV0dXJuIC0xOwot
ICAgICAgaWYgKHJlY29yZF9hcmNoX2xpc3RfYWRkX3JlZyAoaXIucmVnY2Fj
aGUsIEkzODZfR1NfUkVHTlVNKSkKLQlyZXR1cm4gLTE7CisgICAgICBJMzg2
X1JFQ09SRF9BUkNIX0xJU1RfQUREX1JFRyAoWDg2X1JFQ09SRF9SRVNQX1JF
R05VTSk7CisgICAgICBJMzg2X1JFQ09SRF9BUkNIX0xJU1RfQUREX1JFRyAo
WDg2X1JFQ09SRF9HU19SRUdOVU0pOworICAgICAgSTM4Nl9SRUNPUkRfQVJD
SF9MSVNUX0FERF9SRUcgKFg4Nl9SRUNPUkRfRUZMQUdTX1JFR05VTSk7CiAg
ICAgICBicmVhazsKIAogICAgICAgLyogbW92ICovCkBAIC0zODI2LDE5ICsz
OTE1LDIxIEBAIHJlc3dpdGNoOgogCiAgICAgICBpZiAoaXIubW9kICE9IDMp
CiAJeworICAgICAgICAgIGlmIChvcGNvZGUgPT0gMHhjNiB8fCBvcGNvZGUg
PT0gMHhjNykKKwkgICAgaXIucmlwX29mZnNldCA9IChpci5vdCA+IE9UX0xP
TkcpID8gNCA6ICgxIDw8IGlyLm90KTsKIAkgIGlmIChpMzg2X3JlY29yZF9s
ZWFfbW9kcm0gKCZpcikpCiAJICAgIHJldHVybiAtMTsKIAl9CiAgICAgICBl
bHNlCiAJewotCSAgaWYgKGlyLm90ID09IE9UX0JZVEUpCisgICAgICAgICAg
aWYgKG9wY29kZSA9PSAweGM2IHx8IG9wY29kZSA9PSAweGM3KQorCSAgICBp
ci5ybSB8PSBpci5yZXhfYjsKKwkgIGlmIChpci5vdCA9PSBPVF9CWVRFICYm
ICFpci5yZWdtYXBbWDg2X1JFQ09SRF9SOF9SRUdOVU1dKQogCSAgICBpci5y
bSAmPSAweDM7Ci0JICBpZiAocmVjb3JkX2FyY2hfbGlzdF9hZGRfcmVnIChp
ci5yZWdjYWNoZSwgaXIucm0pKQotCSAgICByZXR1cm4gLTE7CisJICBJMzg2
X1JFQ09SRF9BUkNIX0xJU1RfQUREX1JFRyAoaXIucm0pOwogCX0KLSAgICAg
IGlmIChyZWNvcmRfYXJjaF9saXN0X2FkZF9yZWcgKGlyLnJlZ2NhY2hlLCBJ
Mzg2X0VGTEFHU19SRUdOVU0pKQotCXJldHVybiAtMTsKICAgICAgIGJyZWFr
OworCiAgICAgICAvKiBtb3YgKi8KICAgICBjYXNlIDB4OGE6CiAgICAgY2Fz
ZSAweDhiOgpAQCAtMzg0Niw0MCArMzkzNyw1NSBAQCByZXN3aXRjaDoKIAlp
ci5vdCA9IE9UX0JZVEU7CiAgICAgICBlbHNlCiAJaXIub3QgPSBpci5kZmxh
ZyArIE9UX1dPUkQ7Ci0KICAgICAgIGlmIChpMzg2X3JlY29yZF9tb2RybSAo
JmlyKSkKIAlyZXR1cm4gLTE7Ci0KLSAgICAgIGlmIChpci5vdCA9PSBPVF9C
WVRFKQorICAgICAgaXIucmVnIHw9IHJleF9yOworICAgICAgaWYgKGlyLm90
ID09IE9UX0JZVEUgJiYgIWlyLnJlZ21hcFtYODZfUkVDT1JEX1I4X1JFR05V
TV0pCiAJaXIucmVnICY9IDB4MzsKLSAgICAgIGlmIChyZWNvcmRfYXJjaF9s
aXN0X2FkZF9yZWcgKGlyLnJlZ2NhY2hlLCBpci5yZWcpKQotCXJldHVybiAt
MTsKKyAgICAgIEkzODZfUkVDT1JEX0FSQ0hfTElTVF9BRERfUkVHIChpci5y
ZWcpOworICAgICAgYnJlYWs7CiAKLSAgICAgIGlmIChyZWNvcmRfYXJjaF9s
aXN0X2FkZF9yZWcgKGlyLnJlZ2NhY2hlLCBJMzg2X0VGTEFHU19SRUdOVU0p
KQorICAgICAgLyogbW92IHNlZyAqLworICAgIGNhc2UgMHg4YzoKKyAgICAg
IGlmIChpMzg2X3JlY29yZF9tb2RybSAoJmlyKSkKIAlyZXR1cm4gLTE7Cisg
ICAgICBpZiAoaXIucmVnID4gNSkKKwl7CisJICBpci5hZGRyIC09IDI7CisJ
ICBvcGNvZGUgPSBvcGNvZGUgPDwgOCB8IGlyLm1vZHJtOworCSAgZ290byBu
b19zdXBwb3J0OworCX0KKworICAgICAgaWYgKGlyLm1vZCA9PSAzKQorCUkz
ODZfUkVDT1JEX0FSQ0hfTElTVF9BRERfUkVHIChpci5ybSk7CisgICAgICBl
bHNlCisJeworCSAgaXIub3QgPSBPVF9XT1JEOworCSAgaWYgKGkzODZfcmVj
b3JkX2xlYV9tb2RybSAoJmlyKSkKKwkgICAgcmV0dXJuIC0xOworCX0KICAg
ICAgIGJyZWFrOwogCiAgICAgICAvKiBtb3Ygc2VnICovCiAgICAgY2FzZSAw
eDhlOgogICAgICAgaWYgKGkzODZfcmVjb3JkX21vZHJtICgmaXIpKQogCXJl
dHVybiAtMTsKLQogICAgICAgc3dpdGNoIChpci5yZWcpCiAJewogCWNhc2Ug
MDoKLQkgIHRtcHU4ID0gSTM4Nl9FU19SRUdOVU07CisJICB0bXB1OCA9IFg4
Nl9SRUNPUkRfRVNfUkVHTlVNOwogCSAgYnJlYWs7CiAJY2FzZSAyOgotCSAg
dG1wdTggPSBJMzg2X1NTX1JFR05VTTsKKwkgIHRtcHU4ID0gWDg2X1JFQ09S
RF9TU19SRUdOVU07CiAJICBicmVhazsKIAljYXNlIDM6Ci0JICB0bXB1OCA9
IEkzODZfRFNfUkVHTlVNOworCSAgdG1wdTggPSBYODZfUkVDT1JEX0RTX1JF
R05VTTsKIAkgIGJyZWFrOwogCWNhc2UgNDoKLQkgIHRtcHU4ID0gSTM4Nl9G
U19SRUdOVU07CisJICB0bXB1OCA9IFg4Nl9SRUNPUkRfRlNfUkVHTlVNOwog
CSAgYnJlYWs7CiAJY2FzZSA1OgotCSAgdG1wdTggPSBJMzg2X0dTX1JFR05V
TTsKKwkgIHRtcHU4ID0gWDg2X1JFQ09SRF9HU19SRUdOVU07CiAJICBicmVh
azsKIAlkZWZhdWx0OgogCSAgaXIuYWRkciAtPSAyOwpAQCAtMzg4NywzOCAr
Mzk5Myw4IEBAIHJlc3dpdGNoOgogCSAgZ290byBub19zdXBwb3J0OwogCSAg
YnJlYWs7CiAJfQotICAgICAgaWYgKHJlY29yZF9hcmNoX2xpc3RfYWRkX3Jl
ZyAoaXIucmVnY2FjaGUsIHRtcHU4KSkKLQlyZXR1cm4gLTE7Ci0KLSAgICAg
IGlmIChyZWNvcmRfYXJjaF9saXN0X2FkZF9yZWcgKGlyLnJlZ2NhY2hlLCBJ
Mzg2X0VGTEFHU19SRUdOVU0pKQotCXJldHVybiAtMTsKLSAgICAgIGJyZWFr
OwotCi0gICAgICAvKiBtb3Ygc2VnICovCi0gICAgY2FzZSAweDhjOgotICAg
ICAgaWYgKGkzODZfcmVjb3JkX21vZHJtICgmaXIpKQotCXJldHVybiAtMTsK
LSAgICAgIGlmIChpci5yZWcgPiA1KQotCXsKLQkgIGlyLmFkZHIgLT0gMjsK
LQkgIG9wY29kZSA9IG9wY29kZSA8PCA4IHwgaXIubW9kcm07Ci0JICBnb3Rv
IG5vX3N1cHBvcnQ7Ci0JfQotCi0gICAgICBpZiAoaXIubW9kID09IDMpCi0J
ewotCSAgaWYgKHJlY29yZF9hcmNoX2xpc3RfYWRkX3JlZyAoaXIucmVnY2Fj
aGUsIGlyLnJtKSkKLQkgICAgcmV0dXJuIC0xOwotCX0KLSAgICAgIGVsc2UK
LQl7Ci0JICBpci5vdCA9IE9UX1dPUkQ7Ci0JICBpZiAoaTM4Nl9yZWNvcmRf
bGVhX21vZHJtICgmaXIpKQotCSAgICByZXR1cm4gLTE7Ci0JfQotCi0gICAg
ICBpZiAocmVjb3JkX2FyY2hfbGlzdF9hZGRfcmVnIChpci5yZWdjYWNoZSwg
STM4Nl9FRkxBR1NfUkVHTlVNKSkKLQlyZXR1cm4gLTE7CisgICAgICBJMzg2
X1JFQ09SRF9BUkNIX0xJU1RfQUREX1JFRyAodG1wdTgpOworICAgICAgSTM4
Nl9SRUNPUkRfQVJDSF9MSVNUX0FERF9SRUcgKFg4Nl9SRUNPUkRfRUZMQUdT
X1JFR05VTSk7CiAgICAgICBicmVhazsKIAogICAgICAgLyogbW92emJTICov
CkBAIC0zOTMxLDggKzQwMDcsNyBAQCByZXN3aXRjaDoKICAgICBjYXNlIDB4
MGZiZjoKICAgICAgIGlmIChpMzg2X3JlY29yZF9tb2RybSAoJmlyKSkKIAly
ZXR1cm4gLTE7Ci0gICAgICBpZiAocmVjb3JkX2FyY2hfbGlzdF9hZGRfcmVn
IChpci5yZWdjYWNoZSwgaXIucmVnKSkKLQlyZXR1cm4gLTE7CisgICAgICBJ
Mzg2X1JFQ09SRF9BUkNIX0xJU1RfQUREX1JFRyAoaXIucmVnIHwgcmV4X3Ip
OwogICAgICAgYnJlYWs7CiAKICAgICAgIC8qIGxlYSAqLwpAQCAtMzk0NSwx
MiArNDAyMCwxMSBAQCByZXN3aXRjaDoKIAkgIG9wY29kZSA9IG9wY29kZSA8
PCA4IHwgaXIubW9kcm07CiAJICBnb3RvIG5vX3N1cHBvcnQ7CiAJfQotCiAg
ICAgICBpci5vdCA9IGlyLmRmbGFnOwotICAgICAgaWYgKGlyLm90ID09IE9U
X0JZVEUpCisgICAgICBpci5yZWcgfD0gcmV4X3I7CisgICAgICBpZiAoaXIu
b3QgPT0gT1RfQllURSAmJiAhaXIucmVnbWFwW1g4Nl9SRUNPUkRfUjhfUkVH
TlVNXSkKIAlpci5yZWcgJj0gMHgzOwotICAgICAgaWYgKHJlY29yZF9hcmNo
X2xpc3RfYWRkX3JlZyAoaXIucmVnY2FjaGUsIGlyLnJlZykpCi0JcmV0dXJu
IC0xOworICAgICAgSTM4Nl9SRUNPUkRfQVJDSF9MSVNUX0FERF9SRUcgKGly
LnJlZyk7CiAgICAgICBicmVhazsKIAogICAgICAgLyogbW92IEVBWCAqLwpA
QCAtMzk1OCw2MiArNDAzMiw2OCBAQCByZXN3aXRjaDoKICAgICBjYXNlIDB4
YTE6CiAgICAgICAvKiB4bGF0ICovCiAgICAgY2FzZSAweGQ3OgotICAgICAg
aWYgKHJlY29yZF9hcmNoX2xpc3RfYWRkX3JlZyAoaXIucmVnY2FjaGUsIEkz
ODZfRUFYX1JFR05VTSkpCi0JcmV0dXJuIC0xOworICAgICAgSTM4Nl9SRUNP
UkRfQVJDSF9MSVNUX0FERF9SRUcgKFg4Nl9SRUNPUkRfUkVBWF9SRUdOVU0p
OwogICAgICAgYnJlYWs7CiAKICAgICAgIC8qIG1vdiBFQVggKi8KICAgICBj
YXNlIDB4YTI6CiAgICAgY2FzZSAweGEzOgotICAgICAgewotCXVpbnQzMl90
IGFkZHI7Ci0KLQlpZiAoaXIub3ZlcnJpZGUpCi0JICB7Ci0JICAgIGlmIChy
ZWNvcmRfZGVidWcpCi0JICAgICAgcHJpbnRmX3VuZmlsdGVyZWQgKF8oIlBy
b2Nlc3MgcmVjb3JkIGlnbm9yZXMgdGhlIG1lbW9yeSBjaGFuZ2UgIgotCQkJ
CSAgICJvZiBpbnN0cnVjdGlvbiBhdCBhZGRyZXNzICVzIGJlY2F1c2UgIgot
CQkJCSAgICJpdCBjYW4ndCBnZXQgdGhlIHZhbHVlIG9mIHRoZSBzZWdtZW50
ICIKLQkJCQkgICAicmVnaXN0ZXIuXG4iKSwKLQkJCQkgcGFkZHJlc3MgKGdk
YmFyY2gsIGlyLmFkZHIpKTsKLQkgIH0KLQllbHNlCi0JICB7Ci0JICAgIGlm
ICgob3Bjb2RlICYgMSkgPT0gMCkKLQkgICAgICBpci5vdCA9IE9UX0JZVEU7
Ci0JICAgIGVsc2UKLQkgICAgICBpci5vdCA9IGlyLmRmbGFnICsgT1RfV09S
RDsKLQkgICAgaWYgKGlyLmFmbGFnKQotCSAgICAgIHsKLQkJaWYgKHRhcmdl
dF9yZWFkX21lbW9yeQotCQkgICAgKGlyLmFkZHIsIChnZGJfYnl0ZSAqKSAm
IGFkZHIsIDQpKQotCQkgIHsKLQkJICAgIGlmIChyZWNvcmRfZGVidWcpCi0J
CSAgICAgIHByaW50Zl91bmZpbHRlcmVkIChfKCJQcm9jZXNzIHJlY29yZDog
ZXJyb3IgcmVhZGluZyAiCi0JCQkJCSAgICJtZW1vcnkgYXQgYWRkciAlcyBs
ZW4gPSA0LlxuIiksCi0JCQkJCSBwYWRkcmVzcyAoZ2RiYXJjaCwgaXIuYWRk
cikpOwotCQkgICAgcmV0dXJuIC0xOwotCQkgIH0KLQkJaXIuYWRkciArPSA0
OwotCSAgICAgIH0KLQkgICAgZWxzZQotCSAgICAgIHsKLQkJaWYgKHRhcmdl
dF9yZWFkX21lbW9yeQotCQkgICAgKGlyLmFkZHIsIChnZGJfYnl0ZSAqKSAm
IHRtcHUxNiwgNCkpCi0JCSAgewotCQkgICAgaWYgKHJlY29yZF9kZWJ1ZykK
LQkJICAgICAgcHJpbnRmX3VuZmlsdGVyZWQgKF8oIlByb2Nlc3MgcmVjb3Jk
OiBlcnJvciByZWFkaW5nICIKLQkJCQkJICAgIm1lbW9yeSBhdCBhZGRyICVz
IGxlbiA9IDQuXG4iKSwKLQkJCQkJIHBhZGRyZXNzIChnZGJhcmNoLCBpci5h
ZGRyKSk7Ci0JCSAgICByZXR1cm4gLTE7Ci0JCSAgfQotCQlpci5hZGRyICs9
IDI7Ci0JCWFkZHIgPSB0bXB1MTY7Ci0JICAgICAgfQotCSAgICBpZiAocmVj
b3JkX2FyY2hfbGlzdF9hZGRfbWVtIChhZGRyLCAxIDw8IGlyLm90KSkKLQkg
ICAgICByZXR1cm4gLTE7Ci0JICB9Ci0gICAgICB9CisgICAgICBpZiAoaXIu
b3ZlcnJpZGUgPj0gMCkKKyAgICAgICAgeworCSAgaWYgKHJlY29yZF9kZWJ1
ZykKKwkgICAgcHJpbnRmX3VuZmlsdGVyZWQgKF8oIlByb2Nlc3MgcmVjb3Jk
IGlnbm9yZXMgdGhlIG1lbW9yeSBjaGFuZ2UgIgorCQkJCSAib2YgaW5zdHJ1
Y3Rpb24gYXQgYWRkcmVzcyAweCVzIGJlY2F1c2UgIgorCQkJCSAiaXQgY2Fu
J3QgZ2V0IHRoZSB2YWx1ZSBvZiB0aGUgc2VnbWVudCAiCisJCQkJICJyZWdp
c3Rlci5cbiIpLAorCQkJICAgICAgIHBhZGRyZXNzIChnZGJhcmNoLCBpci5h
ZGRyKSk7CisJfQorICAgICAgZWxzZQorCXsKKyAgICAgICAgICBpZiAoKG9w
Y29kZSAmIDEpID09IDApCisJICAgIGlyLm90ID0gT1RfQllURTsKKwkgIGVs
c2UKKwkgICAgaXIub3QgPSBpci5kZmxhZyArIE9UX1dPUkQ7CisJICBpZiAo
aXIuYWZsYWcgPT0gMikKKwkgICAgeworICAgICAgICAgICAgICBpZiAodGFy
Z2V0X3JlYWRfbWVtb3J5IChpci5hZGRyLCAoZ2RiX2J5dGUgKikgJmFkZHIs
IDgpKQorCQl7CisJICAgICAgICAgIGlmIChyZWNvcmRfZGVidWcpCisJCSAg
ICBwcmludGZfdW5maWx0ZXJlZCAoXygiUHJvY2VzcyByZWNvcmQ6IGVycm9y
IHJlYWRpbmcgIgorCSAgICAgICAgICAgICAgICAgICAgCQkgIm1lbW9yeSBh
dCBhZGRyIDB4JXMgbGVuID0gOC5cbiIpLAorCQkJCSAgICAgICBwYWRkcmVz
cyAoZ2RiYXJjaCwgaXIuYWRkcikpOworCQkgIHJldHVybiAtMTsKKwkJfQor
CSAgICAgIGlyLmFkZHIgKz0gODsKKwkgICAgfQorICAgICAgICAgIGVsc2Ug
aWYgKGlyLmFmbGFnKQorCSAgICB7CisgICAgICAgICAgICAgIGlmICh0YXJn
ZXRfcmVhZF9tZW1vcnkgKGlyLmFkZHIsIChnZGJfYnl0ZSAqKSAmdG1wdTMy
LCA0KSkKKwkJeworCSAgICAgICAgICBpZiAocmVjb3JkX2RlYnVnKQorCQkg
ICAgcHJpbnRmX3VuZmlsdGVyZWQgKF8oIlByb2Nlc3MgcmVjb3JkOiBlcnJv
ciByZWFkaW5nICIKKwkgICAgICAgICAgICAgICAgICAgIAkJICJtZW1vcnkg
YXQgYWRkciAweCVzIGxlbiA9IDQuXG4iKSwKKwkJCQkgICAgICAgcGFkZHJl
c3MgKGdkYmFyY2gsIGlyLmFkZHIpKTsKKwkJICByZXR1cm4gLTE7CisJCX0K
KwkgICAgICBpci5hZGRyICs9IDQ7CisgICAgICAgICAgICAgIGFkZHIgPSB0
bXB1MzI7CisJICAgIH0KKyAgICAgICAgICBlbHNlCisJICAgIHsKKyAgICAg
ICAgICAgICAgaWYgKHRhcmdldF9yZWFkX21lbW9yeSAoaXIuYWRkciwgKGdk
Yl9ieXRlICopICZ0bXB1MTYsIDIpKQorCQl7CisJICAgICAgICAgIGlmIChy
ZWNvcmRfZGVidWcpCisJCSAgICBwcmludGZfdW5maWx0ZXJlZCAoXygiUHJv
Y2VzcyByZWNvcmQ6IGVycm9yIHJlYWRpbmcgIgorCSAgICAgICAgICAgICAg
ICAgICAgCQkgIm1lbW9yeSBhdCBhZGRyIDB4JXMgbGVuID0gMi5cbiIpLAor
CQkJCSAgICAgICBwYWRkcmVzcyAoZ2RiYXJjaCwgaXIuYWRkcikpOworCQkg
IHJldHVybiAtMTsKKwkJfQorCSAgICAgIGlyLmFkZHIgKz0gMjsKKyAgICAg
ICAgICAgICAgYWRkciA9IHRtcHUxNjsKKwkgICAgfQorCSAgaWYgKHJlY29y
ZF9hcmNoX2xpc3RfYWRkX21lbSAoYWRkciwgMSA8PCBpci5vdCkpCisJICAg
IHJldHVybiAtMTsKKyAgICAgICAgfQogICAgICAgYnJlYWs7CiAKICAgICAg
IC8qIG1vdiBSLCBJYiAqLwpAQCAtNDAyNSw4ICs0MTA1LDkgQEAgcmVzd2l0
Y2g6CiAgICAgY2FzZSAweGI1OgogICAgIGNhc2UgMHhiNjoKICAgICBjYXNl
IDB4Yjc6Ci0gICAgICBpZiAocmVjb3JkX2FyY2hfbGlzdF9hZGRfcmVnIChp
ci5yZWdjYWNoZSwgKG9wY29kZSAmIDB4NykgJiAweDMpKQotCXJldHVybiAt
MTsKKyAgICAgIEkzODZfUkVDT1JEX0FSQ0hfTElTVF9BRERfUkVHICgoaXIu
cmVnbWFwW1g4Nl9SRUNPUkRfUjhfUkVHTlVNXSkgPworCQkJCSAgICAgKChv
cGNvZGUgJiAweDcpIHwgaXIucmV4X2IpIDoKKwkJCQkgICAgICgob3Bjb2Rl
ICYgMHg3KSAmIDB4MykpOwogICAgICAgYnJlYWs7CiAKICAgICAgIC8qIG1v
diBSLCBJdiAqLwpAQCAtNDAzOCw4ICs0MTE5LDcgQEAgcmVzd2l0Y2g6CiAg
ICAgY2FzZSAweGJkOgogICAgIGNhc2UgMHhiZToKICAgICBjYXNlIDB4YmY6
Ci0gICAgICBpZiAocmVjb3JkX2FyY2hfbGlzdF9hZGRfcmVnIChpci5yZWdj
YWNoZSwgb3Bjb2RlICYgMHg3KSkKLQlyZXR1cm4gLTE7CisgICAgICBJMzg2
X1JFQ09SRF9BUkNIX0xJU1RfQUREX1JFRyAoKG9wY29kZSAmIDB4NykgfCBp
ci5yZXhfYik7CiAgICAgICBicmVhazsKIAogICAgICAgLyogeGNoZyBSLCBF
QVggKi8KQEAgLTQwNTAsMTAgKzQxMzAsOCBAQCByZXN3aXRjaDoKICAgICBj
YXNlIDB4OTU6CiAgICAgY2FzZSAweDk2OgogICAgIGNhc2UgMHg5NzoKLSAg
ICAgIGlmIChyZWNvcmRfYXJjaF9saXN0X2FkZF9yZWcgKGlyLnJlZ2NhY2hl
LCBJMzg2X0VBWF9SRUdOVU0pKQotCXJldHVybiAtMTsKLSAgICAgIGlmIChy
ZWNvcmRfYXJjaF9saXN0X2FkZF9yZWcgKGlyLnJlZ2NhY2hlLCBvcGNvZGUg
JiAweDcpKQotCXJldHVybiAtMTsKKyAgICAgIEkzODZfUkVDT1JEX0FSQ0hf
TElTVF9BRERfUkVHIChYODZfUkVDT1JEX1JFQVhfUkVHTlVNKTsKKyAgICAg
IEkzODZfUkVDT1JEX0FSQ0hfTElTVF9BRERfUkVHIChvcGNvZGUgJiAweDcp
OwogICAgICAgYnJlYWs7CiAKICAgICAgIC8qIHhjaGcgRXYsIEd2ICovCkBA
IC00MDYzLDMzICs0MTQxLDM1IEBAIHJlc3dpdGNoOgogCWlyLm90ID0gT1Rf
QllURTsKICAgICAgIGVsc2UKIAlpci5vdCA9IGlyLmRmbGFnICsgT1RfV09S
RDsKLQogICAgICAgaWYgKGkzODZfcmVjb3JkX21vZHJtICgmaXIpKQogCXJl
dHVybiAtMTsKLQogICAgICAgaWYgKGlyLm1vZCA9PSAzKQogCXsKLQkgIGlm
IChpci5vdCA9PSBPVF9CWVRFKQorCSAgaXIucm0gIT0gaXIucmV4X2I7CisJ
ICBpZiAoaXIub3QgPT0gT1RfQllURSAmJiAhaXIucmVnbWFwW1g4Nl9SRUNP
UkRfUjhfUkVHTlVNXSkKIAkgICAgaXIucm0gJj0gMHgzOwotCSAgaWYgKHJl
Y29yZF9hcmNoX2xpc3RfYWRkX3JlZyAoaXIucmVnY2FjaGUsIGlyLnJtKSkK
LQkgICAgcmV0dXJuIC0xOworCSAgSTM4Nl9SRUNPUkRfQVJDSF9MSVNUX0FE
RF9SRUcgKGlyLnJtKTsKIAl9CiAgICAgICBlbHNlCiAJewogCSAgaWYgKGkz
ODZfcmVjb3JkX2xlYV9tb2RybSAoJmlyKSkKIAkgICAgcmV0dXJuIC0xOwog
CX0KLQotICAgICAgaWYgKGlyLm90ID09IE9UX0JZVEUpCisgICAgICBpci5y
ZWcgfD0gcmV4X3I7CisgICAgICBpZiAoaXIub3QgPT0gT1RfQllURSAmJiAh
aXIucmVnbWFwW1g4Nl9SRUNPUkRfUjhfUkVHTlVNXSkKIAlpci5yZWcgJj0g
MHgzOwotICAgICAgaWYgKHJlY29yZF9hcmNoX2xpc3RfYWRkX3JlZyAoaXIu
cmVnY2FjaGUsIGlyLnJlZykpCi0JcmV0dXJuIC0xOworICAgICAgSTM4Nl9S
RUNPUkRfQVJDSF9MSVNUX0FERF9SRUcgKGlyLnJlZyk7CiAgICAgICBicmVh
azsKIAogICAgICAgLyogbGVzIEd2ICovCiAgICAgY2FzZSAweGM0OgogICAg
ICAgLyogbGRzIEd2ICovCiAgICAgY2FzZSAweGM1OgorICAgICAgaWYgKGly
LnJlZ21hcFtYODZfUkVDT1JEX1I4X1JFR05VTV0pCisgICAgICAgIHsKKwkg
IGlyLmFkZHIgLT0gMTsKKwkgIGdvdG8gbm9fc3VwcG9ydDsKKwl9CiAgICAg
ICAvKiBsc3MgR3YgKi8KICAgICBjYXNlIDB4MGZiMjoKICAgICAgIC8qIGxm
cyBHdiAqLwpAQCAtNDEwNywzNSArNDE4NywzMiBAQCByZXN3aXRjaDoKIAkg
IG9wY29kZSA9IG9wY29kZSA8PCA4IHwgaXIubW9kcm07CiAJICBnb3RvIG5v
X3N1cHBvcnQ7CiAJfQotCiAgICAgICBzd2l0Y2ggKG9wY29kZSkKIAl7CiAJ
ICAvKiBsZXMgR3YgKi8KIAljYXNlIDB4YzQ6Ci0JICB0bXB1OCA9IEkzODZf
RVNfUkVHTlVNOworCSAgdG1wdTggPSBYODZfUkVDT1JEX0VTX1JFR05VTTsK
IAkgIGJyZWFrOwogCSAgLyogbGRzIEd2ICovCiAJY2FzZSAweGM1OgotCSAg
dG1wdTggPSBJMzg2X0RTX1JFR05VTTsKKwkgIHRtcHU4ID0gWDg2X1JFQ09S
RF9EU19SRUdOVU07CiAJICBicmVhazsKIAkgIC8qIGxzcyBHdiAqLwogCWNh
c2UgMHgwZmIyOgotCSAgdG1wdTggPSBJMzg2X1NTX1JFR05VTTsKKwkgIHRt
cHU4ID0gWDg2X1JFQ09SRF9TU19SRUdOVU07CiAJICBicmVhazsKIAkgIC8q
IGxmcyBHdiAqLwogCWNhc2UgMHgwZmI0OgotCSAgdG1wdTggPSBJMzg2X0ZT
X1JFR05VTTsKKwkgIHRtcHU4ID0gWDg2X1JFQ09SRF9GU19SRUdOVU07CiAJ
ICBicmVhazsKIAkgIC8qIGxncyBHdiAqLwogCWNhc2UgMHgwZmI1OgotCSAg
dG1wdTggPSBJMzg2X0dTX1JFR05VTTsKKwkgIHRtcHU4ID0gWDg2X1JFQ09S
RF9HU19SRUdOVU07CiAJICBicmVhazsKIAl9Ci0gICAgICBpZiAocmVjb3Jk
X2FyY2hfbGlzdF9hZGRfcmVnIChpci5yZWdjYWNoZSwgdG1wdTgpKQotCXJl
dHVybiAtMTsKLQotICAgICAgaWYgKHJlY29yZF9hcmNoX2xpc3RfYWRkX3Jl
ZyAoaXIucmVnY2FjaGUsIGlyLnJlZykpCi0JcmV0dXJuIC0xOworICAgICAg
STM4Nl9SRUNPUkRfQVJDSF9MSVNUX0FERF9SRUcgKHRtcHU4KTsKKyAgICAg
IEkzODZfUkVDT1JEX0FSQ0hfTElTVF9BRERfUkVHIChpci5yZWcgfCByZXhf
cik7CisgICAgICBJMzg2X1JFQ09SRF9BUkNIX0xJU1RfQUREX1JFRyAoWDg2
X1JFQ09SRF9FRkxBR1NfUkVHTlVNKTsKICAgICAgIGJyZWFrOwogCiAgICAg
ICAvKiBzaGlmdHMgKi8KQEAgLTQxNDksMTAgKzQyMjYsOCBAQCByZXN3aXRj
aDoKIAlpci5vdCA9IE9UX0JZVEU7CiAgICAgICBlbHNlCiAJaXIub3QgPSBp
ci5kZmxhZyArIE9UX1dPUkQ7Ci0KICAgICAgIGlmIChpMzg2X3JlY29yZF9t
b2RybSAoJmlyKSkKIAlyZXR1cm4gLTE7Ci0KICAgICAgIGlmIChpci5tb2Qg
IT0gMyAmJiAob3Bjb2RlID09IDB4ZDIgfHwgb3Bjb2RlID09IDB4ZDMpKQog
CXsKIAkgIGlmIChpMzg2X3JlY29yZF9sZWFfbW9kcm0gKCZpcikpCkBAIC00
MTYwLDE0ICs0MjM1LDEyIEBAIHJlc3dpdGNoOgogCX0KICAgICAgIGVsc2UK
IAl7Ci0JICBpZiAoaXIub3QgPT0gT1RfQllURSkKKwkgIGlyLnJtIHw9IGly
LnJleF9iOworCSAgaWYgKGlyLm90ID09IE9UX0JZVEUgJiYgIWlyLnJlZ21h
cFtYODZfUkVDT1JEX1I4X1JFR05VTV0pCiAJICAgIGlyLnJtICY9IDB4MzsK
LQkgIGlmIChyZWNvcmRfYXJjaF9saXN0X2FkZF9yZWcgKGlyLnJlZ2NhY2hl
LCBpci5ybSkpCi0JICAgIHJldHVybiAtMTsKKwkgIEkzODZfUkVDT1JEX0FS
Q0hfTElTVF9BRERfUkVHIChpci5ybSk7CiAJfQotCi0gICAgICBpZiAocmVj
b3JkX2FyY2hfbGlzdF9hZGRfcmVnIChpci5yZWdjYWNoZSwgSTM4Nl9FRkxB
R1NfUkVHTlVNKSkKLQlyZXR1cm4gLTE7CisgICAgICBJMzg2X1JFQ09SRF9B
UkNIX0xJU1RfQUREX1JFRyAoWDg2X1JFQ09SRF9FRkxBR1NfUkVHTlVNKTsK
ICAgICAgIGJyZWFrOwogCiAgICAgY2FzZSAweDBmYTQ6CkBAIC00MjA0LDkg
KzQyNzcsOSBAQCByZXN3aXRjaDoKICAgICAgIGlmIChpci5tb2QgIT0gMykK
IAl7CiAJICAvKiBtZW1vcnkgKi8KLQkgIHVpbnQzMl90IGFkZHI7CisJICB1
aW50NjRfdCB0bXB1NjQ7CiAKLQkgIGlmIChpMzg2X3JlY29yZF9sZWFfbW9k
cm1fYWRkciAoJmlyLCAmYWRkcikpCisJICBpZiAoaTM4Nl9yZWNvcmRfbGVh
X21vZHJtX2FkZHIgKCZpciwgJnRtcHU2NCkpCiAJICAgIHJldHVybiAtMTsK
IAkgIHN3aXRjaCAoaXIucmVnKQogCSAgICB7CkBAIC00MjY2LDE2ICs0MzM5
LDE2IEBAIHJlc3dpdGNoOgogCQkgIHN3aXRjaCAoaXIucmVnID4+IDQpCiAJ
CSAgICB7CiAJCSAgICBjYXNlIDA6Ci0JCSAgICAgIGlmIChyZWNvcmRfYXJj
aF9saXN0X2FkZF9tZW0gKGFkZHIsIDQpKQorCQkgICAgICBpZiAocmVjb3Jk
X2FyY2hfbGlzdF9hZGRfbWVtICh0bXB1NjQsIDQpKQogCQkJcmV0dXJuIC0x
OwogCQkgICAgICBicmVhazsKIAkJICAgIGNhc2UgMjoKLQkJICAgICAgaWYg
KHJlY29yZF9hcmNoX2xpc3RfYWRkX21lbSAoYWRkciwgOCkpCisJCSAgICAg
IGlmIChyZWNvcmRfYXJjaF9saXN0X2FkZF9tZW0gKHRtcHU2NCwgOCkpCiAJ
CQlyZXR1cm4gLTE7CiAJCSAgICAgIGJyZWFrOwogCQkgICAgY2FzZSAzOgog
CQkgICAgZGVmYXVsdDoKLQkJICAgICAgaWYgKHJlY29yZF9hcmNoX2xpc3Rf
YWRkX21lbSAoYWRkciwgMikpCisJCSAgICAgIGlmIChyZWNvcmRfYXJjaF9s
aXN0X2FkZF9tZW0gKHRtcHU2NCwgMikpCiAJCQlyZXR1cm4gLTE7CiAJCSAg
ICAgIGJyZWFrOwogCQkgICAgfQpAQCAtNDI4NSwxNiArNDM1OCwxNiBAQCBy
ZXN3aXRjaDoKIAkJICAgIHsKIAkJICAgIGNhc2UgMDoKIAkJICAgIGNhc2Ug
MToKLQkJICAgICAgaWYgKHJlY29yZF9hcmNoX2xpc3RfYWRkX21lbSAoYWRk
ciwgNCkpCisJCSAgICAgIGlmIChyZWNvcmRfYXJjaF9saXN0X2FkZF9tZW0g
KHRtcHU2NCwgNCkpCiAJCQlyZXR1cm4gLTE7CiAJCSAgICAgIGJyZWFrOwog
CQkgICAgY2FzZSAyOgotCQkgICAgICBpZiAocmVjb3JkX2FyY2hfbGlzdF9h
ZGRfbWVtIChhZGRyLCA4KSkKKwkJICAgICAgaWYgKHJlY29yZF9hcmNoX2xp
c3RfYWRkX21lbSAodG1wdTY0LCA4KSkKIAkJCXJldHVybiAtMTsKIAkJICAg
ICAgYnJlYWs7CiAJCSAgICBjYXNlIDM6CiAJCSAgICBkZWZhdWx0OgotCQkg
ICAgICBpZiAocmVjb3JkX2FyY2hfbGlzdF9hZGRfbWVtIChhZGRyLCAyKSkK
KwkJICAgICAgaWYgKHJlY29yZF9hcmNoX2xpc3RfYWRkX21lbSAodG1wdTY0
LCAyKSkKIAkJCXJldHVybiAtMTsKIAkJICAgICAgYnJlYWs7CiAJCSAgICB9
CkBAIC00MzExLDQzICs0Mzg0LDQzIEBAIHJlc3dpdGNoOgogCSAgICBjYXNl
IDB4MGU6CiAJICAgICAgaWYgKGlyLmRmbGFnKQogCQl7Ci0JCSAgaWYgKHJl
Y29yZF9hcmNoX2xpc3RfYWRkX21lbSAoYWRkciwgMjgpKQorCQkgIGlmIChy
ZWNvcmRfYXJjaF9saXN0X2FkZF9tZW0gKHRtcHU2NCwgMjgpKQogCQkgICAg
cmV0dXJuIC0xOwogCQl9CiAJICAgICAgZWxzZQogCQl7Ci0JCSAgaWYgKHJl
Y29yZF9hcmNoX2xpc3RfYWRkX21lbSAoYWRkciwgMTQpKQorCQkgIGlmIChy
ZWNvcmRfYXJjaF9saXN0X2FkZF9tZW0gKHRtcHU2NCwgMTQpKQogCQkgICAg
cmV0dXJuIC0xOwogCQl9CiAJICAgICAgYnJlYWs7CiAJICAgIGNhc2UgMHgw
ZjoKIAkgICAgY2FzZSAweDJmOgotCSAgICAgIGlmIChyZWNvcmRfYXJjaF9s
aXN0X2FkZF9tZW0gKGFkZHIsIDIpKQorCSAgICAgIGlmIChyZWNvcmRfYXJj
aF9saXN0X2FkZF9tZW0gKHRtcHU2NCwgMikpCiAJCXJldHVybiAtMTsKIAkg
ICAgICBicmVhazsKIAkgICAgY2FzZSAweDFmOgogCSAgICBjYXNlIDB4M2U6
Ci0JICAgICAgaWYgKHJlY29yZF9hcmNoX2xpc3RfYWRkX21lbSAoYWRkciwg
MTApKQorCSAgICAgIGlmIChyZWNvcmRfYXJjaF9saXN0X2FkZF9tZW0gKHRt
cHU2NCwgMTApKQogCQlyZXR1cm4gLTE7CiAJICAgICAgYnJlYWs7CiAJICAg
IGNhc2UgMHgyZToKIAkgICAgICBpZiAoaXIuZGZsYWcpCiAJCXsKLQkJICBp
ZiAocmVjb3JkX2FyY2hfbGlzdF9hZGRfbWVtIChhZGRyLCAyOCkpCisJCSAg
aWYgKHJlY29yZF9hcmNoX2xpc3RfYWRkX21lbSAodG1wdTY0LCAyOCkpCiAJ
CSAgICByZXR1cm4gLTE7Ci0JCSAgYWRkciArPSAyODsKKwkJICB0bXB1NjQg
Kz0gMjg7CiAJCX0KIAkgICAgICBlbHNlCiAJCXsKLQkJICBpZiAocmVjb3Jk
X2FyY2hfbGlzdF9hZGRfbWVtIChhZGRyLCAxNCkpCisJCSAgaWYgKHJlY29y
ZF9hcmNoX2xpc3RfYWRkX21lbSAodG1wdTY0LCAxNCkpCiAJCSAgICByZXR1
cm4gLTE7Ci0JCSAgYWRkciArPSAxNDsKKwkJICB0bXB1NjQgKz0gMTQ7CiAJ
CX0KLQkgICAgICBpZiAocmVjb3JkX2FyY2hfbGlzdF9hZGRfbWVtIChhZGRy
LCA4MCkpCisJICAgICAgaWYgKHJlY29yZF9hcmNoX2xpc3RfYWRkX21lbSAo
dG1wdTY0LCA4MCkpCiAJCXJldHVybiAtMTsKIAkgICAgICBicmVhazsKIAkg
ICAgY2FzZSAweDNmOgotCSAgICAgIGlmIChyZWNvcmRfYXJjaF9saXN0X2Fk
ZF9tZW0gKGFkZHIsIDgpKQorCSAgICAgIGlmIChyZWNvcmRfYXJjaF9saXN0
X2FkZF9tZW0gKHRtcHU2NCwgOCkpCiAJCXJldHVybiAtMTsKIAkgICAgICBi
cmVhazsKIAkgICAgZGVmYXVsdDoKQEAgLTQzNjksMTIzICs0NDQyLDg4IEBA
IHJlc3dpdGNoOgogICAgICAgLyogaW5zUyAqLwogICAgIGNhc2UgMHg2YzoK
ICAgICBjYXNlIDB4NmQ6Ci0gICAgICB7Ci0JdWludDMyX3QgYWRkcjsKLQot
CWlmICgob3Bjb2RlICYgMSkgPT0gMCkKLQkgIGlyLm90ID0gT1RfQllURTsK
LQllbHNlCi0JICBpci5vdCA9IGlyLmRmbGFnICsgT1RfV09SRDsKLQlpZiAo
b3Bjb2RlID09IDB4YTQgfHwgb3Bjb2RlID09IDB4YTUpCi0JICB7Ci0JICAg
IGlmIChyZWNvcmRfYXJjaF9saXN0X2FkZF9yZWcgKGlyLnJlZ2NhY2hlLCBJ
Mzg2X0VTSV9SRUdOVU0pKQotCSAgICAgIHJldHVybiAtMTsKLQkgIH0KLQlp
ZiAocmVjb3JkX2FyY2hfbGlzdF9hZGRfcmVnIChpci5yZWdjYWNoZSwgSTM4
Nl9FRElfUkVHTlVNKSkKLQkgIHJldHVybiAtMTsKLQotCXJlZ2NhY2hlX3Jh
d19yZWFkIChpci5yZWdjYWNoZSwgSTM4Nl9FRElfUkVHTlVNLAotCQkJICAg
KGdkYl9ieXRlICopICYgYWRkcik7Ci0JaWYgKCFpci5hZmxhZykKLQkgIHsK
LQkgICAgYWRkciAmPSAweGZmZmY7Ci0JICAgIC8qIGFkZHIgKz0gKCh1aW50
MzJfdClyZWFkX3JlZ2lzdGVyIChJMzg2X0VTX1JFR05VTSkpIDw8IDQ7ICov
Ci0JICAgIGlmIChyZWNvcmRfZGVidWcpCi0JICAgICAgcHJpbnRmX3VuZmls
dGVyZWQgKF8oIlByb2Nlc3MgcmVjb3JkIGlnbm9yZXMgdGhlIG1lbW9yeSBj
aGFuZ2UgIgotCQkJCSAgICJvZiBpbnN0cnVjdGlvbiBhdCBhZGRyZXNzICVz
IGJlY2F1c2UgIgotCQkJCSAgICJpdCBjYW4ndCBnZXQgdGhlIHZhbHVlIG9m
IHRoZSBzZWdtZW50ICIKLQkJCQkgICAicmVnaXN0ZXIuXG4iKSwKLQkJCQkg
cGFkZHJlc3MgKGdkYmFyY2gsIGlyLmFkZHIpKTsKLQkgIH0KLQotCWlmIChw
cmVmaXhlcyAmIChQUkVGSVhfUkVQWiB8IFBSRUZJWF9SRVBOWikpCi0JICB7
Ci0JICAgIHVpbnQzMl90IGNvdW50OwotCi0JICAgIHJlZ2NhY2hlX3Jhd19y
ZWFkIChpci5yZWdjYWNoZSwgSTM4Nl9FQ1hfUkVHTlVNLAotCQkJICAgICAg
IChnZGJfYnl0ZSAqKSAmIGNvdW50KTsKLQkgICAgaWYgKCFpci5hZmxhZykK
LQkgICAgICBjb3VudCAmPSAweGZmZmY7Ci0KLQkgICAgcmVnY2FjaGVfcmF3
X3JlYWQgKGlyLnJlZ2NhY2hlLCBJMzg2X0VGTEFHU19SRUdOVU0sCi0JCQkg
ICAgICAgKGdkYl9ieXRlICopICYgdG1wdTMyKTsKLQkgICAgaWYgKCh0bXB1
MzIgPj4gMTApICYgMHgxKQotCSAgICAgIGFkZHIgLT0gKGNvdW50IC0gMSkg
KiAoMSA8PCBpci5vdCk7Ci0KLQkgICAgaWYgKGlyLmFmbGFnKQotCSAgICAg
IHsKLQkJaWYgKHJlY29yZF9hcmNoX2xpc3RfYWRkX21lbSAoYWRkciwgY291
bnQgKiAoMSA8PCBpci5vdCkpKQotCQkgIHJldHVybiAtMTsKLQkgICAgICB9
CisgICAgICBpZiAoKG9wY29kZSAmIDEpID09IDApCisJaXIub3QgPSBPVF9C
WVRFOworICAgICAgZWxzZQorCWlyLm90ID0gaXIuZGZsYWcgKyBPVF9XT1JE
OworICAgICAgcmVnY2FjaGVfcmF3X3JlYWRfdW5zaWduZWQgKGlyLnJlZ2Nh
Y2hlLAorICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgIGlyLnJl
Z21hcFtYODZfUkVDT1JEX1JFRElfUkVHTlVNXSwKKyAgICAgICAgICAgICAg
ICAgICAgICAgICAgICAgICAgICAmdG1wdWxvbmdlc3QpOworICAgICAgaWYg
KCFpci5hZmxhZykKKyAgICAgICAgeworICAgICAgICAgIHRtcHVsb25nZXN0
ICY9IDB4ZmZmZjsKKyAgICAgICAgICAvKiBhZGRyICs9ICgodWludDMyX3Qp
IHJlYWRfcmVnaXN0ZXIgKEkzODZfRVNfUkVHTlVNKSkgPDwgNDsgKi8KKyAg
ICAgICAgICBpZiAocmVjb3JkX2RlYnVnKQorICAgICAgICAgICAgcHJpbnRm
X3VuZmlsdGVyZWQgKF8oIlByb2Nlc3MgcmVjb3JkIGlnbm9yZXMgdGhlIG1l
bW9yeSBjaGFuZ2UgIgorICAgICAgICAgICAgICAgICAgICAgICAgICAgICAg
ICAgIm9mIGluc3RydWN0aW9uIGF0IGFkZHJlc3MgMHglcyBiZWNhdXNlICIK
KyAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICJpdCBjYW4ndCBn
ZXQgdGhlIHZhbHVlIG9mIHRoZSBzZWdtZW50ICIKKyAgICAgICAgICAgICAg
ICAgICAgICAgICAgICAgICAgICJyZWdpc3Rlci5cbiIpLAorICAgICAgICAg
ICAgICAgICAgICAgICAgICAgICAgIHBhZGRyZXNzIChnZGJhcmNoLCBpci5h
ZGRyKSk7CisgICAgICAgIH0KKyAgICAgIGlmIChwcmVmaXhlcyAmIChQUkVG
SVhfUkVQWiB8IFBSRUZJWF9SRVBOWikpCisgICAgICAgIHsKKyAgICAgICAg
ICBVTE9OR0VTVCBjb3VudCwgZWZsYWdzOworICAgICAgICAgIHJlZ2NhY2hl
X3Jhd19yZWFkX3Vuc2lnbmVkIChpci5yZWdjYWNoZSwKKyAgICAgICAgICAg
ICAgICAgICAgICAgICAgICAgICAgICAgICAgaXIucmVnbWFwW1g4Nl9SRUNP
UkRfUkVESV9SRUdOVU1dLAorICAgICAgICAgICAgICAgICAgICAgICAgICAg
ICAgICAgICAgICAmY291bnQpOworICAgICAgICAgIGlmICghaXIuYWZsYWcp
CisgICAgICAgICAgICBjb3VudCAmPSAweGZmZmY7CisgICAgICAgICAgcmVn
Y2FjaGVfcmF3X3JlYWRfdW5zaWduZWQgKGlyLnJlZ2NhY2hlLAorICAgICAg
ICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICBpci5yZWdtYXBbWDg2
X1JFQ09SRF9FRkxBR1NfUkVHTlVNXSwKKyAgICAgICAgICAgICAgICAgICAg
ICAgICAgICAgICAgICAgICAgJmVmbGFncyk7CisgICAgICAgICAgaWYgKChl
ZmxhZ3MgPj4gMTApICYgMHgxKQorICAgICAgICAgICAgdG1wdWxvbmdlc3Qg
LT0gKGNvdW50IC0gMSkgKiAoMSA8PCBpci5vdCk7CisgICAgICAgICAgaWYg
KHJlY29yZF9hcmNoX2xpc3RfYWRkX21lbSAodG1wdWxvbmdlc3QsIGNvdW50
ICogKDEgPDwgaXIub3QpKSkKKyAgICAgICAgICAgIHJldHVybiAtMTsKKyAg
ICAgICAgICBJMzg2X1JFQ09SRF9BUkNIX0xJU1RfQUREX1JFRyAoWDg2X1JF
Q09SRF9SRUNYX1JFR05VTSk7CisgICAgICAgIH0KKyAgICAgIGVsc2UKKyAg
ICAgICAgeworICAgICAgICAgIGlmIChyZWNvcmRfYXJjaF9saXN0X2FkZF9t
ZW0gKHRtcHVsb25nZXN0LCAxIDw8IGlyLm90KSkKKyAgICAgICAgICAgIHJl
dHVybiAtMTsKKyAgICAgICAgfQorICAgICAgaWYgKG9wY29kZSA9PSAweGE0
IHx8IG9wY29kZSA9PSAweGE1KQorICAgICAgICBJMzg2X1JFQ09SRF9BUkNI
X0xJU1RfQUREX1JFRyAoWDg2X1JFQ09SRF9SRVNJX1JFR05VTSk7CisgICAg
ICBJMzg2X1JFQ09SRF9BUkNIX0xJU1RfQUREX1JFRyAoWDg2X1JFQ09SRF9S
RURJX1JFR05VTSk7CisgICAgICBJMzg2X1JFQ09SRF9BUkNIX0xJU1RfQURE
X1JFRyAoWDg2X1JFQ09SRF9FRkxBR1NfUkVHTlVNKTsKKyAgICAgIGJyZWFr
OwogCi0JICAgIGlmIChyZWNvcmRfYXJjaF9saXN0X2FkZF9yZWcgKGlyLnJl
Z2NhY2hlLCBJMzg2X0VDWF9SRUdOVU0pKQotCSAgICAgIHJldHVybiAtMTsK
LQkgIH0KLQllbHNlCi0JICB7Ci0JICAgIGlmIChpci5hZmxhZykKLQkgICAg
ICB7Ci0JCWlmIChyZWNvcmRfYXJjaF9saXN0X2FkZF9tZW0gKGFkZHIsIDEg
PDwgaXIub3QpKQotCQkgIHJldHVybiAtMTsKLQkgICAgICB9Ci0JICB9Ci0g
ICAgICB9CisgICAgICAvKiBjbXBzUyAqLworICAgIGNhc2UgMHhhNjoKKyAg
ICBjYXNlIDB4YTc6CisgICAgICBJMzg2X1JFQ09SRF9BUkNIX0xJU1RfQURE
X1JFRyAoWDg2X1JFQ09SRF9SRURJX1JFR05VTSk7CisgICAgICBJMzg2X1JF
Q09SRF9BUkNIX0xJU1RfQUREX1JFRyAoWDg2X1JFQ09SRF9SRVNJX1JFR05V
TSk7CisgICAgICBpZiAocHJlZml4ZXMgJiAoUFJFRklYX1JFUFogfCBQUkVG
SVhfUkVQTlopKQorICAgICAgICBJMzg2X1JFQ09SRF9BUkNIX0xJU1RfQURE
X1JFRyAoWDg2X1JFQ09SRF9SRUNYX1JFR05VTSk7CisgICAgICBJMzg2X1JF
Q09SRF9BUkNIX0xJU1RfQUREX1JFRyAoWDg2X1JFQ09SRF9FRkxBR1NfUkVH
TlVNKTsKICAgICAgIGJyZWFrOwogCiAgICAgICAvKiBsb2RzUyAqLwogICAg
IGNhc2UgMHhhYzoKICAgICBjYXNlIDB4YWQ6Ci0gICAgICBpZiAocmVjb3Jk
X2FyY2hfbGlzdF9hZGRfcmVnIChpci5yZWdjYWNoZSwgSTM4Nl9FQVhfUkVH
TlVNKSkKLQlyZXR1cm4gLTE7Ci0gICAgICBpZiAocmVjb3JkX2FyY2hfbGlz
dF9hZGRfcmVnIChpci5yZWdjYWNoZSwgSTM4Nl9FU0lfUkVHTlVNKSkKLQly
ZXR1cm4gLTE7Ci0gICAgICBpZiAocHJlZml4ZXMgJiAoUFJFRklYX1JFUFog
fCBQUkVGSVhfUkVQTlopKQotCXsKLQkgIGlmIChyZWNvcmRfYXJjaF9saXN0
X2FkZF9yZWcgKGlyLnJlZ2NhY2hlLCBJMzg2X0VDWF9SRUdOVU0pKQotCSAg
ICByZXR1cm4gLTE7Ci0JfQotICAgICAgYnJlYWs7Ci0KLSAgICAgIC8qIG91
dHNTICovCi0gICAgY2FzZSAweDZlOgotICAgIGNhc2UgMHg2ZjoKLSAgICAg
IGlmIChyZWNvcmRfYXJjaF9saXN0X2FkZF9yZWcgKGlyLnJlZ2NhY2hlLCBJ
Mzg2X0VTSV9SRUdOVU0pKQotCXJldHVybiAtMTsKKyAgICAgIEkzODZfUkVD
T1JEX0FSQ0hfTElTVF9BRERfUkVHIChYODZfUkVDT1JEX1JFQVhfUkVHTlVN
KTsKKyAgICAgIEkzODZfUkVDT1JEX0FSQ0hfTElTVF9BRERfUkVHIChYODZf
UkVDT1JEX1JFU0lfUkVHTlVNKTsKICAgICAgIGlmIChwcmVmaXhlcyAmIChQ
UkVGSVhfUkVQWiB8IFBSRUZJWF9SRVBOWikpCi0JewotCSAgaWYgKHJlY29y
ZF9hcmNoX2xpc3RfYWRkX3JlZyAoaXIucmVnY2FjaGUsIEkzODZfRUNYX1JF
R05VTSkpCi0JICAgIHJldHVybiAtMTsKLQl9CisgICAgICAgIEkzODZfUkVD
T1JEX0FSQ0hfTElTVF9BRERfUkVHIChYODZfUkVDT1JEX1JFQ1hfUkVHTlVN
KTsKKyAgICAgIEkzODZfUkVDT1JEX0FSQ0hfTElTVF9BRERfUkVHIChYODZf
UkVDT1JEX0VGTEFHU19SRUdOVU0pOwogICAgICAgYnJlYWs7CiAKICAgICAg
IC8qIHNjYXNTICovCiAgICAgY2FzZSAweGFlOgogICAgIGNhc2UgMHhhZjoK
LSAgICAgIGlmIChyZWNvcmRfYXJjaF9saXN0X2FkZF9yZWcgKGlyLnJlZ2Nh
Y2hlLCBJMzg2X0VESV9SRUdOVU0pKQotCXJldHVybiAtMTsKKyAgICAgIEkz
ODZfUkVDT1JEX0FSQ0hfTElTVF9BRERfUkVHIChYODZfUkVDT1JEX1JFRElf
UkVHTlVNKTsKICAgICAgIGlmIChwcmVmaXhlcyAmIChQUkVGSVhfUkVQWiB8
IFBSRUZJWF9SRVBOWikpCi0JewotCSAgaWYgKHJlY29yZF9hcmNoX2xpc3Rf
YWRkX3JlZyAoaXIucmVnY2FjaGUsIEkzODZfRUNYX1JFR05VTSkpCi0JICAg
IHJldHVybiAtMTsKLQl9Ci0gICAgICBpZiAocmVjb3JkX2FyY2hfbGlzdF9h
ZGRfcmVnIChpci5yZWdjYWNoZSwgSTM4Nl9FRkxBR1NfUkVHTlVNKSkKLQly
ZXR1cm4gLTE7CisgICAgICAgIEkzODZfUkVDT1JEX0FSQ0hfTElTVF9BRERf
UkVHIChYODZfUkVDT1JEX1JFQ1hfUkVHTlVNKTsKKyAgICAgIEkzODZfUkVD
T1JEX0FSQ0hfTElTVF9BRERfUkVHIChYODZfUkVDT1JEX0VGTEFHU19SRUdO
VU0pOwogICAgICAgYnJlYWs7CiAKLSAgICAgIC8qIGNtcHNTICovCi0gICAg
Y2FzZSAweGE2OgotICAgIGNhc2UgMHhhNzoKLSAgICAgIGlmIChyZWNvcmRf
YXJjaF9saXN0X2FkZF9yZWcgKGlyLnJlZ2NhY2hlLCBJMzg2X0VESV9SRUdO
VU0pKQotCXJldHVybiAtMTsKLSAgICAgIGlmIChyZWNvcmRfYXJjaF9saXN0
X2FkZF9yZWcgKGlyLnJlZ2NhY2hlLCBJMzg2X0VTSV9SRUdOVU0pKQotCXJl
dHVybiAtMTsKKyAgICAgIC8qIG91dHNTICovCisgICAgY2FzZSAweDZlOgor
ICAgIGNhc2UgMHg2ZjoKKyAgICAgIEkzODZfUkVDT1JEX0FSQ0hfTElTVF9B
RERfUkVHIChYODZfUkVDT1JEX1JFU0lfUkVHTlVNKTsKICAgICAgIGlmIChw
cmVmaXhlcyAmIChQUkVGSVhfUkVQWiB8IFBSRUZJWF9SRVBOWikpCi0Jewot
CSAgaWYgKHJlY29yZF9hcmNoX2xpc3RfYWRkX3JlZyAoaXIucmVnY2FjaGUs
IEkzODZfRUNYX1JFR05VTSkpCi0JICAgIHJldHVybiAtMTsKLQl9Ci0gICAg
ICBpZiAocmVjb3JkX2FyY2hfbGlzdF9hZGRfcmVnIChpci5yZWdjYWNoZSwg
STM4Nl9FRkxBR1NfUkVHTlVNKSkKLQlyZXR1cm4gLTE7CisgICAgICAgIEkz
ODZfUkVDT1JEX0FSQ0hfTElTVF9BRERfUkVHIChYODZfUkVDT1JEX1JFQ1hf
UkVHTlVNKTsKKyAgICAgIEkzODZfUkVDT1JEX0FSQ0hfTElTVF9BRERfUkVH
IChYODZfUkVDT1JEX0VGTEFHU19SRUdOVU0pOwogICAgICAgYnJlYWs7CiAK
ICAgICAgIC8qIHBvcnQgSS9PICovCkBAIC00NDkzLDggKzQ1MzEsOCBAQCBy
ZXN3aXRjaDoKICAgICBjYXNlIDB4ZTU6CiAgICAgY2FzZSAweGVjOgogICAg
IGNhc2UgMHhlZDoKLSAgICAgIGlmIChyZWNvcmRfYXJjaF9saXN0X2FkZF9y
ZWcgKGlyLnJlZ2NhY2hlLCBJMzg2X0VBWF9SRUdOVU0pKQotCXJldHVybiAt
MTsKKyAgICAgIEkzODZfUkVDT1JEX0FSQ0hfTElTVF9BRERfUkVHIChYODZf
UkVDT1JEX0VGTEFHU19SRUdOVU0pOworICAgICAgSTM4Nl9SRUNPUkRfQVJD
SF9MSVNUX0FERF9SRUcgKFg4Nl9SRUNPUkRfUkVBWF9SRUdOVU0pOwogICAg
ICAgYnJlYWs7CiAKICAgICBjYXNlIDB4ZTY6CkBAIC00NTA4LDQ4ICs0NTQ2
LDMyIEBAIHJlc3dpdGNoOgogICAgIGNhc2UgMHhjMjoKICAgICAgIC8qIHJl
dCAqLwogICAgIGNhc2UgMHhjMzoKKyAgICAgIEkzODZfUkVDT1JEX0FSQ0hf
TElTVF9BRERfUkVHIChYODZfUkVDT1JEX1JFU1BfUkVHTlVNKTsKKyAgICAg
IEkzODZfUkVDT1JEX0FSQ0hfTElTVF9BRERfUkVHIChYODZfUkVDT1JEX0VG
TEFHU19SRUdOVU0pOworICAgICAgYnJlYWs7CisKICAgICAgIC8qIGxyZXQg
aW0gKi8KICAgICBjYXNlIDB4Y2E6CiAgICAgICAvKiBscmV0ICovCiAgICAg
Y2FzZSAweGNiOgotICAgICAgaWYgKHJlY29yZF9hcmNoX2xpc3RfYWRkX3Jl
ZyAoaXIucmVnY2FjaGUsIEkzODZfRVNQX1JFR05VTSkpCi0JcmV0dXJuIC0x
OwotICAgICAgaWYgKHJlY29yZF9hcmNoX2xpc3RfYWRkX3JlZyAoaXIucmVn
Y2FjaGUsIEkzODZfQ1NfUkVHTlVNKSkKLQlyZXR1cm4gLTE7Ci0gICAgICBi
cmVhazsKLQogICAgICAgLyogaXJldCAqLwogICAgIGNhc2UgMHhjZjoKLSAg
ICAgIGlmIChyZWNvcmRfYXJjaF9saXN0X2FkZF9yZWcgKGlyLnJlZ2NhY2hl
LCBJMzg2X0VTUF9SRUdOVU0pKQotCXJldHVybiAtMTsKLSAgICAgIGlmIChy
ZWNvcmRfYXJjaF9saXN0X2FkZF9yZWcgKGlyLnJlZ2NhY2hlLCBJMzg2X0NT
X1JFR05VTSkpCi0JcmV0dXJuIC0xOwotICAgICAgaWYgKHJlY29yZF9hcmNo
X2xpc3RfYWRkX3JlZyAoaXIucmVnY2FjaGUsIEkzODZfRUZMQUdTX1JFR05V
TSkpCi0JcmV0dXJuIC0xOworICAgICAgSTM4Nl9SRUNPUkRfQVJDSF9MSVNU
X0FERF9SRUcgKFg4Nl9SRUNPUkRfQ1NfUkVHTlVNKTsKKyAgICAgIEkzODZf
UkVDT1JEX0FSQ0hfTElTVF9BRERfUkVHIChYODZfUkVDT1JEX1JFU1BfUkVH
TlVNKTsKKyAgICAgIEkzODZfUkVDT1JEX0FSQ0hfTElTVF9BRERfUkVHIChY
ODZfUkVDT1JEX0VGTEFHU19SRUdOVU0pOwogICAgICAgYnJlYWs7CiAKICAg
ICAgIC8qIGNhbGwgaW0gKi8KICAgICBjYXNlIDB4ZTg6Ci0gICAgICBpZiAo
cmVjb3JkX2FyY2hfbGlzdF9hZGRfcmVnIChpci5yZWdjYWNoZSwgSTM4Nl9F
U1BfUkVHTlVNKSkKLQlyZXR1cm4gLTE7Ci0gICAgICByZWdjYWNoZV9yYXdf
cmVhZCAoaXIucmVnY2FjaGUsIEkzODZfRVNQX1JFR05VTSwKLQkJCSAoZ2Ri
X2J5dGUgKikgJiB0bXB1MzIpOwotICAgICAgaWYgKHJlY29yZF9hcmNoX2xp
c3RfYWRkX21lbQotCSAgKChDT1JFX0FERFIpIHRtcHUzMiAtICgxIDw8IChp
ci5kZmxhZyArIDEpKSwgKDEgPDwgKGlyLmRmbGFnICsgMSkpKSkKLQlyZXR1
cm4gLTE7CisgICAgICBpZiAoaTM4Nl9yZWNvcmRfcHVzaCAoJmlyLCAxIDw8
IChpci5kZmxhZyArIDEpKSkKKyAgICAgICAgcmV0dXJuIC0xOwogICAgICAg
YnJlYWs7CiAKICAgICAgIC8qIGxjYWxsIGltICovCiAgICAgY2FzZSAweDlh
OgotICAgICAgaWYgKHJlY29yZF9hcmNoX2xpc3RfYWRkX3JlZyAoaXIucmVn
Y2FjaGUsIEkzODZfQ1NfUkVHTlVNKSkKLQlyZXR1cm4gLTE7Ci0gICAgICBp
ZiAocmVjb3JkX2FyY2hfbGlzdF9hZGRfcmVnIChpci5yZWdjYWNoZSwgSTM4
Nl9FU1BfUkVHTlVNKSkKLQlyZXR1cm4gLTE7Ci0gICAgICByZWdjYWNoZV9y
YXdfcmVhZCAoaXIucmVnY2FjaGUsIEkzODZfRVNQX1JFR05VTSwKLQkJCSAo
Z2RiX2J5dGUgKikgJiB0bXB1MzIpOwotICAgICAgaWYgKHJlY29yZF9hcmNo
X2xpc3RfYWRkX21lbQotCSAgKChDT1JFX0FERFIpIHRtcHUzMiAtICgxIDw8
IChpci5kZmxhZyArIDIpKSwgKDEgPDwgKGlyLmRmbGFnICsgMikpKSkKLQly
ZXR1cm4gLTE7CisgICAgICBJMzg2X1JFQ09SRF9BUkNIX0xJU1RfQUREX1JF
RyAoWDg2X1JFQ09SRF9DU19SRUdOVU0pOworICAgICAgaWYgKGkzODZfcmVj
b3JkX3B1c2ggKCZpciwgMSA8PCAoaXIuZGZsYWcgKyAxKSkpCisgICAgICAg
IHJldHVybiAtMTsKICAgICAgIGJyZWFrOwogCiAgICAgICAvKiBqbXAgaW0g
Ki8KQEAgLTQ2MTEsMTQgKzQ2MzMsMTMgQEAgcmVzd2l0Y2g6CiAgICAgY2Fz
ZSAweDBmOWQ6CiAgICAgY2FzZSAweDBmOWU6CiAgICAgY2FzZSAweDBmOWY6
CisgICAgICBJMzg2X1JFQ09SRF9BUkNIX0xJU1RfQUREX1JFRyAoWDg2X1JF
Q09SRF9FRkxBR1NfUkVHTlVNKTsKICAgICAgIGlyLm90ID0gT1RfQllURTsK
ICAgICAgIGlmIChpMzg2X3JlY29yZF9tb2RybSAoJmlyKSkKIAlyZXR1cm4g
LTE7CiAgICAgICBpZiAoaXIubW9kID09IDMpCi0JewotCSAgaWYgKHJlY29y
ZF9hcmNoX2xpc3RfYWRkX3JlZyAoaXIucmVnY2FjaGUsIGlyLnJtICYgMHgz
KSkKLQkgICAgcmV0dXJuIC0xOwotCX0KKyAgICAgICAgSTM4Nl9SRUNPUkRf
QVJDSF9MSVNUX0FERF9SRUcgKGlyLnJleF9iID8gKGlyLnJtIHwgaXIucmV4
X2IpOgorICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAg
ICAgICAgICAgICAoaXIucm0gJiAweDMpKTsKICAgICAgIGVsc2UKIAl7CiAJ
ICBpZiAoaTM4Nl9yZWNvcmRfbGVhX21vZHJtICgmaXIpKQpAQCAtNDY0NSwz
NCArNDY2NiwzMyBAQCByZXN3aXRjaDoKICAgICBjYXNlIDB4MGY0ZjoKICAg
ICAgIGlmIChpMzg2X3JlY29yZF9tb2RybSAoJmlyKSkKIAlyZXR1cm4gLTE7
CisgICAgICBpci5yZWcgfD0gcmV4X3I7CiAgICAgICBpZiAoaXIuZGZsYWcg
PT0gT1RfQllURSkKIAlpci5yZWcgJj0gMHgzOwotICAgICAgaWYgKHJlY29y
ZF9hcmNoX2xpc3RfYWRkX3JlZyAoaXIucmVnY2FjaGUsIGlyLnJlZyAmIDB4
MykpCi0JcmV0dXJuIC0xOworICAgICAgSTM4Nl9SRUNPUkRfQVJDSF9MSVNU
X0FERF9SRUcgKGlyLnJlZyk7CiAgICAgICBicmVhazsKIAogICAgICAgLyog
ZmxhZ3MgKi8KICAgICAgIC8qIHB1c2hmICovCiAgICAgY2FzZSAweDljOgot
ICAgICAgaWYgKHJlY29yZF9hcmNoX2xpc3RfYWRkX3JlZyAoaXIucmVnY2Fj
aGUsIEkzODZfRVNQX1JFR05VTSkpCi0JcmV0dXJuIC0xOwotICAgICAgcmVn
Y2FjaGVfcmF3X3JlYWQgKGlyLnJlZ2NhY2hlLCBJMzg2X0VTUF9SRUdOVU0s
Ci0JCQkgKGdkYl9ieXRlICopICYgdG1wdTMyKTsKLSAgICAgIGlmIChyZWNv
cmRfYXJjaF9saXN0X2FkZF9tZW0KLQkgICgoQ09SRV9BRERSKSB0bXB1MzIg
LSAoMSA8PCAoaXIuZGZsYWcgKyAxKSksICgxIDw8IChpci5kZmxhZyArIDEp
KSkpCi0JcmV0dXJuIC0xOworICAgICAgSTM4Nl9SRUNPUkRfQVJDSF9MSVNU
X0FERF9SRUcgKFg4Nl9SRUNPUkRfRUZMQUdTX1JFR05VTSk7CisgICAgICBp
ZiAoaTM4Nl9yZWNvcmRfcHVzaCAoJmlyLCAxIDw8IChpci5kZmxhZyArIDEp
KSkKKyAgICAgICAgcmV0dXJuIC0xOwogICAgICAgYnJlYWs7CiAKICAgICAg
IC8qIHBvcGYgKi8KICAgICBjYXNlIDB4OWQ6Ci0gICAgICBpZiAocmVjb3Jk
X2FyY2hfbGlzdF9hZGRfcmVnIChpci5yZWdjYWNoZSwgSTM4Nl9FU1BfUkVH
TlVNKSkKLQlyZXR1cm4gLTE7Ci0gICAgICBpZiAocmVjb3JkX2FyY2hfbGlz
dF9hZGRfcmVnIChpci5yZWdjYWNoZSwgSTM4Nl9FRkxBR1NfUkVHTlVNKSkK
LQlyZXR1cm4gLTE7CisgICAgICBJMzg2X1JFQ09SRF9BUkNIX0xJU1RfQURE
X1JFRyAoWDg2X1JFQ09SRF9SRVNQX1JFR05VTSk7CisgICAgICBJMzg2X1JF
Q09SRF9BUkNIX0xJU1RfQUREX1JFRyAoWDg2X1JFQ09SRF9FRkxBR1NfUkVH
TlVNKTsKICAgICAgIGJyZWFrOwogCiAgICAgICAvKiBzYWhmICovCiAgICAg
Y2FzZSAweDllOgorICAgICAgaWYgKGlyLnJlZ21hcFtYODZfUkVDT1JEX1I4
X1JFR05VTV0pCisgICAgICAgIHsKKyAgICAgICAgICBpci5hZGRyIC09IDE7
CisgICAgICAgICAgZ290byBub19zdXBwb3J0OworICAgICAgICB9CiAgICAg
ICAvKiBjbWMgKi8KICAgICBjYXNlIDB4ZjU6CiAgICAgICAvKiBjbGMgKi8K
QEAgLTQ2ODMsNjYgKzQ3MDMsOTUgQEAgcmVzd2l0Y2g6CiAgICAgY2FzZSAw
eGZjOgogICAgICAgLyogc3RkICovCiAgICAgY2FzZSAweGZkOgotICAgICAg
aWYgKHJlY29yZF9hcmNoX2xpc3RfYWRkX3JlZyAoaXIucmVnY2FjaGUsIEkz
ODZfRUZMQUdTX1JFR05VTSkpCi0JcmV0dXJuIC0xOworICAgICAgSTM4Nl9S
RUNPUkRfQVJDSF9MSVNUX0FERF9SRUcgKFg4Nl9SRUNPUkRfRUZMQUdTX1JF
R05VTSk7CiAgICAgICBicmVhazsKIAogICAgICAgLyogbGFoZiAqLwogICAg
IGNhc2UgMHg5ZjoKLSAgICAgIGlmIChyZWNvcmRfYXJjaF9saXN0X2FkZF9y
ZWcgKGlyLnJlZ2NhY2hlLCBJMzg2X0VBWF9SRUdOVU0pKQotCXJldHVybiAt
MTsKKyAgICAgIGlmIChpci5yZWdtYXBbWDg2X1JFQ09SRF9SOF9SRUdOVU1d
KQorICAgICAgICB7CisgICAgICAgICAgaXIuYWRkciAtPSAxOworICAgICAg
ICAgIGdvdG8gbm9fc3VwcG9ydDsKKyAgICAgICAgfQorICAgICAgSTM4Nl9S
RUNPUkRfQVJDSF9MSVNUX0FERF9SRUcgKFg4Nl9SRUNPUkRfRUZMQUdTX1JF
R05VTSk7CisgICAgICBJMzg2X1JFQ09SRF9BUkNIX0xJU1RfQUREX1JFRyAo
WDg2X1JFQ09SRF9SRUFYX1JFR05VTSk7CiAgICAgICBicmVhazsKIAogICAg
ICAgLyogYml0IG9wZXJhdGlvbnMgKi8KICAgICAgIC8qIGJ0L2J0cy9idHIv
YnRjIEd2LCBpbSAqLwogICAgIGNhc2UgMHgwZmJhOgotICAgICAgLyogYnRz
ICovCi0gICAgY2FzZSAweDBmYWI6Ci0gICAgICAvKiBidHIgKi8KLSAgICBj
YXNlIDB4MGZiMzoKLSAgICAgIC8qIGJ0YyAqLwotICAgIGNhc2UgMHgwZmJi
OgogICAgICAgaXIub3QgPSBpci5kZmxhZyArIE9UX1dPUkQ7CiAgICAgICBp
ZiAoaTM4Nl9yZWNvcmRfbW9kcm0gKCZpcikpCiAJcmV0dXJuIC0xOwogICAg
ICAgaWYgKGlyLnJlZyA8IDQpCiAJewotCSAgaXIuYWRkciAtPSAzOworCSAg
aXIuYWRkciAtPSAyOwogCSAgb3Bjb2RlID0gb3Bjb2RlIDw8IDggfCBpci5t
b2RybTsKIAkgIGdvdG8gbm9fc3VwcG9ydDsKIAl9Ci0gICAgICBpci5yZWcg
LT0gNDsKLSAgICAgIGlmIChpci5yZWcgIT0gMCkKKyAgICAgIGlmIChpci5y
ZWcgIT0gNCkKIAl7Ci0JICBpZiAoaXIubW9kICE9IDMpCi0JICAgIHsKLQkg
ICAgICBpZiAoaTM4Nl9yZWNvcmRfbGVhX21vZHJtICgmaXIpKQotCQlyZXR1
cm4gLTE7Ci0JICAgIH0KKyAgICAgICAgICBpZiAoaXIubW9kID09IDMpCisg
ICAgICAgICAgICBJMzg2X1JFQ09SRF9BUkNIX0xJU1RfQUREX1JFRyAoaXIu
cm0gfCBpci5yZXhfYik7CiAJICBlbHNlCiAJICAgIHsKLQkgICAgICBpZiAo
cmVjb3JkX2FyY2hfbGlzdF9hZGRfcmVnIChpci5yZWdjYWNoZSwgaXIucm0p
KQorCSAgICAgIGlmIChpMzg2X3JlY29yZF9sZWFfbW9kcm0gKCZpcikpCiAJ
CXJldHVybiAtMTsKIAkgICAgfQogCX0KLSAgICAgIGlmIChyZWNvcmRfYXJj
aF9saXN0X2FkZF9yZWcgKGlyLnJlZ2NhY2hlLCBJMzg2X0VGTEFHU19SRUdO
VU0pKQotCXJldHVybiAtMTsKKyAgICAgIEkzODZfUkVDT1JEX0FSQ0hfTElT
VF9BRERfUkVHIChYODZfUkVDT1JEX0VGTEFHU19SRUdOVU0pOwogICAgICAg
YnJlYWs7CiAKICAgICAgIC8qIGJ0IEd2LCBFdiAqLwogICAgIGNhc2UgMHgw
ZmEzOgotICAgICAgaWYgKHJlY29yZF9hcmNoX2xpc3RfYWRkX3JlZyAoaXIu
cmVnY2FjaGUsIEkzODZfRUZMQUdTX1JFR05VTSkpCi0JcmV0dXJuIC0xOwor
ICAgICAgSTM4Nl9SRUNPUkRfQVJDSF9MSVNUX0FERF9SRUcgKFg4Nl9SRUNP
UkRfRUZMQUdTX1JFR05VTSk7CisgICAgICBicmVhazsKKworICAgICAgLyog
YnRzICovCisgICAgY2FzZSAweDBmYWI6CisgICAgICAvKiBidHIgKi8KKyAg
ICBjYXNlIDB4MGZiMzoKKyAgICAgIC8qIGJ0YyAqLworICAgIGNhc2UgMHgw
ZmJiOgorICAgICAgaXIub3QgPSBpci5kZmxhZyArIE9UX1dPUkQ7CisgICAg
ICBpZiAoaTM4Nl9yZWNvcmRfbW9kcm0gKCZpcikpCisgICAgICAgIHJldHVy
biAtMTsKKyAgICAgIGlmIChpci5tb2QgPT0gMykKKyAgICAgICAgSTM4Nl9S
RUNPUkRfQVJDSF9MSVNUX0FERF9SRUcgKGlyLnJtIHwgaXIucmV4X2IpOwor
ICAgICAgZWxzZQorICAgICAgICB7CisgICAgICAgICAgdWludDY0X3QgdG1w
dTY0OworICAgICAgICAgIGlmIChpMzg2X3JlY29yZF9sZWFfbW9kcm1fYWRk
ciAoJmlyLCAmdG1wdTY0KSkKKyAgICAgICAgICAgIHJldHVybiAtMTsKKyAg
ICAgICAgICByZWdjYWNoZV9yYXdfcmVhZF91bnNpZ25lZCAoaXIucmVnY2Fj
aGUsCisgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgIGly
LnJlZ21hcFtpci5yZWcgfCByZXhfcl0sCisgICAgICAgICAgICAgICAgICAg
ICAgICAgICAgICAgICAgICAgICZ0bXB1bG9uZ2VzdCk7CisgICAgICAgICAg
c3dpdGNoIChpci5kZmxhZykKKyAgICAgICAgICAgIHsKKyAgICAgICAgICAg
IGNhc2UgMDoKKyAgICAgICAgICAgICAgdG1wdTY0ICs9ICgoaW50MTZfdCkg
dG1wdWxvbmdlc3QgPj4gNCkgPDwgNDsKKyAgICAgICAgICAgICAgYnJlYWs7
CisgICAgICAgICAgICBjYXNlIDE6CisgICAgICAgICAgICAgIHRtcHU2NCAr
PSAoKGludDMyX3QpIHRtcHVsb25nZXN0ID4+IDUpIDw8IDU7CisgICAgICAg
ICAgICAgIGJyZWFrOworICAgICAgICAgICAgY2FzZSAyOgorICAgICAgICAg
ICAgICB0bXB1NjQgKz0gKChpbnQ2NF90KSB0bXB1bG9uZ2VzdCA+PiA2KSA8
PCA2OworICAgICAgICAgICAgICBicmVhazsKKyAgICAgICAgICAgIH0KKyAg
ICAgICAgICBpZiAocmVjb3JkX2FyY2hfbGlzdF9hZGRfbWVtICh0bXB1NjQs
IDEgPDwgaXIub3QpKQorICAgICAgICAgICAgcmV0dXJuIC0xOworICAgICAg
ICAgIGlmIChpMzg2X3JlY29yZF9sZWFfbW9kcm0gKCZpcikpCisgICAgICAg
ICAgICByZXR1cm4gLTE7CisgICAgICAgIH0KKyAgICAgIEkzODZfUkVDT1JE
X0FSQ0hfTElTVF9BRERfUkVHIChYODZfUkVDT1JEX0VGTEFHU19SRUdOVU0p
OwogICAgICAgYnJlYWs7CiAKICAgICAgIC8qIGJzZiAqLwogICAgIGNhc2Ug
MHgwZmJjOgogICAgICAgLyogYnNyICovCiAgICAgY2FzZSAweDBmYmQ6Ci0g
ICAgICBpZiAocmVjb3JkX2FyY2hfbGlzdF9hZGRfcmVnIChpci5yZWdjYWNo
ZSwgaXIucmVnKSkKLQlyZXR1cm4gLTE7Ci0gICAgICBpZiAocmVjb3JkX2Fy
Y2hfbGlzdF9hZGRfcmVnIChpci5yZWdjYWNoZSwgSTM4Nl9FRkxBR1NfUkVH
TlVNKSkKLQlyZXR1cm4gLTE7CisgICAgICBJMzg2X1JFQ09SRF9BUkNIX0xJ
U1RfQUREX1JFRyAoaXIucmVnIHwgcmV4X3IpOworICAgICAgSTM4Nl9SRUNP
UkRfQVJDSF9MSVNUX0FERF9SRUcgKFg4Nl9SRUNPUkRfRUZMQUdTX1JFR05V
TSk7CiAgICAgICBicmVhazsKIAogICAgICAgLyogYmNkICovCkBAIC00NzU4
LDEwICs0ODA3LDEzIEBAIHJlc3dpdGNoOgogICAgIGNhc2UgMHhkNDoKICAg
ICAgIC8qIGFhZCAqLwogICAgIGNhc2UgMHhkNToKLSAgICAgIGlmIChyZWNv
cmRfYXJjaF9saXN0X2FkZF9yZWcgKGlyLnJlZ2NhY2hlLCBJMzg2X0VBWF9S
RUdOVU0pKQotCXJldHVybiAtMTsKLSAgICAgIGlmIChyZWNvcmRfYXJjaF9s
aXN0X2FkZF9yZWcgKGlyLnJlZ2NhY2hlLCBJMzg2X0VGTEFHU19SRUdOVU0p
KQotCXJldHVybiAtMTsKKyAgICAgIGlmIChpci5yZWdtYXBbWDg2X1JFQ09S
RF9SOF9SRUdOVU1dKQorICAgICAgICB7CisgICAgICAgICAgaXIuYWRkciAt
PSAxOworICAgICAgICAgIGdvdG8gbm9fc3VwcG9ydDsKKyAgICAgICAgfQor
ICAgICAgSTM4Nl9SRUNPUkRfQVJDSF9MSVNUX0FERF9SRUcgKFg4Nl9SRUNP
UkRfUkVBWF9SRUdOVU0pOworICAgICAgSTM4Nl9SRUNPUkRfQVJDSF9MSVNU
X0FERF9SRUcgKFg4Nl9SRUNPUkRfRUZMQUdTX1JFR05VTSk7CiAgICAgICBi
cmVhazsKIAogICAgICAgLyogbWlzYyAqLwpAQCAtNDg1MywxNiArNDkwNSwx
OCBAQCByZXN3aXRjaDoKICAgICBjYXNlIDB4MGZjZDoKICAgICBjYXNlIDB4
MGZjZToKICAgICBjYXNlIDB4MGZjZjoKLSAgICAgIGlmIChyZWNvcmRfYXJj
aF9saXN0X2FkZF9yZWcgKGlyLnJlZ2NhY2hlLCBvcGNvZGUgJiA3KSkKLQly
ZXR1cm4gLTE7CisgICAgICBJMzg2X1JFQ09SRF9BUkNIX0xJU1RfQUREX1JF
RyAoKG9wY29kZSAmIDcpIHwgaXIucmV4X2IpOwogICAgICAgYnJlYWs7CiAK
ICAgICAgIC8qIHNhbGMgKi8KICAgICBjYXNlIDB4ZDY6Ci0gICAgICBpZiAo
cmVjb3JkX2FyY2hfbGlzdF9hZGRfcmVnIChpci5yZWdjYWNoZSwgSTM4Nl9F
QVhfUkVHTlVNKSkKLQlyZXR1cm4gLTE7Ci0gICAgICBpZiAocmVjb3JkX2Fy
Y2hfbGlzdF9hZGRfcmVnIChpci5yZWdjYWNoZSwgSTM4Nl9FRkxBR1NfUkVH
TlVNKSkKLQlyZXR1cm4gLTE7CisgICAgICBpZiAoaXIucmVnbWFwW1g4Nl9S
RUNPUkRfUjhfUkVHTlVNXSkKKyAgICAgICAgeworICAgICAgICAgIGlyLmFk
ZHIgLT0gMTsKKyAgICAgICAgICBnb3RvIG5vX3N1cHBvcnQ7CisgICAgICAg
IH0KKyAgICAgIEkzODZfUkVDT1JEX0FSQ0hfTElTVF9BRERfUkVHIChYODZf
UkVDT1JEX1JFQVhfUkVHTlVNKTsKKyAgICAgIEkzODZfUkVDT1JEX0FSQ0hf
TElTVF9BRERfUkVHIChYODZfUkVDT1JEX0VGTEFHU19SRUdOVU0pOwogICAg
ICAgYnJlYWs7CiAKICAgICAgIC8qIGxvb3BueiAqLwpAQCAtNDg3Myw4ICs0
OTI3LDggQEAgcmVzd2l0Y2g6CiAgICAgY2FzZSAweGUyOgogICAgICAgLyog
amVjeHogKi8KICAgICBjYXNlIDB4ZTM6Ci0gICAgICBpZiAocmVjb3JkX2Fy
Y2hfbGlzdF9hZGRfcmVnIChpci5yZWdjYWNoZSwgSTM4Nl9FQ1hfUkVHTlVN
KSkKLQlyZXR1cm4gLTE7CisgICAgICBJMzg2X1JFQ09SRF9BUkNIX0xJU1Rf
QUREX1JFRyAoWDg2X1JFQ09SRF9SRUNYX1JFR05VTSk7CisgICAgICBJMzg2
X1JFQ09SRF9BUkNIX0xJU1RfQUREX1JFRyAoWDg2X1JFQ09SRF9FRkxBR1Nf
UkVHTlVNKTsKICAgICAgIGJyZWFrOwogCiAgICAgICAvKiB3cm1zciAqLwpA
QCAtNDkwNSw2ICs0OTU5LDExIEBAIHJlc3dpdGNoOgogICAgIGNhc2UgMHgw
ZjM0OgogICAgICAgewogCWludCByZXQ7CisgICAgICAgIGlmIChpci5yZWdt
YXBbWDg2X1JFQ09SRF9SOF9SRUdOVU1dKQorICAgICAgICAgIHsKKyAgICAg
ICAgICAgIGlyLmFkZHIgLT0gMjsKKyAgICAgICAgICAgIGdvdG8gbm9fc3Vw
cG9ydDsKKyAgICAgICAgICB9CiAJaWYgKGdkYmFyY2hfdGRlcCAoZ2RiYXJj
aCktPmkzODZfc3lzZW50ZXJfcmVjb3JkID09IE5VTEwpCiAJICB7CiAJICAg
IHByaW50Zl91bmZpbHRlcmVkIChfKCJQcm9jZXNzIHJlY29yZCBkb2Vzbid0
IHN1cHBvcnQgIgpAQCAtNDkyNiwxNiArNDk4NSwzNyBAQCByZXN3aXRjaDoK
ICAgICAgIGdvdG8gbm9fc3VwcG9ydDsKICAgICAgIGJyZWFrOwogCisgICAg
ICAvKiBzeXNjYWxsICovCisgICAgY2FzZSAweDBmMDU6CisgICAgICB7CisJ
aW50IHJldDsKKwlpZiAoZ2RiYXJjaF90ZGVwIChnZGJhcmNoKS0+aTM4Nl9z
eXNjYWxsX3JlY29yZCA9PSBOVUxMKQorCSAgeworCSAgICBwcmludGZfdW5m
aWx0ZXJlZCAoXygiUHJvY2VzcyByZWNvcmQgZG9lc24ndCBzdXBwb3J0ICIK
KwkJCQkgImluc3RydWN0aW9uIHN5c2NhbGwuXG4iKSk7CisJICAgIGlyLmFk
ZHIgLT0gMjsKKwkgICAgZ290byBub19zdXBwb3J0OworCSAgfQorCXJldCA9
IGdkYmFyY2hfdGRlcCAoZ2RiYXJjaCktPmkzODZfc3lzY2FsbF9yZWNvcmQg
KGlyLnJlZ2NhY2hlKTsKKwlpZiAocmV0KQorCSAgcmV0dXJuIHJldDsKKyAg
ICAgIH0KKyAgICAgIGJyZWFrOworCisgICAgICAvKiBzeXNyZXQgKi8KKyAg
ICBjYXNlIDB4MGYwNzoKKyAgICAgIHByaW50Zl91bmZpbHRlcmVkIChfKCJQ
cm9jZXNzIHJlY29yZCBkb2Vzbid0IHN1cHBvcnQgIgorICAgICAgICAgICAg
ICAgICAgICAgICAgICAgImluc3RydWN0aW9uIHN5c3JldC5cbiIpKTsKKyAg
ICAgIGlyLmFkZHIgLT0gMjsKKyAgICAgIGdvdG8gbm9fc3VwcG9ydDsKKyAg
ICAgIGJyZWFrOworCiAgICAgICAvKiBjcHVpZCAqLwogICAgIGNhc2UgMHgw
ZmEyOgotICAgICAgaWYgKHJlY29yZF9hcmNoX2xpc3RfYWRkX3JlZyAoaXIu
cmVnY2FjaGUsIEkzODZfRUFYX1JFR05VTSkpCi0JcmV0dXJuIC0xOwotICAg
ICAgaWYgKHJlY29yZF9hcmNoX2xpc3RfYWRkX3JlZyAoaXIucmVnY2FjaGUs
IEkzODZfRUNYX1JFR05VTSkpCi0JcmV0dXJuIC0xOwotICAgICAgaWYgKHJl
Y29yZF9hcmNoX2xpc3RfYWRkX3JlZyAoaXIucmVnY2FjaGUsIEkzODZfRURY
X1JFR05VTSkpCi0JcmV0dXJuIC0xOwotICAgICAgaWYgKHJlY29yZF9hcmNo
X2xpc3RfYWRkX3JlZyAoaXIucmVnY2FjaGUsIEkzODZfRUJYX1JFR05VTSkp
Ci0JcmV0dXJuIC0xOworICAgICAgSTM4Nl9SRUNPUkRfQVJDSF9MSVNUX0FE
RF9SRUcgKFg4Nl9SRUNPUkRfUkVBWF9SRUdOVU0pOworICAgICAgSTM4Nl9S
RUNPUkRfQVJDSF9MSVNUX0FERF9SRUcgKFg4Nl9SRUNPUkRfUkVDWF9SRUdO
VU0pOworICAgICAgSTM4Nl9SRUNPUkRfQVJDSF9MSVNUX0FERF9SRUcgKFg4
Nl9SRUNPUkRfUkVEWF9SRUdOVU0pOworICAgICAgSTM4Nl9SRUNPUkRfQVJD
SF9MSVNUX0FERF9SRUcgKFg4Nl9SRUNPUkRfUkVCWF9SRUdOVU0pOwogICAg
ICAgYnJlYWs7CiAKICAgICAgIC8qIGhsdCAqLwpAQCAtNDk1NiwxMCArNTAz
Niw3IEBAIHJlc3dpdGNoOgogCSAgLyogc3RyICovCiAJY2FzZSAxOgogCSAg
aWYgKGlyLm1vZCA9PSAzKQotCSAgICB7Ci0JICAgICAgaWYgKHJlY29yZF9h
cmNoX2xpc3RfYWRkX3JlZyAoaXIucmVnY2FjaGUsIGlyLnJtKSkKLQkJcmV0
dXJuIC0xOwotCSAgICB9CisgICAgICAgICAgICBJMzg2X1JFQ09SRF9BUkNI
X0xJU1RfQUREX1JFRyAoaXIucm0gfCBpci5yZXhfYik7CiAJICBlbHNlCiAJ
ICAgIHsKIAkgICAgICBpci5vdCA9IE9UX1dPUkQ7CkBAIC00OTc2LDggKzUw
NTMsNyBAQCByZXN3aXRjaDoKIAljYXNlIDQ6CiAJICAvKiB2ZXJ3ICovCiAJ
Y2FzZSA1OgotCSAgaWYgKHJlY29yZF9hcmNoX2xpc3RfYWRkX3JlZyAoaXIu
cmVnY2FjaGUsIEkzODZfRUZMQUdTX1JFR05VTSkpCi0JICAgIHJldHVybiAt
MTsKKyAgICAgICAgICBJMzg2X1JFQ09SRF9BUkNIX0xJU1RfQUREX1JFRyAo
WDg2X1JFQ09SRF9FRkxBR1NfUkVHTlVNKTsKIAkgIGJyZWFrOwogCWRlZmF1
bHQ6CiAJICBpci5hZGRyIC09IDM7CkBAIC00OTk1LDcgKzUwNzEsNyBAQCBy
ZXN3aXRjaDoKIAkgIC8qIHNnZHQgKi8KIAljYXNlIDA6CiAJICB7Ci0JICAg
IHVpbnQzMl90IGFkZHI7CisJICAgIHVpbnQ2NF90IHRtcHU2NDsKIAogCSAg
ICBpZiAoaXIubW9kID09IDMpCiAJICAgICAgewpAQCAtNTAwMyw4ICs1MDc5
LDcgQEAgcmVzd2l0Y2g6CiAJCW9wY29kZSA9IG9wY29kZSA8PCA4IHwgaXIu
bW9kcm07CiAJCWdvdG8gbm9fc3VwcG9ydDsKIAkgICAgICB9Ci0KLQkgICAg
aWYgKGlyLm92ZXJyaWRlKQorCSAgICBpZiAoaXIub3ZlcnJpZGUgPj0gMCkK
IAkgICAgICB7CiAJCWlmIChyZWNvcmRfZGVidWcpCiAJCSAgcHJpbnRmX3Vu
ZmlsdGVyZWQgKF8oIlByb2Nlc3MgcmVjb3JkIGlnbm9yZXMgdGhlIG1lbW9y
eSAiCkBAIC01MDE2LDEzICs1MDkxLDIxIEBAIHJlc3dpdGNoOgogCSAgICAg
IH0KIAkgICAgZWxzZQogCSAgICAgIHsKLQkJaWYgKGkzODZfcmVjb3JkX2xl
YV9tb2RybV9hZGRyICgmaXIsICZhZGRyKSkKLQkJICByZXR1cm4gLTE7Ci0J
CWlmIChyZWNvcmRfYXJjaF9saXN0X2FkZF9tZW0gKGFkZHIsIDIpKQorCQlp
ZiAoaTM4Nl9yZWNvcmRfbGVhX21vZHJtX2FkZHIgKCZpciwgJnRtcHU2NCkp
CiAJCSAgcmV0dXJuIC0xOwotCQlhZGRyICs9IDI7Ci0JCWlmIChyZWNvcmRf
YXJjaF9saXN0X2FkZF9tZW0gKGFkZHIsIDQpKQorCQlpZiAocmVjb3JkX2Fy
Y2hfbGlzdF9hZGRfbWVtICh0bXB1NjQsIDIpKQogCQkgIHJldHVybiAtMTsK
KwkJdG1wdTY0ICs9IDI7CisgICAgICAgICAgICAgICAgaWYgKGlyLnJlZ21h
cFtYODZfUkVDT1JEX1I4X1JFR05VTV0pCisgICAgICAgICAgICAgICAgICB7
CisgICAgICAgICAgICAgICAgICAgIGlmIChyZWNvcmRfYXJjaF9saXN0X2Fk
ZF9tZW0gKHRtcHU2NCwgOCkpCisJCSAgICAgIHJldHVybiAtMTsKKyAgICAg
ICAgICAgICAgICAgIH0KKyAgICAgICAgICAgICAgICBlbHNlCisgICAgICAg
ICAgICAgICAgICB7CisgICAgICAgICAgICAgICAgICAgIGlmIChyZWNvcmRf
YXJjaF9saXN0X2FkZF9tZW0gKHRtcHU2NCwgNCkpCisJCSAgICAgIHJldHVy
biAtMTsKKyAgICAgICAgICAgICAgICAgIH0KIAkgICAgICB9CiAJICB9CiAJ
ICBicmVhazsKQEAgLTUwMzYsOCArNTExOSw3IEBAIHJlc3dpdGNoOgogCQkg
IGJyZWFrOwogCQkgIC8qIG13YWl0ICovCiAJCWNhc2UgMToKLQkJICBpZiAo
cmVjb3JkX2FyY2hfbGlzdF9hZGRfcmVnIChpci5yZWdjYWNoZSwgSTM4Nl9F
RkxBR1NfUkVHTlVNKSkKLQkJICAgIHJldHVybiAtMTsKKwkJICBJMzg2X1JF
Q09SRF9BUkNIX0xJU1RfQUREX1JFRyAoWDg2X1JFQ09SRF9FRkxBR1NfUkVH
TlVNKTsKIAkJICBicmVhazsKIAkJZGVmYXVsdDoKIAkJICBpci5hZGRyIC09
IDM7CkBAIC01MDQ5LDcgKzUxMzEsNyBAQCByZXN3aXRjaDoKIAkgIGVsc2UK
IAkgICAgewogCSAgICAgIC8qIHNpZHQgKi8KLQkgICAgICBpZiAoaXIub3Zl
cnJpZGUpCisJICAgICAgaWYgKGlyLm92ZXJyaWRlID49IDApCiAJCXsKIAkJ
ICBpZiAocmVjb3JkX2RlYnVnKQogCQkgICAgcHJpbnRmX3VuZmlsdGVyZWQg
KF8oIlByb2Nlc3MgcmVjb3JkIGlnbm9yZXMgdGhlIG1lbW9yeSAiCkBAIC01
MDYxLDE1ICs1MTQzLDIzIEBAIHJlc3dpdGNoOgogCQl9CiAJICAgICAgZWxz
ZQogCQl7Ci0JCSAgdWludDMyX3QgYWRkcjsKKwkJICB1aW50NjRfdCB0bXB1
NjQ7CiAKLQkJICBpZiAoaTM4Nl9yZWNvcmRfbGVhX21vZHJtX2FkZHIgKCZp
ciwgJmFkZHIpKQorCQkgIGlmIChpMzg2X3JlY29yZF9sZWFfbW9kcm1fYWRk
ciAoJmlyLCAmdG1wdTY0KSkKIAkJICAgIHJldHVybiAtMTsKLQkJICBpZiAo
cmVjb3JkX2FyY2hfbGlzdF9hZGRfbWVtIChhZGRyLCAyKSkKKwkJICBpZiAo
cmVjb3JkX2FyY2hfbGlzdF9hZGRfbWVtICh0bXB1NjQsIDIpKQogCQkgICAg
cmV0dXJuIC0xOwogCQkgIGFkZHIgKz0gMjsKLQkJICBpZiAocmVjb3JkX2Fy
Y2hfbGlzdF9hZGRfbWVtIChhZGRyLCA0KSkKLQkJICAgIHJldHVybiAtMTsK
KyAgICAgICAgICAgICAgICAgIGlmIChpci5yZWdtYXBbWDg2X1JFQ09SRF9S
OF9SRUdOVU1dKQorICAgICAgICAgICAgICAgICAgICB7CisgICAgICAgICAg
ICAgICAgICAgICAgaWYgKHJlY29yZF9hcmNoX2xpc3RfYWRkX21lbSAodG1w
dTY0LCA4KSkKKwkJICAgICAgICByZXR1cm4gLTE7CisgICAgICAgICAgICAg
ICAgICAgIH0KKyAgICAgICAgICAgICAgICAgIGVsc2UKKyAgICAgICAgICAg
ICAgICAgICAgeworICAgICAgICAgICAgICAgICAgICAgIGlmIChyZWNvcmRf
YXJjaF9saXN0X2FkZF9tZW0gKHRtcHU2NCwgNCkpCisJCSAgICAgICAgcmV0
dXJuIC0xOworICAgICAgICAgICAgICAgICAgICB9CiAJCX0KIAkgICAgfQog
CSAgYnJlYWs7CkBAIC01MDc3LDkgKzUxNjcsNiBAQCByZXN3aXRjaDoKIAlj
YXNlIDI6CiAJICAvKiBsaWR0ICovCiAJY2FzZSAzOgotCSAgLyogaW52bHBn
ICovCi0JY2FzZSA3OgotCWRlZmF1bHQ6CiAJICBpZiAoaXIubW9kID09IDMp
CiAJICAgIHsKIAkgICAgICBpci5hZGRyIC09IDM7CkBAIC01MDkxLDcgKzUx
NzgsNyBAQCByZXN3aXRjaDoKIAljYXNlIDQ6CiAJICBpZiAoaXIubW9kID09
IDMpCiAJICAgIHsKLQkgICAgICBpZiAocmVjb3JkX2FyY2hfbGlzdF9hZGRf
cmVnIChpci5yZWdjYWNoZSwgaXIucm0pKQorCSAgICAgIGlmIChyZWNvcmRf
YXJjaF9saXN0X2FkZF9yZWcgKGlyLnJlZ2NhY2hlLCBpci5ybSB8IGlyLnJl
eF9iKSkKIAkJcmV0dXJuIC0xOwogCSAgICB9CiAJICBlbHNlCkBAIC01MTAw
LDkgKzUxODcsMzIgQEAgcmVzd2l0Y2g6CiAJICAgICAgaWYgKGkzODZfcmVj
b3JkX2xlYV9tb2RybSAoJmlyKSkKIAkJcmV0dXJuIC0xOwogCSAgICB9CisJ
ICBJMzg2X1JFQ09SRF9BUkNIX0xJU1RfQUREX1JFRyAoWDg2X1JFQ09SRF9F
RkxBR1NfUkVHTlVNKTsKIAkgIGJyZWFrOwogCSAgLyogbG1zdyAqLwogCWNh
c2UgNjoKKwkgIEkzODZfUkVDT1JEX0FSQ0hfTElTVF9BRERfUkVHIChYODZf
UkVDT1JEX0VGTEFHU19SRUdOVU0pOworCSAgYnJlYWs7CisJICAvKiBpbnZs
cGcgKi8KKwljYXNlIDc6CisJICBpZiAoaXIubW9kID09IDMpCisJICAgIHsK
KwkgICAgICBpZiAoaXIucm0gPT0gMCAmJiBpci5yZWdtYXBbWDg2X1JFQ09S
RF9SOF9SRUdOVU1dKQorCSAgICAgICAgSTM4Nl9SRUNPUkRfQVJDSF9MSVNU
X0FERF9SRUcgKFg4Nl9SRUNPUkRfR1NfUkVHTlVNKTsKKwkgICAgICBlbHNl
CisJICAgICAgICB7CisJICAgICAgICAgIGlyLmFkZHIgLT0gMzsKKwkgICAg
ICAgICAgb3Bjb2RlID0gb3Bjb2RlIDw8IDggfCBpci5tb2RybTsKKwkgICAg
ICAgICAgZ290byBub19zdXBwb3J0OworCSAgICAgICAgfQorCSAgICB9CisJ
ICBlbHNlCisJICAgIEkzODZfUkVDT1JEX0FSQ0hfTElTVF9BRERfUkVHIChY
ODZfUkVDT1JEX0VGTEFHU19SRUdOVU0pOworCSAgYnJlYWs7CisJZGVmYXVs
dDoKKwkgIGlyLmFkZHIgLT0gMzsKKwkgIG9wY29kZSA9IG9wY29kZSA8PCA4
IHwgaXIubW9kcm07CisJICBnb3RvIG5vX3N1cHBvcnQ7CiAJICBicmVhazsK
IAl9CiAgICAgICBicmVhazsKQEAgLTUxMTUsMjEgKzUyMjUsMjEgQEAgcmVz
d2l0Y2g6CiAKICAgICAgIC8qIGFycGwgKi8KICAgICBjYXNlIDB4NjM6Ci0g
ICAgICBpci5vdCA9IGlyLmRmbGFnID8gT1RfTE9ORyA6IE9UX1dPUkQ7CiAg
ICAgICBpZiAoaTM4Nl9yZWNvcmRfbW9kcm0gKCZpcikpCiAJcmV0dXJuIC0x
OwotICAgICAgaWYgKGlyLm1vZCAhPSAzKQotCXsKLQkgIGlmIChpMzg2X3Jl
Y29yZF9sZWFfbW9kcm0gKCZpcikpCi0JICAgIHJldHVybiAtMTsKLQl9Cisg
ICAgICBpZiAoaXIubW9kID09IDMgfHwgaXIucmVnbWFwW1g4Nl9SRUNPUkRf
UjhfUkVHTlVNXSkKKyAgICAgICAgeworICAgICAgICAgIEkzODZfUkVDT1JE
X0FSQ0hfTElTVF9BRERfUkVHIChpci5yZWdtYXBbWDg2X1JFQ09SRF9SOF9S
RUdOVU1dPworICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAg
ICAgICAgIChpci5yZWcgfCByZXhfcikgOiBpci5ybSk7CisgICAgICAgIH0K
ICAgICAgIGVsc2UKLQl7Ci0JICBpZiAocmVjb3JkX2FyY2hfbGlzdF9hZGRf
cmVnIChpci5yZWdjYWNoZSwgaXIucm0pKQotCSAgICByZXR1cm4gLTE7Ci0J
fQotICAgICAgaWYgKHJlY29yZF9hcmNoX2xpc3RfYWRkX3JlZyAoaXIucmVn
Y2FjaGUsIEkzODZfRUZMQUdTX1JFR05VTSkpCi0JcmV0dXJuIC0xOworICAg
ICAgICB7CisgICAgICAgICAgaXIub3QgPSBpci5kZmxhZyA/IE9UX0xPTkcg
OiBPVF9XT1JEOworICAgICAgICAgIGlmIChpMzg2X3JlY29yZF9sZWFfbW9k
cm0gKCZpcikpCisgICAgICAgICAgICByZXR1cm4gLTE7CisgICAgICAgIH0K
KyAgICAgIGlmICghaXIucmVnbWFwW1g4Nl9SRUNPUkRfUjhfUkVHTlVNXSkK
KyAgICAgICAgSTM4Nl9SRUNPUkRfQVJDSF9MSVNUX0FERF9SRUcgKFg4Nl9S
RUNPUkRfRUZMQUdTX1JFR05VTSk7CiAgICAgICBicmVhazsKIAogICAgICAg
LyogbGFyICovCkBAIC01MTM4LDEzICs1MjQ4LDE5IEBAIHJlc3dpdGNoOgog
ICAgIGNhc2UgMHgwZjAzOgogICAgICAgaWYgKGkzODZfcmVjb3JkX21vZHJt
ICgmaXIpKQogCXJldHVybiAtMTsKLSAgICAgIGlmIChyZWNvcmRfYXJjaF9s
aXN0X2FkZF9yZWcgKGlyLnJlZ2NhY2hlLCBpci5yZWcpKQotCXJldHVybiAt
MTsKLSAgICAgIGlmIChyZWNvcmRfYXJjaF9saXN0X2FkZF9yZWcgKGlyLnJl
Z2NhY2hlLCBJMzg2X0VGTEFHU19SRUdOVU0pKQotCXJldHVybiAtMTsKKyAg
ICAgIEkzODZfUkVDT1JEX0FSQ0hfTElTVF9BRERfUkVHIChpci5yZWcgfCBy
ZXhfcik7CisgICAgICBJMzg2X1JFQ09SRF9BUkNIX0xJU1RfQUREX1JFRyAo
WDg2X1JFQ09SRF9FRkxBR1NfUkVHTlVNKTsKICAgICAgIGJyZWFrOwogCiAg
ICAgY2FzZSAweDBmMTg6CisgICAgICBpZiAoaTM4Nl9yZWNvcmRfbW9kcm0g
KCZpcikpCisJcmV0dXJuIC0xOworICAgICAgaWYgKGlyLm1vZCA9PSAzICYm
IGlyLnJlZyA9PSAzKQorICAgICAgICB7CisJICBpci5hZGRyIC09IDM7CisJ
ICBvcGNvZGUgPSBvcGNvZGUgPDwgOCB8IGlyLm1vZHJtOworCSAgZ290byBu
b19zdXBwb3J0OworCX0KICAgICAgIGJyZWFrOwogCiAgICAgICAvKiBub3Ag
KG11bHRpIGJ5dGUpICovCkBAIC01MTY1LDcgKzUyODEsNyBAQCByZXN3aXRj
aDoKIAlyZXR1cm4gLTE7CiAgICAgICBpZiAoKGlyLm1vZHJtICYgMHhjMCkg
IT0gMHhjMCkKIAl7Ci0JICBpci5hZGRyIC09IDI7CisJICBpci5hZGRyIC09
IDM7CiAJICBvcGNvZGUgPSBvcGNvZGUgPDwgOCB8IGlyLm1vZHJtOwogCSAg
Z290byBub19zdXBwb3J0OwogCX0KQEAgLTUxNzcsMTYgKzUyOTMsMTIgQEAg
cmVzd2l0Y2g6CiAJY2FzZSA0OgogCWNhc2UgODoKIAkgIGlmIChvcGNvZGUg
JiAyKQotCSAgICB7Ci0JICAgIH0KKwkgICAgSTM4Nl9SRUNPUkRfQVJDSF9M
SVNUX0FERF9SRUcgKFg4Nl9SRUNPUkRfRUZMQUdTX1JFR05VTSk7CiAJICBl
bHNlCi0JICAgIHsKLQkgICAgICBpZiAocmVjb3JkX2FyY2hfbGlzdF9hZGRf
cmVnIChpci5yZWdjYWNoZSwgaXIucm0pKQotCQlyZXR1cm4gLTE7Ci0JICAg
IH0KKyAgICAgICAgICAgIEkzODZfUkVDT1JEX0FSQ0hfTElTVF9BRERfUkVH
IChpci5ybSB8IGlyLnJleF9iKTsKIAkgIGJyZWFrOwogCWRlZmF1bHQ6Ci0J
ICBpci5hZGRyIC09IDI7CisJICBpci5hZGRyIC09IDM7CiAJICBvcGNvZGUg
PSBvcGNvZGUgPDwgOCB8IGlyLm1vZHJtOwogCSAgZ290byBub19zdXBwb3J0
OwogCSAgYnJlYWs7CkBAIC01MjAyLDIyICs1MzE0LDE5IEBAIHJlc3dpdGNo
OgogICAgICAgaWYgKChpci5tb2RybSAmIDB4YzApICE9IDB4YzAgfHwgaXIu
cmVnID09IDQKIAkgIHx8IGlyLnJlZyA9PSA1IHx8IGlyLnJlZyA+PSA4KQog
CXsKLQkgIGlyLmFkZHIgLT0gMjsKKwkgIGlyLmFkZHIgLT0gMzsKIAkgIG9w
Y29kZSA9IG9wY29kZSA8PCA4IHwgaXIubW9kcm07CiAJICBnb3RvIG5vX3N1
cHBvcnQ7CiAJfQogICAgICAgaWYgKG9wY29kZSAmIDIpCi0JewotCX0KKyAg
ICAgICAgSTM4Nl9SRUNPUkRfQVJDSF9MSVNUX0FERF9SRUcgKFg4Nl9SRUNP
UkRfRUZMQUdTX1JFR05VTSk7CiAgICAgICBlbHNlCi0JewotCSAgaWYgKHJl
Y29yZF9hcmNoX2xpc3RfYWRkX3JlZyAoaXIucmVnY2FjaGUsIGlyLnJtKSkK
LQkgICAgcmV0dXJuIC0xOwotCX0KKwlJMzg2X1JFQ09SRF9BUkNIX0xJU1Rf
QUREX1JFRyAoaXIucm0gfCBpci5yZXhfYik7CiAgICAgICBicmVhazsKIAog
ICAgICAgLyogY2x0cyAqLwogICAgIGNhc2UgMHgwZjA2OgorICAgICAgSTM4
Nl9SRUNPUkRfQVJDSF9MSVNUX0FERF9SRUcgKFg4Nl9SRUNPUkRfRUZMQUdT
X1JFR05VTSk7CiAgICAgICBicmVhazsKIAogICAgICAgLyogTU1YL1NTRS9T
U0UyL1BOSSBzdXBwb3J0ICovCkBAIC01MjMyLDkgKzUzNDEsOCBAQCByZXN3
aXRjaDoKICAgICAgIGJyZWFrOwogICAgIH0KIAotLyogSW4gdGhlIGZ1dHVy
ZSwgTWF5YmUgc3RpbGwgbmVlZCB0byBkZWFsIHdpdGggbmVlZF9kYXNtICov
Ci0gIGlmIChyZWNvcmRfYXJjaF9saXN0X2FkZF9yZWcgKGlyLnJlZ2NhY2hl
LCBJMzg2X0VJUF9SRUdOVU0pKQotICAgIHJldHVybiAtMTsKKyAgLyogSW4g
dGhlIGZ1dHVyZSwgTWF5YmUgc3RpbGwgbmVlZCB0byBkZWFsIHdpdGggbmVl
ZF9kYXNtICovCisgIEkzODZfUkVDT1JEX0FSQ0hfTElTVF9BRERfUkVHIChY
ODZfUkVDT1JEX1JFSVBfUkVHTlVNKTsKICAgaWYgKHJlY29yZF9hcmNoX2xp
c3RfYWRkX2VuZCAoKSkKICAgICByZXR1cm4gLTE7CiAKQEAgLTUyNDcsNiAr
NTM1NSwxNSBAQCBub19zdXBwb3J0OgogICByZXR1cm4gLTE7CiB9CiAKK3N0
YXRpYyBjb25zdCBpbnQgaTM4Nl9yZWNvcmRfcmVnbWFwW10gPQoreworICBJ
Mzg2X0VBWF9SRUdOVU0sIEkzODZfRUNYX1JFR05VTSwgSTM4Nl9FRFhfUkVH
TlVNLCBJMzg2X0VCWF9SRUdOVU0sCisgIEkzODZfRVNQX1JFR05VTSwgSTM4
Nl9FQlBfUkVHTlVNLCBJMzg2X0VTSV9SRUdOVU0sIEkzODZfRURJX1JFR05V
TSwKKyAgMCwgMCwgMCwgMCwgMCwgMCwgMCwgMCwKKyAgSTM4Nl9FSVBfUkVH
TlVNLCBJMzg2X0VGTEFHU19SRUdOVU0sIEkzODZfQ1NfUkVHTlVNLCBJMzg2
X1NTX1JFR05VTSwKKyAgSTM4Nl9EU19SRUdOVU0sIEkzODZfRVNfUkVHTlVN
LCBJMzg2X0ZTX1JFR05VTSwgSTM4Nl9HU19SRUdOVU0KK307CisKIAwKIHN0
YXRpYyBzdHJ1Y3QgZ2RiYXJjaCAqCiBpMzg2X2dkYmFyY2hfaW5pdCAoc3Ry
dWN0IGdkYmFyY2hfaW5mbyBpbmZvLCBzdHJ1Y3QgZ2RiYXJjaF9saXN0ICph
cmNoZXMpCkBAIC01MzA3LDYgKzU0MjQsOCBAQCBpMzg2X2dkYmFyY2hfaW5p
dCAoc3RydWN0IGdkYmFyY2hfaW5mbyBpCiAgIHRkZXAtPnNjX3BjX29mZnNl
dCA9IC0xOwogICB0ZGVwLT5zY19zcF9vZmZzZXQgPSAtMTsKIAorICB0ZGVw
LT5yZWNvcmRfcmVnbWFwID0gaTM4Nl9yZWNvcmRfcmVnbWFwOworCiAgIC8q
IFRoZSBmb3JtYXQgdXNlZCBmb3IgYGxvbmcgZG91YmxlJyBvbiBhbG1vc3Qg
YWxsIGkzODYgdGFyZ2V0cyBpcwogICAgICB0aGUgaTM4NyBleHRlbmRlZCBm
bG9hdGluZy1wb2ludCBmb3JtYXQuICBJbiBmYWN0LCBvZiBhbGwgdGFyZ2V0
cwogICAgICBpbiB0aGUgR0NDIDIuOTUgdHJlZSwgb25seSBPU0YvMSBkb2Vz
IGl0IGRpZmZlcmVudCwgYW5kIGluc2lzdHMKLS0tIGEvaTM4Ni10ZGVwLmgK
KysrIGIvaTM4Ni10ZGVwLmgKQEAgLTExMSwxMCArMTExLDE1IEBAIHN0cnVj
dCBnZGJhcmNoX3RkZXAKICAgc3RydWN0IHR5cGUgKmkzODdfZXh0X3R5cGU7
CiAKICAgLyogUHJvY2VzcyByZWNvcmQvcmVwbGF5IHRhcmdldC4gICovCisg
IC8qIFRoZSBtYXAgZm9yIHJlZ2lzdGVycyBiZWNhdXNlIHRoZSBBTUQ2NCdz
IHJlZ2lzdGVycyBvcmRlcgorICAgICBpbiBHREIgaXMgbm90IHNhbWUgYXMg
STM4NiBpbnN0cnVjdGlvbnMuICAqLworICBjb25zdCBpbnQgKnJlY29yZF9y
ZWdtYXA7CiAgIC8qIFBhcnNlIGludHg4MCBhcmdzLiAgKi8KICAgaW50ICgq
aTM4Nl9pbnR4ODBfcmVjb3JkKSAoc3RydWN0IHJlZ2NhY2hlICpyZWdjYWNo
ZSk7CiAgIC8qIFBhcnNlIHN5c2VudGVyIGFyZ3MuICAqLwogICBpbnQgKCpp
Mzg2X3N5c2VudGVyX3JlY29yZCkgKHN0cnVjdCByZWdjYWNoZSAqcmVnY2Fj
aGUpOworICAvKiBQYXJzZSBzeXNjYWxsIGFyZ3MuICAqLworICBpbnQgKCpp
Mzg2X3N5c2NhbGxfcmVjb3JkKSAoc3RydWN0IHJlZ2NhY2hlICpyZWdjYWNo
ZSk7CiB9OwogCiAvKiBGbG9hdGluZy1wb2ludCByZWdpc3RlcnMuICAqLwpA
QCAtMTUxLDYgKzE1NiwzNiBAQCBlbnVtIGkzODZfcmVnbnVtCiAgIEkzODZf
U1QwX1JFR05VTQkJLyogJXN0KDApICovCiB9OwogCisvKiBSZWdpc3RlciBu
dW1iZXJzIG9mIFJFQ09SRF9SRUdNQVAuICAqLworCitlbnVtIHJlY29yZF9p
Mzg2X3JlZ251bQoreworICBYODZfUkVDT1JEX1JFQVhfUkVHTlVNLAorICBY
ODZfUkVDT1JEX1JFQ1hfUkVHTlVNLAorICBYODZfUkVDT1JEX1JFRFhfUkVH
TlVNLAorICBYODZfUkVDT1JEX1JFQlhfUkVHTlVNLAorICBYODZfUkVDT1JE
X1JFU1BfUkVHTlVNLAorICBYODZfUkVDT1JEX1JFQlBfUkVHTlVNLAorICBY
ODZfUkVDT1JEX1JFU0lfUkVHTlVNLAorICBYODZfUkVDT1JEX1JFRElfUkVH
TlVNLAorICBYODZfUkVDT1JEX1I4X1JFR05VTSwKKyAgWDg2X1JFQ09SRF9S
OV9SRUdOVU0sCisgIFg4Nl9SRUNPUkRfUjEwX1JFR05VTSwKKyAgWDg2X1JF
Q09SRF9SMTFfUkVHTlVNLAorICBYODZfUkVDT1JEX1IxMl9SRUdOVU0sCisg
IFg4Nl9SRUNPUkRfUjEzX1JFR05VTSwKKyAgWDg2X1JFQ09SRF9SMTRfUkVH
TlVNLAorICBYODZfUkVDT1JEX1IxNV9SRUdOVU0sCisgIFg4Nl9SRUNPUkRf
UkVJUF9SRUdOVU0sCisgIFg4Nl9SRUNPUkRfRUZMQUdTX1JFR05VTSwKKyAg
WDg2X1JFQ09SRF9DU19SRUdOVU0sCisgIFg4Nl9SRUNPUkRfU1NfUkVHTlVN
LAorICBYODZfUkVDT1JEX0RTX1JFR05VTSwKKyAgWDg2X1JFQ09SRF9FU19S
RUdOVU0sCisgIFg4Nl9SRUNPUkRfRlNfUkVHTlVNLAorICBYODZfUkVDT1JE
X0dTX1JFR05VTSwKK307CisKICNkZWZpbmUgSTM4Nl9OVU1fR1JFR1MJMTYK
ICNkZWZpbmUgSTM4Nl9OVU1fRlJFR1MJMTYKICNkZWZpbmUgSTM4Nl9OVU1f
WFJFR1MgIDkK

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