From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from simark.ca by simark.ca with LMTP id rB9dHFSzIWMKiDkAWB0awg (envelope-from ) for ; Wed, 14 Sep 2022 06:56:20 -0400 Received: by simark.ca (Postfix, from userid 112) id 5FEDB1E112; Wed, 14 Sep 2022 06:56:20 -0400 (EDT) Authentication-Results: simark.ca; dkim=pass (1024-bit key; secure) header.d=sourceware.org header.i=@sourceware.org header.a=rsa-sha256 header.s=default header.b=SUiDnsPy; dkim-atps=neutral X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on simark.ca X-Spam-Level: X-Spam-Status: No, score=-2.0 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI,RDNS_DYNAMIC,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 Received: from sourceware.org (ip-8-43-85-97.sourceware.org [8.43.85.97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by simark.ca (Postfix) with ESMTPS id BA5111E0D5 for ; Wed, 14 Sep 2022 06:56:19 -0400 (EDT) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id D7ABD385843E for ; Wed, 14 Sep 2022 10:56:18 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org D7ABD385843E DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1663152978; bh=gBRTIcl6pebI4hOsWSHjoFJMj+yn5ePbJ/N5CyqjTik=; h=To:Subject:Date:In-Reply-To:References:List-Id:List-Unsubscribe: List-Archive:List-Post:List-Help:List-Subscribe:From:Reply-To:Cc: From; b=SUiDnsPyjiPDr0S87k4r+3BpNLjsR38Z47dupX04N+C7Ryg36+QiMyhnA59tbcX38 k/7XFhRtoC0XWlZre9vvRMZww7SYiiN7Ze6I2tmvWJ6uBAIPIxx1K6lvRVrcJQw4qd f9bSy8LRl1Eu8iyyOD6PHPDAv9VFwLYE5IL84qbk= Received: from mail-sender-0.a4lg.com (mail-sender-0.a4lg.com [IPv6:2401:2500:203:30b:4000:6bfe:4757:0]) by sourceware.org (Postfix) with ESMTPS id 22BE03858D37 for ; Wed, 14 Sep 2022 10:55:58 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 22BE03858D37 Received: from [127.0.0.1] (localhost [127.0.0.1]) by mail-sender-0.a4lg.com (Postfix) with ESMTPSA id 2244B300089; Wed, 14 Sep 2022 10:55:56 +0000 (UTC) To: Tsukasa OI Subject: [PING^1 PATCH 0/1] sim: Fix RISC-V multiply instructions on simulator Date: Wed, 14 Sep 2022 10:55:50 +0000 Message-Id: In-Reply-To: References: Mime-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: gdb-patches@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gdb-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , From: Tsukasa OI via Gdb-patches Reply-To: Tsukasa OI Cc: gdb-patches@sourceware.org Errors-To: gdb-patches-bounces+public-inbox=simark.ca@sourceware.org Sender: "Gdb-patches" NOTE: the cover letter may change each time I ping. Hello, As I describe later, this patchset fixes now-broken RISC-V instruction simulator. I hope this patchset is approved as fast as possible since it's clearly a functional blocker for GDB 13.1. The patch is a PING (1) of . Tracker on GitHub: Previous: 'Zmmul' v5: Due to opcodes changes (to add the 'Zmmul' extension in the commit 0938b032daa5 "RISC-V: Add 'Zmmul' extension in assembler."), the instruction simulator for RISC-V is now broken. For multiply/divide instructions in the 'M' extension, only division / remainder instructions work and **multiply instructions cause a trap**. This is because only one side of my 'Zmmul' patchset is applied and GDB- part of my 'Zmmul' patchset (this) is not approved yet. In the current master, multiply instructions of the RISC-V simulator doesn't work. The cause was simple. The RISC-V simulator supports 'I', 'M' and 'A' extensions and the instruction is identified by those instruction classes: - INSN_CLASS_I (for 'I') - INSN_CLASS_M (for 'M') - INSN_CLASS_A (for 'A') After adding the 'Zmmul' extension, INSN_CLASS_M is splitted to: - INSN_CLASS_ZMMUL (multiply instructions) - INSN_CLASS_M (division instructions) So, the simulator must handle INSN_CLASS_ZMMUL separately. My 'Zmmul' patchset fixed that and I added a testcase (checks whether all RV32M instructions run without any fault) but only opcodes part is applied so it's now broken state for the simulator. This is the simulator part of the original 'Zmmul' patchset (from PATCH v5). Note: To confirm that the simulator is fixed, it requires another patch. Without the patch above, all multiply instructions will still work. Still, testing whether the simulator works with this extension (with `make check-sim') requires it. Regards, Tsukasa Tsukasa OI (1): sim/riscv: Fix RISC-V multiply instructions on the simulator sim/riscv/sim-main.c | 1 + sim/testsuite/riscv/m-ext.s | 18 ++++++++++++++++++ 2 files changed, 19 insertions(+) create mode 100644 sim/testsuite/riscv/m-ext.s base-commit: e959744eca88a4d145f39d5fbf4ab095af0f16b4 -- 2.34.1