From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from simark.ca by simark.ca with LMTP id /t3iBou9DmMmLjAAWB0awg (envelope-from ) for ; Tue, 30 Aug 2022 21:46:51 -0400 Received: by simark.ca (Postfix, from userid 112) id 06FEC1E4A7; Tue, 30 Aug 2022 21:46:51 -0400 (EDT) Authentication-Results: simark.ca; dkim=pass (1024-bit key; secure) header.d=sourceware.org header.i=@sourceware.org header.a=rsa-sha256 header.s=default header.b=EblG+zIV; dkim-atps=neutral X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on simark.ca X-Spam-Level: X-Spam-Status: No, score=-3.0 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 Received: from sourceware.org (server2.sourceware.org [8.43.85.97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by simark.ca (Postfix) with ESMTPS id 739751E222 for ; Tue, 30 Aug 2022 21:46:50 -0400 (EDT) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 2E530383CCF0 for ; Wed, 31 Aug 2022 01:46:47 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 2E530383CCF0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1661910407; bh=CQFkHcz6wKmYEkL0leZLH98XpYs52mPcbbbZmxKe7DM=; h=To:Subject:Date:In-Reply-To:References:List-Id:List-Unsubscribe: List-Archive:List-Post:List-Help:List-Subscribe:From:Reply-To:Cc: From; b=EblG+zIVwHVrfUSkYo4384eLIW+r3O+DaWYFTDXMCMk0BkSdMoCOE1+WTCZP4NbbJ c+DUjAJCcp0gVQaBpKN3QoyyC7PtJF9uVqFVl+ohTsqYIq3Y/tlf/Y70XOLzd8zcOH TCm4YKS1kytPQ/7G8QVj24esMSLjkPf6dn1A8xiM= Received: from mail-sender-0.a4lg.com (mail-sender-0.a4lg.com [IPv6:2401:2500:203:30b:4000:6bfe:4757:0]) by sourceware.org (Postfix) with ESMTPS id 78BDC383CCCB for ; Wed, 31 Aug 2022 01:46:25 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 78BDC383CCCB Received: from [127.0.0.1] (localhost [127.0.0.1]) by mail-sender-0.a4lg.com (Postfix) with ESMTPSA id 255CC300089; Wed, 31 Aug 2022 01:46:22 +0000 (UTC) To: Andrew Burgess , Palmer Dabbelt , Mike Frysinger Subject: [PATCH 0/1] sim: Fix RISC-V multiply instructions on simulator Date: Wed, 31 Aug 2022 01:46:07 +0000 Message-Id: In-Reply-To: References: Mime-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: gdb-patches@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gdb-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , From: Tsukasa OI via Gdb-patches Reply-To: Tsukasa OI Cc: gdb-patches@sourceware.org Errors-To: gdb-patches-bounces+public-inbox=simark.ca@sourceware.org Sender: "Gdb-patches" Hi, Due to opcodes changes (to add the 'Zmmul' extension in the commit 0938b032daa5 "RISC-V: Add 'Zmmul' extension in assembler."), the instruction simulator for RISC-V is now broken. This is because only one side of my 'Zmmul' patchset is applied. Tracker on GitHub: Previous: 'Zmmul' v5: In the current master, multiply instructions of the RISC-V simulator doesn't work. The cause was simple. The RISC-V simulator supports 'I', 'M' and 'A' extensions and the instruction is identified by those instruction classes: - INSN_CLASS_I (for 'I') - INSN_CLASS_M (for 'M') - INSN_CLASS_A (for 'A') After adding the 'Zmmul' extension, INSN_CLASS_M is splitted to: - INSN_CLASS_ZMMUL (multiply instructions) - INSN_CLASS_M (division instructions) So, the simulator must handle INSN_CLASS_ZMMUL separately. My 'Zmmul' patchset fixed that and I added a testcase (checks whether all RV32M instructions run without any fault) but only opcodes part is applied so it's now broken state for the simulator. This is the simulator part of the original 'Zmmul' patchset (from PATCH v5). Note: To confirm that the simulator is fixed, it requires another patch. Without the patch above, all multiply instructions will still work. Still, testing whether the simulator works with this extension (with `make check-sim') requires it. Thanks, Tsukasa Tsukasa OI (1): sim: Fix RISC-V multiply instructions on simulator sim/riscv/sim-main.c | 1 + sim/testsuite/riscv/m-ext.s | 18 ++++++++++++++++++ 2 files changed, 19 insertions(+) create mode 100644 sim/testsuite/riscv/m-ext.s base-commit: 803584b96d97e1f6ea50b0a0064d2a03ab0baa60 -- 2.34.1