From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from simark.ca by simark.ca with LMTP id PYUjCWAdDGPyES8AWB0awg (envelope-from ) for ; Sun, 28 Aug 2022 21:58:56 -0400 Received: by simark.ca (Postfix, from userid 112) id 1719E1E4A7; Sun, 28 Aug 2022 21:58:56 -0400 (EDT) Authentication-Results: simark.ca; dkim=pass (1024-bit key; secure) header.d=sourceware.org header.i=@sourceware.org header.a=rsa-sha256 header.s=default header.b=JXYfvCVO; dkim-atps=neutral X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on simark.ca X-Spam-Level: X-Spam-Status: No, score=-2.0 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI,RDNS_DYNAMIC,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 Received: from sourceware.org (ip-8-43-85-97.sourceware.org [8.43.85.97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by simark.ca (Postfix) with ESMTPS id 1EE6E1E13B for ; Sun, 28 Aug 2022 21:58:55 -0400 (EDT) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 120623858025 for ; Mon, 29 Aug 2022 01:58:53 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 120623858025 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1661738333; bh=n5FqR1hwYYQLAaBrZUY3A6LJ2BlZkhPcik4VpOQQcwY=; h=To:Subject:Date:In-Reply-To:References:List-Id:List-Unsubscribe: List-Archive:List-Post:List-Help:List-Subscribe:From:Reply-To:Cc: From; b=JXYfvCVONZwH437HOQzAvIgJCR471IT7KIyQQ3J3IpwolYkYHhaGIW/eC87tMr3TE Q6wt3Jl3ibMoUW0lNGWwB5+liKb97ojLZ37aSkxb6q4jwywoTo676u736URInrjwzG 8pzWmBa50huEAg9bmxA4pPeL28EOCAabVOfEgmvM= Received: from mail-sender-0.a4lg.com (mail-sender.a4lg.com [153.120.152.154]) by sourceware.org (Postfix) with ESMTPS id 60B823858D1E; Mon, 29 Aug 2022 01:58:30 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 60B823858D1E Received: from [127.0.0.1] (localhost [127.0.0.1]) by mail-sender-0.a4lg.com (Postfix) with ESMTPSA id C1999300089; Mon, 29 Aug 2022 01:58:25 +0000 (UTC) To: Tsukasa OI , Nelson Chu , Kito Cheng , Palmer Dabbelt , Liao Shihua Subject: [PATCH v5 0/3] RISC-V: Add 'Zmmul' extension Date: Mon, 29 Aug 2022 01:58:15 +0000 Message-Id: In-Reply-To: References: Mime-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: gdb-patches@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gdb-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , From: Tsukasa OI via Gdb-patches Reply-To: Tsukasa OI Cc: binutils@sourceware.org, gdb-patches@sourceware.org Errors-To: gdb-patches-bounces+public-inbox=simark.ca@sourceware.org Sender: "Gdb-patches" Hi RISC-V folks, 'Zmmul' is a RISC-V extension consisting of only multiply instructions (a subset of 'M'; multiply and divide instructions). This patch is PATCH v5 of the Zmmul support patchset primarily for Binutils but also contains some GDB changes (a simulator fix and a new testcase). I completed the copyright assignment for my GDB contribution so minor simulator changes are now safe enough to merge. Changed Project(s): PATCH 1/3: Binutils PATCH 2/3: Binutils and GDB (not to make "temporally broken" revision) PATCH 3/3: Binutils Note: To confirm that the simulator is fixed, it requires another patch. Without the patch above, 'Zmmul' extension will still work perfectly (even the simulator). Still, testing whether the simulator works with this extension (with `make check-sim') requires it. Tracker on GitHub: PATCH v1: PATCH v2: PATCH v3: PATCH v4: This is based on the ISA Manual, draft-20220707-f518c25: This patchset also contains generic 'M' extension testcases as PATCH 1/3 (it also tests for existence of the symbol `zmmul' so that it can also be a base of 'Zmmul' testcases). [Changes: v4 -> v5] - Clarify that PATCH 1/3 (new 'M' extension testcases) contains preparation for the 'Zmmul' extension. [BUG in PATCH v2 (fixed in v3): Simulator stopped working] The cause was simple. The RISC-V simulator supports I, M and A extensions and the instruction is identified by those instruction classes: - INSN_CLASS_I (for 'I') - INSN_CLASS_M (for 'M') - INSN_CLASS_A (for 'A') I forgot to add INSN_CLASS_ZMMUL (also for 'M') to that list and that caused multiply instructions to cause failure. PATCH v3 fixed that and I added a testcase (checks whether all RV32M instructions run without any fault). Thanks, Tsukasa Tsukasa OI (3): RISC-V: Add 'M' extension testcases RISC-V: Add 'Zmmul' extension RISC-V: Add 'Zmmul' failure testcases bfd/elfxx-riscv.c | 6 +++++ gas/testsuite/gas/riscv/attribute-09.d | 2 +- gas/testsuite/gas/riscv/m-ext-32.d | 18 +++++++++++++ gas/testsuite/gas/riscv/m-ext-64.d | 23 ++++++++++++++++ .../gas/riscv/m-ext-fail-noarch-64.d | 4 +++ .../gas/riscv/m-ext-fail-noarch-64.l | 14 ++++++++++ gas/testsuite/gas/riscv/m-ext-fail-xlen-32.d | 4 +++ gas/testsuite/gas/riscv/m-ext-fail-xlen-32.l | 6 +++++ gas/testsuite/gas/riscv/m-ext-fail-zmmul-32.d | 4 +++ gas/testsuite/gas/riscv/m-ext-fail-zmmul-32.l | 5 ++++ gas/testsuite/gas/riscv/m-ext-fail-zmmul-64.d | 4 +++ gas/testsuite/gas/riscv/m-ext-fail-zmmul-64.l | 9 +++++++ gas/testsuite/gas/riscv/m-ext.s | 21 +++++++++++++++ gas/testsuite/gas/riscv/option-arch-02.d | 2 +- gas/testsuite/gas/riscv/zmmul-32.d | 14 ++++++++++ gas/testsuite/gas/riscv/zmmul-64.d | 15 +++++++++++ include/opcode/riscv.h | 1 + opcodes/riscv-opc.c | 26 +++++++++---------- sim/riscv/sim-main.c | 1 + sim/testsuite/riscv/m-ext.s | 18 +++++++++++++ 20 files changed, 182 insertions(+), 15 deletions(-) create mode 100644 gas/testsuite/gas/riscv/m-ext-32.d create mode 100644 gas/testsuite/gas/riscv/m-ext-64.d create mode 100644 gas/testsuite/gas/riscv/m-ext-fail-noarch-64.d create mode 100644 gas/testsuite/gas/riscv/m-ext-fail-noarch-64.l create mode 100644 gas/testsuite/gas/riscv/m-ext-fail-xlen-32.d create mode 100644 gas/testsuite/gas/riscv/m-ext-fail-xlen-32.l create mode 100644 gas/testsuite/gas/riscv/m-ext-fail-zmmul-32.d create mode 100644 gas/testsuite/gas/riscv/m-ext-fail-zmmul-32.l create mode 100644 gas/testsuite/gas/riscv/m-ext-fail-zmmul-64.d create mode 100644 gas/testsuite/gas/riscv/m-ext-fail-zmmul-64.l create mode 100644 gas/testsuite/gas/riscv/m-ext.s create mode 100644 gas/testsuite/gas/riscv/zmmul-32.d create mode 100644 gas/testsuite/gas/riscv/zmmul-64.d create mode 100644 sim/testsuite/riscv/m-ext.s base-commit: 27d582267a1d06e94661979f8893799ac235a768 -- 2.34.1