Re: [PATCH 0/8] Bare-metal core dumps for RISC-V

Andrew Burgess
2020-12-07T12:11:04Z

* Jim Wilson <jimw@sifive.com> [2020-12-02 15:59:36 -0800]:

> On Wed, Dec 2, 2020 at 9:39 AM Andrew Burgess <andrew.burgess@embecosm.com>
> wrote:
>
> > This series touches both binutils and gdb. Patches #2, #4, and #6 are
> > binutils patches, all the rest are gdb patches.
> >
> > The goal of this series is to add support to GDB for generating a core
> > file for a bare metal RISC-V target.
> >
> > As part of this series patches #2 and #3 add a generic new feature to
> > GDB, the ability to include the current target description in a
> > generated core file.
> >
>
> Just as a general comment, the RISC-V psabi currently only specifies the
> dwarf2 register numbers, which the compiler obviously needs. Otherwise, it
> doesn't try to document anything gdb related, as it has been mainly
> assembler/linker/compiler folk contributing to it. At some point we might
> need some gdb related documentation. Some of the changes here potentially
> affect llvm/lldb and the FreeBSD folks, and they may not be reading GNU
> mailing lists.

Thanks for your feedback.

I agree that it would be a good idea to document this layout
somewhere. Am I correct in thinking that here:

https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md

Is where such things should be documented?

I guess it's probably worth getting the documentation approved before
merging to GDB in case changes are suggested.

Thanks,
Andrew