From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from simark.ca by simark.ca with LMTP id Cb/ADABkEGNA8DAAWB0awg (envelope-from ) for ; Thu, 01 Sep 2022 03:49:20 -0400 Received: by simark.ca (Postfix, from userid 112) id 2533E1E4A7; Thu, 1 Sep 2022 03:49:20 -0400 (EDT) Authentication-Results: simark.ca; dkim=pass (1024-bit key; secure) header.d=sourceware.org header.i=@sourceware.org header.a=rsa-sha256 header.s=default header.b=npgXwHL5; dkim-atps=neutral X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on simark.ca X-Spam-Level: X-Spam-Status: No, score=-2.0 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI,RDNS_DYNAMIC,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 Received: from sourceware.org (ip-8-43-85-97.sourceware.org [8.43.85.97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by simark.ca (Postfix) with ESMTPS id A11AF1E222 for ; Thu, 1 Sep 2022 03:49:19 -0400 (EDT) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id D2CA2382DB11 for ; Thu, 1 Sep 2022 07:49:18 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org D2CA2382DB11 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1662018558; bh=pvTovfazkirBUYFbJ7Z7whmKGSMO8CO66Uuwc1wir70=; h=Date:Subject:To:References:In-Reply-To:List-Id:List-Unsubscribe: List-Archive:List-Post:List-Help:List-Subscribe:From:Reply-To:Cc: From; b=npgXwHL5EQmEGeGxUxSCk96rFELipQM11xDXTMz3adxDvkHpuWLAbUfNRMcB1KwoD rJpWAfR67gdL1j3gu7bOM6faPEUkIC1fcoZkZvXQDnESYlKRcbE9CUPlu0aBE4MUDT CcSn5YOIQ/jh5gYBDx0GATryapDRJEpT502i5Di0= Received: from mail-sender-0.a4lg.com (mail-sender-0.a4lg.com [IPv6:2401:2500:203:30b:4000:6bfe:4757:0]) by sourceware.org (Postfix) with ESMTPS id 8FDCD3858401; Thu, 1 Sep 2022 07:47:58 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 8FDCD3858401 Received: from [127.0.0.1] (localhost [127.0.0.1]) by mail-sender-0.a4lg.com (Postfix) with ESMTPSA id 91152300089; Thu, 1 Sep 2022 07:47:55 +0000 (UTC) Message-ID: Date: Thu, 1 Sep 2022 16:47:54 +0900 Mime-Version: 1.0 Subject: Re: [PATCH v5 0/3] RISC-V: Add 'Zmmul' extension Content-Language: en-US To: Nelson Chu , Palmer Dabbelt References: In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-BeenThere: gdb-patches@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gdb-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , From: Tsukasa OI via Gdb-patches Reply-To: Tsukasa OI Cc: binutils@sourceware.org, gdb-patches@sourceware.org Errors-To: gdb-patches-bounces+public-inbox=simark.ca@sourceware.org Sender: "Gdb-patches" On 2022/08/30 18:55, Nelson Chu wrote: > Thanks, committed except the gdb-sim part, since I'm not the > maintainer of gdb and sim, so I cannot approve the related stuff. > Besides that, some minor failures of ld testcases which caused by m > adding implicit zmmul. However, I also fix that since it's minor. > > Nelson Thanks, and I resubmitted the sim part because it's now broken. Tsukasa > > On Mon, Aug 29, 2022 at 9:59 AM Tsukasa OI via Binutils > wrote: >> >> Hi RISC-V folks, >> >> 'Zmmul' is a RISC-V extension consisting of only multiply instructions (a >> subset of 'M'; multiply and divide instructions). >> >> This patch is PATCH v5 of the Zmmul support patchset primarily for Binutils >> but also contains some GDB changes (a simulator fix and a new testcase). >> >> I completed the copyright assignment for my GDB contribution so minor >> simulator changes are now safe enough to merge. >> >> Changed Project(s): >> PATCH 1/3: Binutils >> PATCH 2/3: Binutils and GDB (not to make "temporally broken" revision) >> PATCH 3/3: Binutils >> >> >> Note: >> To confirm that the simulator is fixed, it requires another patch. >> >> Without the patch above, 'Zmmul' extension will still work perfectly >> (even the simulator). Still, testing whether the simulator works with this >> extension (with `make check-sim') requires it. >> >> >> Tracker on GitHub: >> >> PATCH v1: >> >> PATCH v2: >> >> PATCH v3: >> >> PATCH v4: >> >> >> >> This is based on the ISA Manual, draft-20220707-f518c25: >> >> >> >> This patchset also contains generic 'M' extension testcases as PATCH 1/3 (it >> also tests for existence of the symbol `zmmul' so that it can also be a >> base of 'Zmmul' testcases). >> >> >> [Changes: v4 -> v5] >> >> - Clarify that PATCH 1/3 (new 'M' extension testcases) contains >> preparation for the 'Zmmul' extension. >> >> >> [BUG in PATCH v2 (fixed in v3): Simulator stopped working] >> >> The cause was simple. The RISC-V simulator supports I, M and A extensions >> and the instruction is identified by those instruction classes: >> >> - INSN_CLASS_I (for 'I') >> - INSN_CLASS_M (for 'M') >> - INSN_CLASS_A (for 'A') >> >> I forgot to add INSN_CLASS_ZMMUL (also for 'M') to that list and that caused >> multiply instructions to cause failure. >> >> PATCH v3 fixed that and I added a testcase (checks whether all RV32M >> instructions run without any fault). >> >> >> Thanks, >> Tsukasa >> >> >> >> >> Tsukasa OI (3): >> RISC-V: Add 'M' extension testcases >> RISC-V: Add 'Zmmul' extension >> RISC-V: Add 'Zmmul' failure testcases >> >> bfd/elfxx-riscv.c | 6 +++++ >> gas/testsuite/gas/riscv/attribute-09.d | 2 +- >> gas/testsuite/gas/riscv/m-ext-32.d | 18 +++++++++++++ >> gas/testsuite/gas/riscv/m-ext-64.d | 23 ++++++++++++++++ >> .../gas/riscv/m-ext-fail-noarch-64.d | 4 +++ >> .../gas/riscv/m-ext-fail-noarch-64.l | 14 ++++++++++ >> gas/testsuite/gas/riscv/m-ext-fail-xlen-32.d | 4 +++ >> gas/testsuite/gas/riscv/m-ext-fail-xlen-32.l | 6 +++++ >> gas/testsuite/gas/riscv/m-ext-fail-zmmul-32.d | 4 +++ >> gas/testsuite/gas/riscv/m-ext-fail-zmmul-32.l | 5 ++++ >> gas/testsuite/gas/riscv/m-ext-fail-zmmul-64.d | 4 +++ >> gas/testsuite/gas/riscv/m-ext-fail-zmmul-64.l | 9 +++++++ >> gas/testsuite/gas/riscv/m-ext.s | 21 +++++++++++++++ >> gas/testsuite/gas/riscv/option-arch-02.d | 2 +- >> gas/testsuite/gas/riscv/zmmul-32.d | 14 ++++++++++ >> gas/testsuite/gas/riscv/zmmul-64.d | 15 +++++++++++ >> include/opcode/riscv.h | 1 + >> opcodes/riscv-opc.c | 26 +++++++++---------- >> sim/riscv/sim-main.c | 1 + >> sim/testsuite/riscv/m-ext.s | 18 +++++++++++++ >> 20 files changed, 182 insertions(+), 15 deletions(-) >> create mode 100644 gas/testsuite/gas/riscv/m-ext-32.d >> create mode 100644 gas/testsuite/gas/riscv/m-ext-64.d >> create mode 100644 gas/testsuite/gas/riscv/m-ext-fail-noarch-64.d >> create mode 100644 gas/testsuite/gas/riscv/m-ext-fail-noarch-64.l >> create mode 100644 gas/testsuite/gas/riscv/m-ext-fail-xlen-32.d >> create mode 100644 gas/testsuite/gas/riscv/m-ext-fail-xlen-32.l >> create mode 100644 gas/testsuite/gas/riscv/m-ext-fail-zmmul-32.d >> create mode 100644 gas/testsuite/gas/riscv/m-ext-fail-zmmul-32.l >> create mode 100644 gas/testsuite/gas/riscv/m-ext-fail-zmmul-64.d >> create mode 100644 gas/testsuite/gas/riscv/m-ext-fail-zmmul-64.l >> create mode 100644 gas/testsuite/gas/riscv/m-ext.s >> create mode 100644 gas/testsuite/gas/riscv/zmmul-32.d >> create mode 100644 gas/testsuite/gas/riscv/zmmul-64.d >> create mode 100644 sim/testsuite/riscv/m-ext.s >> >> >> base-commit: 27d582267a1d06e94661979f8893799ac235a768 >> -- >> 2.34.1 >> >