From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from simark.ca (simark.ca [158.69.221.121]) by sourceware.org (Postfix) with ESMTPS id 0DCD1396D826 for ; Thu, 14 May 2020 15:01:46 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.3.2 sourceware.org 0DCD1396D826 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=simark.ca Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=simark@simark.ca Received: from [10.0.0.193] (unknown [192.222.164.54]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits)) (No client certificate requested) by simark.ca (Postfix) with ESMTPSA id 31CB81ED39; Thu, 14 May 2020 11:01:45 -0400 (EDT) Subject: Re: [PATCH v2 2/4] arc: Recognize registers available on Linux targets To: Shahab Vahedi , gdb-patches@sourceware.org Cc: Shahab Vahedi , Anton Kolesov , Tom Tromey , Francois Bedard References: <20200326125206.13120-1-shahab.vahedi@gmail.com> <20200428160437.1585-1-shahab.vahedi@gmail.com> <20200428160437.1585-3-shahab.vahedi@gmail.com> From: Simon Marchi Message-ID: Date: Thu, 14 May 2020 11:01:44 -0400 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.7.0 MIME-Version: 1.0 In-Reply-To: <20200428160437.1585-3-shahab.vahedi@gmail.com> Content-Type: text/plain; charset=utf-8 Content-Language: tl Content-Transfer-Encoding: 7bit X-Spam-Status: No, score=-7.2 required=5.0 tests=BAYES_00, KAM_DMARC_STATUS, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: gdb-patches@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gdb-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 14 May 2020 15:01:47 -0000 Just some nits - I don't really know about the specific details of the ARC architecture. On 2020-04-28 12:04 p.m., Shahab Vahedi via Gdb-patches wrote: > @@ -1950,13 +1984,17 @@ arc_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) > if (arc_debug) > debug_printf ("arc: Architecture initialization.\n"); > > - if (!arc_tdesc_init (info, &tdesc, &tdesc_data)) > - return NULL; > - > /* Allocate the ARC-private target-dependent information structure, and the > GDB target-independent information structure. */ > struct gdbarch_tdep *tdep = XCNEW (struct gdbarch_tdep); > tdep->jb_pc = -1; /* No longjmp support by default. */ > + > + if (!arc_tdesc_init (info, &tdesc, &tdesc_data, tdep)) > + { > + xfree (tdep); > + return nullptr; > + } > + I would suggest to do it in a bit more C++-y way, to even avoid the xfree: gdb::unique_xmalloc_ptr tdep (XCNEW (struct gdbarch_tdep)); tdep->jb_pc = -1; /* No longjmp support by default. */ if (!arc_tdesc_init (info, &tdesc, &tdesc_data, tdep.get ())) return nullptr; struct gdbarch *gdbarch = gdbarch_alloc (&info, tdep.release ()); This way it shows clearly that this function is giving ownership of the tdep to gdbarch_alloc. > struct gdbarch *gdbarch = gdbarch_alloc (&info, tdep); > > /* Data types. */ > @@ -1987,6 +2025,13 @@ arc_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) > set_gdbarch_ps_regnum (gdbarch, ARC_STATUS32_REGNUM); > set_gdbarch_fp0_regnum (gdbarch, -1); /* No FPU registers. */ > > + /* Confirm that register name lists have proper length. */ > + gdb_static_assert (ARC_LAST_REGNUM + 1 > + == (ARRAY_SIZE (core_v2_register_names) > + + ARRAY_SIZE (aux_minimal_register_names))); > + gdb_static_assert (ARRAY_SIZE (core_v2_register_names) > + == ARRAY_SIZE (core_arcompact_register_names)); Does this need to be here? I would expect them to be near (just after) the definitions of said arrays. Simon