From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 130855 invoked by alias); 30 Sep 2018 14:22:02 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Received: (qmail 130838 invoked by uid 89); 30 Sep 2018 14:22:02 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-26.9 required=5.0 tests=BAYES_00,GIT_PATCH_0,GIT_PATCH_1,GIT_PATCH_2,GIT_PATCH_3,SPF_HELO_PASS,SPF_PASS autolearn=ham version=3.3.2 spammy=23725, Piepho, piepho, trent X-HELO: simark.ca Received: from simark.ca (HELO simark.ca) (158.69.221.121) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Sun, 30 Sep 2018 14:22:01 +0000 Received: from [10.0.0.11] (unknown [192.222.164.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by simark.ca (Postfix) with ESMTPSA id 397771E197; Sun, 30 Sep 2018 10:21:59 -0400 (EDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=simark.ca; s=mail; t=1538317319; bh=GTauUJLfMOrcLGAGjrJUD8bs3QRMt3mF6GVOc4zPH9g=; h=Subject:To:References:From:Date:In-Reply-To:From; b=T+7rL5YgmGd8/E0qcJKZRyM65TQ2a31fhIfcB2mNTE5UPKhwN5tUsh+a6ts/i+ueF TjpZ0SiNo+rOhSZNlUQ2Vyxkkvejd2aDfg8C+M6RtopseOYbkE05fzzHwnxUohgk9y YLsJzPRr1XpErTdSOZTrRQ87a9OunTimoIgM/6bw= Subject: Re: [PATCH] Record ARM THUMB2 PLD/PLI cache instructions To: Trent Piepho , "gdb-patches@sourceware.org" References: <20180928230437.4329-1-tpiepho@impinj.com> From: Simon Marchi Message-ID: Date: Sun, 30 Sep 2018 14:22:00 -0000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.0 MIME-Version: 1.0 In-Reply-To: <20180928230437.4329-1-tpiepho@impinj.com> Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 7bit X-SW-Source: 2018-09/txt/msg00944.txt.bz2 On 2018-09-28 7:04 p.m., Trent Piepho wrote: > These weren't decoded correctly and trigger an unknown instruction error > when recording. The ARM format was handled, but not the 32-bit THUMB2 > format. > > Since they are only hints that may affect cache state, there is nothing > to record. > > gdb/ChangeLog > 2018-09-28 Trent Piepho > > PR gdb/23725 > * gdb/arm-tdep.c (thumb2_record_ld_mem_hints): Decode thumb2 PLD/PLI > --- > gdb/arm-tdep.c | 8 ++++++++ > 1 file changed, 8 insertions(+) > > diff --git a/gdb/arm-tdep.c b/gdb/arm-tdep.c > index c3280ee211..90936ada8e 100644 > --- a/gdb/arm-tdep.c > +++ b/gdb/arm-tdep.c > @@ -12683,6 +12683,14 @@ thumb2_record_ld_mem_hints (insn_decode_record *thumb2_insn_r) > record_buf); > return ARM_RECORD_SUCCESS; > } > + else > + { > + if (bits (thumb2_insn_r->arm_insn, 20, 22) == 0x1) > + { > + /* Handle PLD, PLI affect only caches, so nothing to record */ > + return ARM_RECORD_SUCCESS; > + } > + } > > return ARM_RECORD_FAILURE; > } > Hi Trent, Thanks for the patch. After staring at the ARM architecture reference manual enough, I think this is fine. In the manual, however, in table "Table A5-20 Load byte, memory hints", some encodings with Rt == 0b1111 decode to "UNPREDICTABLE". Should the record fail for those? I think currently with your patch we will accept them. I am thinking it would be good to fail, because since we can't know the side effects of such instruction, we risk showing some false information if we just assume nothing has changed. If you are motivated, it would be nice to add a test for this instruction in arm_record_test, but I won't require it, since the current state is that this test isn't meant to test all possible instruction, and I don't want to impose that burden on you. Simon