From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 7094 invoked by alias); 12 Jun 2014 08:34:21 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Received: (qmail 7081 invoked by uid 89); 12 Jun 2014 08:34:20 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.1 required=5.0 tests=AWL,BAYES_00,MIME_BASE64_BLANKS,RCVD_IN_DNSWL_NONE,SPF_HELO_PASS,SPF_PASS autolearn=ham version=3.3.2 X-HELO: na01-bn1-obe.outbound.protection.outlook.com Received: from mail-bn1lp0140.outbound.protection.outlook.com (HELO na01-bn1-obe.outbound.protection.outlook.com) (207.46.163.140) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES128-SHA encrypted) ESMTPS; Thu, 12 Jun 2014 08:34:18 +0000 Received: from BN1BFFO11FD015.protection.gbl (10.58.144.30) by BN1BFFO11HUB035.protection.gbl (10.58.144.182) with Microsoft SMTP Server (TLS) id 15.0.959.15; Thu, 12 Jun 2014 08:34:14 +0000 Received: from xsj-pvapsmtpgw01 (149.199.60.83) by BN1BFFO11FD015.mail.protection.outlook.com (10.58.144.78) with Microsoft SMTP Server (TLS) id 15.0.959.15 via Frontend Transport; Thu, 12 Jun 2014 08:34:14 +0000 Received: from unknown-38-66.xilinx.com ([149.199.38.66] helo=xsj-smtp1) by xsj-pvapsmtpgw01 with esmtp (Exim 4.63) (envelope-from ) id 1Wv0Sw-0001pa-MB; Thu, 12 Jun 2014 01:34:34 -0700 From: Ajit Kumar Agarwal To: Michael Eager , "gdb-patches@sourceware.org" , Pedro Alves CC: Vinod Kathail , Vidhumouli Hunsigida , Nagaraju Mekala Subject: RE: [Patch, microblaze]: Add slr and shr regs Date: Thu, 12 Jun 2014 08:34:00 -0000 References: <537EFA08.1060309@eagercon.com> <537FCEDA.9030504@eagercon.com> <2e5c185d-329c-46cf-930c-8cc2288891aa@BN1BFFO11FD019.protection.gbl> <538431FB.2070904@eagercon.com> <865132b2-a593-4147-a7c6-cee25c1ed0fd@BN1AFFO11FD052.protection.gbl> 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149.199.60.83) smtp.mailfrom=ajit.kumar.agarwal@xilinx.com; X-SW-Source: 2014-06/txt/msg00492.txt.bz2 VGhhbmsgeW91ICBhbGwuIEFsbCB0aGUgZmVlZGJhY2tzIGhhdmUgYmVlbiBp bmNvcnBvcmF0ZWQgYW5kIHRoZSBmcmVzaCBwYXRjaCB3aWxsIGJlIHNlbnQg aW4gdGhlIG5leHQgbWFpbC4NCg0KLS0tLS1PcmlnaW5hbCBNZXNzYWdlLS0t LS0NCkZyb206IE1pY2hhZWwgRWFnZXIgW21haWx0bzplYWdlckBlYWdlcm0u Y29tXSANClNlbnQ6IFR1ZXNkYXksIEp1bmUgMTAsIDIwMTQgODo1NyBQTQ0K VG86IEFqaXQgS3VtYXIgQWdhcndhbDsgZ2RiLXBhdGNoZXNAc291cmNld2Fy ZS5vcmcNCkNjOiBWaW5vZCBLYXRoYWlsOyBWaWRodW1vdWxpIEh1bnNpZ2lk YTsgTmFnYXJhanUgTWVrYWxhDQpTdWJqZWN0OiBSZTogW1BhdGNoLCBtaWNy b2JsYXplXTogQWRkIHNsciBhbmQgc2hyIHJlZ3MNCg0KT24gMDYvMTAvMTQg MDc6NDksIEFqaXQgS3VtYXIgQWdhcndhbCB3cm90ZToNCj4NCj4gLS0tLS1P cmlnaW5hbCBNZXNzYWdlLS0tLS0NCj4gRnJvbTogTWljaGFlbCBFYWdlciBb bWFpbHRvOmVhZ2VyQGVhZ2VybS5jb21dDQo+IFNlbnQ6IFR1ZXNkYXksIEp1 bmUgMTAsIDIwMTQgNzo0MiBQTQ0KPiBUbzogQWppdCBLdW1hciBBZ2Fyd2Fs OyBnZGItcGF0Y2hlc0Bzb3VyY2V3YXJlLm9yZw0KPiBDYzogVmlub2QgS2F0 aGFpbDsgVmlkaHVtb3VsaSBIdW5zaWdpZGE7IE5hZ2FyYWp1IE1la2FsYQ0K PiBTdWJqZWN0OiBSZTogW1BhdGNoLCBtaWNyb2JsYXplXTogQWRkIHNsciBh bmQgc2hyIHJlZ3MNCj4NCj4gT24gMDYvMTAvMTQgMDY6NTAsIEFqaXQgS3Vt YXIgQWdhcndhbCB3cm90ZToNCj4+DQo+Pj4+IFhNRCBpcyBub3QgcnVubmlu ZyBnZGJzZXJ2ZXIgYnVpbHQgd2l0aCB0aGVzZSBzb3VyY2VzLCBpcyBpdD8N Cj4+DQo+PiBZZXMgWE1EIGlzIG5vdCBydW5uaW5nIGdkYnNlcnZlciBidWls dCB3aXRoIHRoZXNlIHNvdXJjZXMuDQo+Pg0KPj4+PiBZb3VyIHBhdGNoIG1v ZGlmaWVkIGZpbGVzIHVuZGVyIGdkYi9nZGJzZXJ2ZXIuICBXaGVuIHlvdSBi dWlsZCBiaW51dGlscy9nZGIgd2l0aCAtdGFyZ2V0PW1pY3JvYmxhemUteGls aW54LWVsZiwgdGhlc2UgZmlsZXMgYXJlIG5vdCBidWlsdC4NCj4+DQo+PiBU aGUgcGF0Y2ggcmVsYXRlZCB0byBidWlsZGluZyBnZGJzZXJ2ZXIgd2l0aCB0 aGUgbGF0ZXN0IEZTRiBTb3VyY2VzIHdpbGwgYmUgdGhlIG5leHQgcGF0Y2gg d2hpY2ggSSBhbSBnb2luZyB0byAgc3VibWl0IGZvciByZXZpZXcuDQo+DQo+ Pj4gQ2hhbmdlcyByZWxhdGVkIHRvIGJ1aWxkaW5nIGdkYnNlcnZlciBzaG91 bGQgYmUgc3VibWl0dGVkIHRvZ2V0aGVyLiAgSXQgc291bmRzIGxpa2UgdGhp cyBwYXRjaCBpcyBkZXBlbmRlbnQgb24gc29tZSBmdXR1cmUgcGF0Y2guDQo+ DQo+IENvdWxkIHlvdSBwbGVhc2UgZXhwbGFpbiB3aHkgeW91IHRoaW5rICBi dWlsZGluZyBnZGJzZXJ2ZXIgc2hvdWxkIGJlIHN1Ym1pdHRlZCB0b2dldGhl cj8uIFRoaXMgcGF0Y2ggaXMgcmVsYXRlZCB0byB0aGUgcHJvYmxlbSBvZiBS ZW1vdGUgRyBQYWNrZXQgZXJyb3Igd2hpY2ggaXMgbWFpbmx5IHRhcmdldGVk IGZvciBiYXJlbWV0YWwuDQo+IFNvbHZpbmcgdGhlIG1pc21hdGNoaW5nIGVy cm9yIGJldHdlZW4gcGFja2V0cyByZXR1cm5pbmcgZnJvbSBYTUQgU3R1YiBh bmQgR0RCLg0KDQpZb3VyIHBhdGNoIGNvbnRhaW5zIGNoYW5nZXMgdG8gZ2Ri c2VydmVyLiAgQXMgZmFyIGFzIHlvdSBoYXZlIGluZGljYXRlZCwgeW91IGhh dmVuJ3QgYnVpbHQgb3IgdGVzdGVkIGdkYnNlcnZlciBmcm9tIHRoZXNlIHNv dXJjZXMuDQoNCj4gVGhpcyBpcyBwbGFpbmx5IGluZGVwZW5kZW50IG9mIHRo ZSAgcGF0Y2ggdGhhdCBkZWFscyB3aXRoIGdkYnNlcnZlciBwYXRjaCB3aGlj aCBtYWlubHkgZGVhbHMgd2l0aCBuYXRpdmUgbGludXggZGVidWdnaW5nIHN1 cHBvcnQgd2hpY2ggaXMgcXVpdGUgaW5kZXBlbmRlbnQgb2YgdGhpcyBwYXRj aC4NCg0KSSBoYXZlIG5vIGlkZWEgd2hhdCB5b3VyIGZ1dHVyZSBwYXRjaCB3 aWxsIGNvbnRhaW4uDQoNCkkgZG9uJ3QgcGFydGljdWxhcmx5IGNhcmUgd2hl dGhlciB5b3Ugc3VibWl0IHRoZSBnZGJzZXJ2ZXIgY2hhbmdlcyBpbiB0aGlz IHBhdGNoIHRvZ2V0aGVyIHdpdGggdGhpcyB1bmtub3duIGZ1dHVyZSBwYXRj aCwgb3Igd2hldGhlciB5b3Ugc3VibWl0IHRoZW0gYXMgbXVsdGlwbGUgcGF0 Y2hlcy4gIEl0IGFwcGVhcnMgdGhhdCB0aGVzZSBjaGFuZ2VzIGFyZSBpbmFw cHJvcHJpYXRlIGZvciBhIHBhdGNoIHdoaWNoIGlzIHVucmVsYXRlZC4NCg0K Pj4+IFBsZWFzZSBzdWJtaXQgYSByZXZpc2VkIHBhdGNoIHdoaWNoIGFkZHJl c3NlcyBvbmUgcHJvYmxlbToNCj4+PiBzdXBwb3J0IGZvciB0aGUgYWRkZWQg cmVnaXN0ZXJzIGluIE1pY3JvQmxhemUgdjguMTBhLiAgQXMgbWVudGlvbmVk IHByZXZpb3VzbHksIGdkYiBidWlsdCB3aXRoIHRoaXMgcGF0Y2ggc2hvdWxk IGNvbnRpbnVlIHRvIHN1cHBvcnQgdGhlIHNhbWUgdmVyc2lvbnMgb2YgTWlj cm9CbGF6ZSB0aGF0IGFyZSBjdXJyZW50bHkgc3VwcG9ydGVkLg0KPg0KPiBT dXBwb3J0IGZvciBTSFIvU0hMIHJlZ2lzdGVycyB3aXRoIGJhcmVtZXRhbCBz dXBwb3J0IGlzIHF1aXRlIGRpZmZlcmVudCBmcm9tIHRoZSBwYXRjaCB3aXRo IGJ1aWxkaW5nIGdkYnNlcnZlciBhcyBYTUQgZG9lc27igJl0IHVzZSB0aGUg Z2Ric2VydmVyIHN0dWIgZnJvbSB0aGUgRlNGIHNvdXJjZXMuIEl0IGhhcyBp dHMgb3duIGdkYnNlcnZlciBBbmQgd2UgZG9u4oCZdCBoYXZlIHBsYW5zIHRv IHJlcGxhY2UgZ2RiIFNlcnZlciBpbiBYTUQgd2l0aCBnZGJzZXJ2ZXIgZnJv bSBGU0YgU291cmNlcy4gVGhlIGJ1aWxkaW5nIG9mIGdkYlNlcnZlciAgZnJv bSBGU0YgaXMgbWFpbmx5IHJlbGF0ZWQgdG8gTGludXggbmF0aXZlIGRlYnVn Z2luZyBhbmQgdXNlIGZvciBMaW51eCBpbWFnZSBTdXBwb3J0IG9mIE1JY3Jv YmxhemUgd2hpY2ggaXMgcXVpdGUgaW5kZXBlbmRlbnQgb2YgdGhlIHBhdGNo IHN1Ym1pdHRlZCBmb3IgYmFyZW1ldGFsLg0KDQpZZXMsIHN1cHBvcnQgZm9y IGJhcmVtZXRhbCBpcyBxdWl0ZSBkaWZmZXJlbnQgZnJvbSBMaW51eCBwYXRj aGVzLg0KVGhpcyBwYXRjaCBpcyBvbmx5IGZvciBiYXJlbWV0YWwgc3VwcG9y dCBhbmQgc2hvdWxkIG5vdCBjb250YWluIGNoYW5nZXMgdG8gZ2Ric2VydmVy Lg0KDQo+IEkgZG9u4oCZdCBzZWUgYW55IHJlbGF0aW9ucyBiZXR3ZWVuIHRo ZSB0d28gYW5kIHdoeSB0aGUgcGF0Y2hlcyBzaG91bGQgYmUgc3VibWl0dGVk IHRvZ2V0aGVyLg0KDQpJJ20gYXNraW5nIHlvdSB0byBoYXZlIG9uZSBwYXRj aCBhZGRyZXNzIG9uZSBjaGFuZ2UuDQoNCg0KLS0gDQpNaWNoYWVsIEVhZ2Vy CSBlYWdlckBlYWdlcmNvbi5jb20NCjE5NjAgUGFyayBCbHZkLiwgUGFsbyBB bHRvLCBDQSA5NDMwNiAgNjUwLTMyNS04MDc3DQoNCg== >From gdb-patches-return-113421-listarch-gdb-patches=sources.redhat.com@sourceware.org Thu Jun 12 08:40:34 2014 Return-Path: Delivered-To: listarch-gdb-patches@sources.redhat.com Received: (qmail 11626 invoked by alias); 12 Jun 2014 08:40:33 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Delivered-To: mailing list gdb-patches@sourceware.org Received: (qmail 11611 invoked by uid 89); 12 Jun 2014 08:40:32 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.3 required=5.0 tests=AWL,BAYES_00,FREEMAIL_FROM,RCVD_IN_DNSWL_LOW,SPF_PASS autolearn=ham version=3.3.2 X-HELO: mail-ob0-f171.google.com Received: from mail-ob0-f171.google.com (HELO mail-ob0-f171.google.com) (209.85.214.171) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES128-SHA encrypted) ESMTPS; Thu, 12 Jun 2014 08:40:30 +0000 Received: by mail-ob0-f171.google.com with SMTP id nu7so978547obb.2 for ; Thu, 12 Jun 2014 01:40:29 -0700 (PDT) X-Received: by 10.182.60.65 with SMTP id f1mr880899obr.78.1402562429090; Thu, 12 Jun 2014 01:40:29 -0700 (PDT) MIME-Version: 1.0 Received: by 10.60.37.4 with HTTP; Thu, 12 Jun 2014 01:39:49 -0700 (PDT) In-Reply-To: <0a87ce80-983c-4a0e-a5be-f931581873e8@SVR-ORW-FEM-02.mgc.mentorg.com> References: <0a87ce80-983c-4a0e-a5be-f931581873e8@SVR-ORW-FEM-02.mgc.mentorg.com> From: Hui Zhu Date: Thu, 12 Jun 2014 08:40:00 -0000 Message-ID: Subject: Re: [PATCH v2] Fix interrupt.exp fails with m32 in x86_64 To: Hui Zhu Cc: Mark Kettenis , Pedro Alves , "H.Peter Anvin" , gdb-patches ml Content-Type: text/plain; charset=ISO-8859-1 X-IsSubscribed: yes X-SW-Source: 2014-06/txt/msg00493.txt.bz2 Content-length: 4579 Ping. Thanks, Hui On Tue, May 6, 2014 at 4:21 PM, Hui Zhu wrote: > According to your comments in the discussion thread about Linux kernel > patch. I make a new patch for GDB that let %eax sign-extend if %orig_eax >= 0. > > Thanks, > Hui > > 2014-05-06 Hui Zhu > > * amd64-linux-nat.c (fill_gregset): Make %eax > sign-extended if need. > (amd64_linux_store_inferior_registers): Change > amd64_collect_native_gregset to fill_gregset. > * amd64-nat.c (amd64_native_gregset_reg_offset): Remove static. > * amd64-nat.h (amd64_native_gregset_reg_offset): Add extern. > > --- a/gdb/amd64-linux-nat.c > +++ b/gdb/amd64-linux-nat.c > @@ -128,7 +128,52 @@ void > fill_gregset (const struct regcache *regcache, > elf_gregset_t *gregsetp, int regnum) > { > + struct gdbarch *gdbarch = get_regcache_arch (regcache); > + > amd64_collect_native_gregset (regcache, gregsetp, regnum); > + > + /* If target arch is 32 bits and GDB interrupt a system call of > + inferior (%orig_rax >= 0), %rax is the errno of this system call. > + amd64_collect_native_gregset let %eax zero-extend put %rax from > + negative to positive. > + If Linux cannot convert value of %rax back, the system call of > + inferior will got errno -ERESTARTNOHAND, -ERESTARTSYS, -ERESTARTNOINTR > + or -ERESTART_RESTARTBLOCK. > + So if this is a 32 bits system call and fill value to %orig_eax > + (not %eax to make sure REGCACHE has the right value of %orig_rax) > + or all registers, let %eax sign-extend. */ > + if (regcache_register_status (regcache, I386_LINUX_ORIG_EAX_REGNUM) > + == REG_VALID > + && regcache_register_status (regcache, I386_EAX_REGNUM) == REG_VALID > + && gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 32 > + && (regnum == I386_LINUX_ORIG_EAX_REGNUM || regnum == -1)) > + { > + LONGEST val; > + gdb_byte buf[MAX_REGISTER_SIZE]; > + int orig_eax_size; > + > + /* Get value of orig_eax and put it to val. */ > + regcache_raw_collect (regcache, I386_LINUX_ORIG_EAX_REGNUM, > + buf); > + orig_eax_size = register_size (gdbarch, > + I386_LINUX_ORIG_EAX_REGNUM); > + val = extract_signed_integer (buf, orig_eax_size, > + gdbarch_byte_order (gdbarch)); > + if (val >= 0) > + { > + /* Make %eax get sign-extended to 64 bits. */ > + char *regs = (char *) gregsetp; > + int offset = amd64_native_gregset_reg_offset (gdbarch, > + I386_EAX_REGNUM); > + > + regcache_raw_collect (regcache, I386_EAX_REGNUM, > + regs + offset); > + val = extract_signed_integer ((gdb_byte *)(regs + offset), 4, > + gdbarch_byte_order (gdbarch)); > + store_signed_integer ((gdb_byte *)(regs + offset), 8, > + gdbarch_byte_order (gdbarch), val); > + } > + } > } > > /* Transfering floating-point registers between GDB, inferiors and cores. */ > @@ -234,7 +279,7 @@ amd64_linux_store_inferior_registers (st > if (ptrace (PTRACE_GETREGS, tid, 0, (long) ®s) < 0) > perror_with_name (_("Couldn't get registers")); > > - amd64_collect_native_gregset (regcache, ®s, regnum); > + fill_gregset (regcache, ®s, regnum); > > if (ptrace (PTRACE_SETREGS, tid, 0, (long) ®s) < 0) > perror_with_name (_("Couldn't write registers")); > --- a/gdb/amd64-nat.c > +++ b/gdb/amd64-nat.c > @@ -51,7 +51,7 @@ int amd64_native_gregset64_num_regs = AM > /* Return the offset of REGNUM within the appropriate native > general-purpose register set. */ > > -static int > +int > amd64_native_gregset_reg_offset (struct gdbarch *gdbarch, int regnum) > { > int *reg_offset = amd64_native_gregset64_reg_offset; > --- a/gdb/amd64-nat.h > +++ b/gdb/amd64-nat.h > @@ -30,6 +30,12 @@ extern int amd64_native_gregset32_num_re > extern int *amd64_native_gregset64_reg_offset; > extern int amd64_native_gregset64_num_regs; > > +/* Return the offset of REGNUM within the appropriate native > + general-purpose register set. */ > + > +extern int amd64_native_gregset_reg_offset (struct gdbarch *gdbarch, > + int regnum); > + > /* Return whether the native general-purpose register set supplies > register REGNUM. */ >