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BYAPR15MB2390.namprd15.prod.outlook.com ([fe80::649a:ddbf:ecc5:1f0a]) by BYAPR15MB2390.namprd15.prod.outlook.com ([fe80::649a:ddbf:ecc5:1f0a%3]) with mapi id 15.20.1273.019; Fri, 26 Oct 2018 16:08:24 +0000 From: Simon Marchi To: Sergio Durigan Junior , GDB Patches , Pedro Alves Subject: Re: [PATCH] Fix thinko on common/offset-type.h (compare 'lhs' against 'rhs') Date: Fri, 26 Oct 2018 16:08:00 -0000 Message-ID: References: <20181025211008.12164-1-sergiodj@redhat.com> In-Reply-To: <20181025211008.12164-1-sergiodj@redhat.com> authentication-results: spf=none (sender IP is ) smtp.mailfrom=simon.marchi@ericsson.com; received-spf: None (protection.outlook.com: ericsson.com does not designate permitted sender hosts) Content-Type: text/plain; charset="utf-8" Content-ID: Content-Transfer-Encoding: base64 MIME-Version: 1.0 Return-Path: simon.marchi@ericsson.com X-IsSubscribed: yes X-SW-Source: 2018-10/txt/msg00623.txt.bz2 T24gMjAxOC0xMC0yNSA1OjEwIHAubS4sIFNlcmdpbyBEdXJpZ2FuIEp1bmlv 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gdb-patches-return-151906-listarch-gdb-patches=sources.redhat.com@sourceware.org Fri Oct 26 16:26:09 2018 Return-Path: Delivered-To: listarch-gdb-patches@sources.redhat.com Received: (qmail 15364 invoked by alias); 26 Oct 2018 16:26:08 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Delivered-To: mailing list gdb-patches@sourceware.org Received: (qmail 15347 invoked by uid 89); 26 Oct 2018 16:26:08 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-25.1 required=5.0 tests=AWL,BAYES_00,GIT_PATCH_0,GIT_PATCH_1,GIT_PATCH_2,GIT_PATCH_3,SPF_HELO_PASS,SPF_SOFTFAIL autolearn=ham version=3.3.2 spammy=bank X-HELO: mail.baldwin.cx Received: from bigwig.baldwin.cx (HELO mail.baldwin.cx) (96.47.65.170) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Fri, 26 Oct 2018 16:26:05 +0000 Received: from John-Baldwins-MacBook-Pro-2.local (ralph.baldwin.cx [66.234.199.215]) by mail.baldwin.cx (Postfix) with ESMTPSA id A1A3B10A87D; Fri, 26 Oct 2018 12:26:03 -0400 (EDT) Subject: Re: [PATCH 2/2] RISC-V: Linux signal frame support. To: Jim Wilson , gdb-patches@sourceware.org References: <20181026000030.3847-1-jimw@sifive.com> From: John Baldwin Message-ID: Date: Fri, 26 Oct 2018 16:26:00 -0000 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.12; rv:52.0) Gecko/20100101 Thunderbird/52.9.1 MIME-Version: 1.0 In-Reply-To: <20181026000030.3847-1-jimw@sifive.com> Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 7bit X-IsSubscribed: yes X-SW-Source: 2018-10/txt/msg00624.txt.bz2 Content-length: 4545 On 10/25/18 5:00 PM, Jim Wilson wrote: > Add support for recognizing signal trampolines, parsing the signal frame, > and reading register values from it. > > gdb/ > * riscv-linux-tdep.c: Include tramp-frame.h and trad-frame.h. > (riscv_linux_sigframe_init): Declare. > (RISCV_INST_LI_A7_SIGRETURN, RISCV_INT_ECALL): New. > (riscv_linux_sigframe): New. > (SIGFRAME_SIGINFO_SIZE, UCONTEXT_MCONTEXT_OFFSET): New. > (riscv_linux_sigframe_init): Define. > (riscv_linux_init_abi): Call tramp_frame_prepend_unwinder. > --- > gdb/riscv-linux-tdep.c | 80 ++++++++++++++++++++++++++++++++++++++++++ > 1 file changed, 80 insertions(+) > > diff --git a/gdb/riscv-linux-tdep.c b/gdb/riscv-linux-tdep.c > index d072c0b754..ece75dba47 100644 > --- a/gdb/riscv-linux-tdep.c > +++ b/gdb/riscv-linux-tdep.c > @@ -23,6 +23,8 @@ > #include "linux-tdep.h" > #include "solib-svr4.h" > #include "regset.h" > +#include "tramp-frame.h" > +#include "trad-frame.h" > > /* Define the general register mapping. The kernel puts the PC at offset 0, > gdb puts it at offset 32. Register x0 is always 0 and can be ignored. > @@ -56,6 +58,82 @@ riscv_linux_iterate_over_regset_sections (struct gdbarch *gdbarch, > /* TODO: Add FP register support. */ > } > > +/* Signal trampoline support. */ > + > +static void riscv_linux_sigframe_init (const struct tramp_frame *self, > + struct frame_info *this_frame, > + struct trad_frame_cache *this_cache, > + CORE_ADDR func); > + > +#define RISCV_INST_LI_A7_SIGRETURN 0x08b00893 > +#define RISCV_INST_ECALL 0x00000073 > + > +static const struct tramp_frame riscv_linux_sigframe = { > + SIGTRAMP_FRAME, > + 4, > + { > + { RISCV_INST_LI_A7_SIGRETURN, ULONGEST_MAX }, > + { RISCV_INST_ECALL, ULONGEST_MAX }, > + { TRAMP_SENTINEL_INSN } > + }, > + riscv_linux_sigframe_init, > + NULL > +}; > + > +/* Runtime signal frames look like this: > + struct rt_sigframe { > + struct siginfo info; > + struct ucontext uc; > + }; > + > + struct ucontext { > + unsigned long __uc_flags; > + struct ucontext *uclink; > + stack_t uc_stack; > + sigset_t uc_sigmask; > + char __glibc_reserved[1024 / 8 - sizeof (sigset_t)]; > + mcontext_t uc_mcontext; > + }; */ > + > +#define SIGFRAME_SIGINFO_SIZE 128 > +#define UCONTEXT_MCONTEXT_OFFSET 176 > + > +static void > +riscv_linux_sigframe_init (const struct tramp_frame *self, > + struct frame_info *this_frame, > + struct trad_frame_cache *this_cache, > + CORE_ADDR func) > +{ > + struct gdbarch *gdbarch = get_frame_arch (this_frame); > + int xlen = riscv_isa_xlen (gdbarch); > + int flen = riscv_isa_flen (gdbarch); > + CORE_ADDR frame_sp = get_frame_sp (this_frame); > + CORE_ADDR mcontext_base; > + CORE_ADDR regs_base; > + > + mcontext_base = frame_sp + SIGFRAME_SIGINFO_SIZE + UCONTEXT_MCONTEXT_OFFSET; > + > + /* Handle the integer registers. The first one is PC, followed by x1 > + through x31. */ > + regs_base = mcontext_base; > + trad_frame_set_reg_addr (this_cache, RISCV_PC_REGNUM, regs_base); > + for (int i = 1; i < 32; i++) > + trad_frame_set_reg_addr (this_cache, RISCV_ZERO_REGNUM + i, > + regs_base + (i * xlen)); > + > + /* Handle the FP registers. First comes the 32 FP registers, followed by > + fcsr. */ > + regs_base += 32 * xlen; > + for (int i = 0; i < 32; i++) > + trad_frame_set_reg_addr (this_cache, RISCV_FIRST_FP_REGNUM + i, > + regs_base + (i * flen)); > + regs_base += 32 * flen; > + trad_frame_set_reg_addr (this_cache, RISCV_CSR_FCSR_REGNUM, regs_base); > + > + /* Choice of the bottom of the sigframe is somewhat arbitrary. */ > + trad_frame_set_id (this_cache, frame_id_build (frame_sp, func)); FYI, I recently added a new function to the trad_frame interface that lets you re-use a register map instead of open-coding the layout of registers. In this case the logic isn't too complex, but you could simplify the handling for the first register bank to just be: trad_frame_set_reg_regmap (this_cache, riscv_linux_gregmap, regs_base, 33 * riscv_isa_xlen (gdbarch)); (I added this new function when writing the signal frame unwinder for riscv-fbsd-tdep.c because I was tired of duplicating the same logic for various signal frame unwinders.) You can see an example of this in the riscv_fbsd_sigframe_init() in riscv-fbsd-tdep.c. (For FreeBSD I also use a register map for the fp registers since FreeBSD is dumping those in a core dump note as well.) -- John Baldwin