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([2a02:908:1242:30e0:ed2c:dc29:543c:9073]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-486eb32d5f1sm11934692f8f.12.2026.09.12.00.37.52 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sat, 12 Sep 2026 00:37:52 -0700 (PDT) Message-ID: Date: Sat, 12 Sep 2026 09:37:51 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] RISC-V: support for vector register accesses via ptrace() in RISC-V Linux native To: Sameer Natu Cc: Greg Savin , gdb-patches@sourceware.org, Andrew Burgess , Palmer Dabbelt , Soham Gargote , Kirill Radkin , Charlie Jenkins References: <20250730105248.661381-2-snatu@whileone.in> Content-Language: en-US From: Heinrich Schuchardt In-Reply-To: <20250730105248.661381-2-snatu@whileone.in> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-BeenThere: gdb-patches@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gdb-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gdb-patches-bounces~public-inbox=simark.ca@sourceware.org On 7/30/25 12:52, Sameer Natu wrote: > Add support for GDB to read from/write to vector registers in a native riscv > linux environment. This uses the NT_RISCV_VECTOR ptrace flag introduced in > Linux 6.5. The values that can be collected by this API are the vector CSRS > vstart, vl, vtype, vcsr, vlenb along with all of the 32 vector registers which > are stored in the pointer datap. > > Different from other architectures, riscv vector units can have a variable size > of between 32 bits and 8124 bits for each of the 32 vector registers. All > vector registers on a single system must have the same size. The size of the > vector registers supported by the hardware is exposed by the vlenb csr. As a > consequence, the size of datap will be different depending on the size of the > hardware's vector registers, which GDB is able to determine by using the vlenb > csr. > > Co-Authored-By: Greg Savin Hello Sameer, I have applied this patch on top of current upstream and it does its job after rebasing. But there are some issues to look into. gdb/MAINTAINERS lists the RISC-V maintainers. I could not see them on copy when I downloaded the patch from the mailing list archive. Maybe that explains that it received little attention. An alternative implementation in [1/2] RISC-V Vector Extension Support https://patchwork.sourceware.org/project/gdb/list/?series=53937 wasn't reviewed by the maintainers either. Will you continue to work on this patch or do you prefer that alternative implementaton? I would add a Signed-off-by: to patches to make it clear in the git changelog who takes ownership of the patch. This specific submission should probably have been marked as v6 as you already sent a v5. The difference seems to be reformatting to 80 characters per line. https://sourceware.org/gdb/wiki/ContributionChecklist describes that typically tests should be added. > Soham Gargote It is unclear what the role of your colleague is. Is Co-Authored-By: missing here? > ---> gdb/arch/riscv.c | 194 ++++++++++++++++++++++++++++++++++- > gdb/nat/riscv-linux-tdesc.c | 69 +++++++++++++ > gdb/nat/riscv-linux-tdesc.h | 28 +++++ > gdb/riscv-linux-nat.c | 181 ++++++++++++++++++++++++++++++++ > gdb/riscv-linux-tdep.c | 145 ++++++++++++++++++++++++++ > gdb/riscv-tdep.c | 51 ++++++++- > gdb/riscv-tdep.h | 6 ++ > gdbserver/linux-riscv-low.cc | 115 +++++++++++++++++++++ > include/elf/common.h | 1 + > 9 files changed, 782 insertions(+), 8 deletions(-) > > diff --git a/gdb/arch/riscv.c b/gdb/arch/riscv.c > index a6188ea3a8c..49b0326e724 100644 > --- a/gdb/arch/riscv.c > +++ b/gdb/arch/riscv.c > @@ -25,17 +25,36 @@ > #include "../features/riscv/64bit-fpu.c" > #include "../features/riscv/rv32e-xregs.c" > > +#include "opcode/riscv-opc.h" > + > #ifndef GDBSERVER > #define STATIC_IN_GDB static > #else > #define STATIC_IN_GDB > #endif > > +#ifdef GDBSERVER > +/* Work around issue where trying to include riscv-tdep.h (to get access to Applying your patch produces whitespace warnings: .git/rebase-apply/patch:30: trailing whitespace. /* Work around issue where trying to include riscv-tdep.h (to get access to .git/rebase-apply/patch:51: trailing whitespace. { .git/rebase-apply/patch:74: trailing whitespace. * expressable in XML format, but this is a special case where length of .git/rebase-apply/patch:80: indent with spaces. long regnum, .git/rebase-apply/patch:81: indent with spaces. const struct riscv_gdbarch_features > + * canonical RISCV_V0_REGNUM declaration > + from that header) is problamtic for gdbserver build. */ > +#define RISCV_V0_REGNUM 4162 > +#else > +#include "riscv-tdep.h" > +#include "defs.h" This results in a build error: In file included from ../../gdb/arch/riscv.c:42: ../../gdb/defs.h:398:4: error: #error gdb/defs.h should not be included manually 398 | # error gdb/defs.h should not be included manually | ^~~~~ > +#endif > + > +static int > +create_feature_riscv_vector_from_features (struct target_desc *result, > + long regnum, > + const struct riscv_gdbarch_features > + features); Please, be consistent in your formatting. You formatted the same differently below. > + > + > /* See arch/riscv.h. */ > > STATIC_IN_GDB target_desc_up > riscv_create_target_description (const struct riscv_gdbarch_features features) > -{ > +{ > /* Now we should create a new target description. */ > target_desc_up tdesc = allocate_target_description (); > > @@ -83,15 +102,180 @@ riscv_create_target_description (const struct riscv_gdbarch_features features) > else if (features.flen == 8) > regnum = create_feature_riscv_64bit_fpu (tdesc.get (), regnum); > > - /* Currently GDB only supports vector features coming from remote > - targets. We don't support creating vector features on native targets > - (yet). */ > if (features.vlen != 0) > - error (_("unable to create vector feature")); > + regnum = > + create_feature_riscv_vector_from_features (tdesc.get (), > + regnum, features); > > return tdesc; > } > > + > + > +/* Usually, these target_desc instances are static for an architecture, and > + * expressable in XML format, but this is a special case where length of > + * a RISC-V vector register is not architecturally fixed to a constant > + * (the maximuim width is a defined constant, > + * but it's nice to tailor a target description the actual VLENB). */ > +static int > +create_feature_riscv_vector_from_features (struct target_desc *result, > + long regnum, > + const struct riscv_gdbarch_features > + features) > +{ > + struct tdesc_feature *feature; > + unsigned long bitsize; > + > + feature = tdesc_create_feature (result, "org.gnu.gdb.riscv.vector"); > + tdesc_type *element_type; > + > + /* If VLENB is present (which we know it is present if execution reaches > + * this function),then we know by definition > + * that it is at least 4 bytes wide. */ > + > + element_type = tdesc_named_type (feature, "uint8"); > + tdesc_create_vector (feature, "bytes", element_type, features.vlen); > + > + element_type = tdesc_named_type (feature, "uint16"); > + tdesc_create_vector (feature, "shorts", element_type, features.vlen / 2); > + > + element_type = tdesc_named_type (feature, "uint32"); > + tdesc_create_vector (feature, "words", element_type, features.vlen / 4); > + > + /* Need VLENB value checks for element chunks larger than 4 byte. */ > + > + if (features.vlen >= 8) > + { > + element_type = tdesc_named_type (feature, "uint64"); > + tdesc_create_vector (feature, "longs", element_type, features.vlen / 8); > + } > + > + /* QEMU and OpenOCD include the quads width in their target descriptions, > + * so we're following that precedent, even if it's not particularly useful > + * in practice, yet. */ > + > + if (features.vlen >= 16) > + { > + element_type = tdesc_named_type (feature, "uint128"); > + tdesc_create_vector (feature, "quads", element_type, > + features.vlen / 16); > + } > + > + tdesc_type_with_fields *type_with_fields; > + type_with_fields = tdesc_create_union (feature, "riscv_vector"); > + tdesc_type *field_type; > + > + if (features.vlen >= 16) > + { > + field_type = tdesc_named_type (feature, "quads"); > + tdesc_add_field (type_with_fields, "q", field_type); > + } > + if (features.vlen >= 8) > + { > + field_type = tdesc_named_type (feature, "longs"); > + tdesc_add_field (type_with_fields, "l", field_type); > + } > + > + /* Again, we know vlenb is >= 4, so no if guards needed for words/shorts/ > + * bytes. */ > + > + field_type = tdesc_named_type (feature, "words"); > + tdesc_add_field (type_with_fields, "w", field_type); > + > + field_type = tdesc_named_type (feature, "shorts"); > + tdesc_add_field (type_with_fields, "s", field_type); > + > + field_type = tdesc_named_type (feature, "bytes"); > + tdesc_add_field (type_with_fields, "b", field_type); > + > + /* Register vector and CSR definitions using stable magic regnums to > + ensure compatibility across GDB and gdbserver builds. */ > + tdesc_create_reg (feature, "vstart", regnum++, 1, NULL, > + features.xlen * 8, "int"); > + tdesc_create_reg (feature, "vxsat", regnum++, 1, NULL, > + features.xlen * 8, "int"); > + tdesc_create_reg (feature, "vxrm", regnum++, 1, NULL, > + features.xlen * 8, "int"); > + tdesc_create_reg (feature, "vcsr", regnum++, 1, NULL, > + features.xlen * 8, "int"); > + tdesc_create_reg (feature, "vl", regnum++, 1, NULL, > + features.xlen * 8, "int"); > + tdesc_create_reg (feature, "vtype", regnum++, 1, NULL, > + features.xlen * 8, "int"); > + tdesc_create_reg (feature, "vlenb", regnum++, 1, NULL, > + features.xlen * 8, "int"); > + > + bitsize = features.vlen * 8; > + tdesc_create_reg (feature, "v0", regnum++, 1, NULL, bitsize, > + "riscv_vector"); > + tdesc_create_reg (feature, "v1", regnum++, 1, NULL, bitsize, > + "riscv_vector"); > + tdesc_create_reg (feature, "v2", regnum++, 1, NULL, bitsize, > + "riscv_vector"); > + tdesc_create_reg (feature, "v3", regnum++, 1, NULL, bitsize, > + "riscv_vector"); > + tdesc_create_reg (feature, "v4", regnum++, 1, NULL, bitsize, > + "riscv_vector"); > + tdesc_create_reg (feature, "v5", regnum++, 1, NULL, bitsize, > + "riscv_vector"); > + tdesc_create_reg (feature, "v6", regnum++, 1, NULL, bitsize, > + "riscv_vector"); > + tdesc_create_reg (feature, "v7", regnum++, 1, NULL, bitsize, > + "riscv_vector"); > + tdesc_create_reg (feature, "v8", regnum++, 1, NULL, bitsize, > + "riscv_vector"); > + tdesc_create_reg (feature, "v9", regnum++, 1, NULL, bitsize, > + "riscv_vector"); > + tdesc_create_reg (feature, "v10", regnum++, 1, NULL, bitsize, > + "riscv_vector"); > + tdesc_create_reg (feature, "v11", regnum++, 1, NULL, bitsize, > + "riscv_vector"); > + tdesc_create_reg (feature, "v12", regnum++, 1, NULL, bitsize, > + "riscv_vector"); > + tdesc_create_reg (feature, "v13", regnum++, 1, NULL, bitsize, > + "riscv_vector"); > + tdesc_create_reg (feature, "v14", regnum++, 1, NULL, bitsize, > + "riscv_vector"); > + tdesc_create_reg (feature, "v15", regnum++, 1, NULL, bitsize, > + "riscv_vector"); > + tdesc_create_reg (feature, "v16", regnum++, 1, NULL, bitsize, > + "riscv_vector"); > + tdesc_create_reg (feature, "v17", regnum++, 1, NULL, bitsize, > + "riscv_vector"); > + tdesc_create_reg (feature, "v18", regnum++, 1, NULL, bitsize, > + "riscv_vector"); > + tdesc_create_reg (feature, "v19", regnum++, 1, NULL, bitsize, > + "riscv_vector"); > + tdesc_create_reg (feature, "v20", regnum++, 1, NULL, bitsize, > + "riscv_vector"); > + tdesc_create_reg (feature, "v21", regnum++, 1, NULL, bitsize, > + "riscv_vector"); > + tdesc_create_reg (feature, "v22", regnum++, 1, NULL, bitsize, > + "riscv_vector"); > + tdesc_create_reg (feature, "v23", regnum++, 1, NULL, bitsize, > + "riscv_vector"); > + tdesc_create_reg (feature, "v24", regnum++, 1, NULL, bitsize, > + "riscv_vector"); > + tdesc_create_reg (feature, "v25", regnum++, 1, NULL, bitsize, > + "riscv_vector"); > + tdesc_create_reg (feature, "v26", regnum++, 1, NULL, bitsize, > + "riscv_vector"); > + tdesc_create_reg (feature, "v27", regnum++, 1, NULL, bitsize, > + "riscv_vector"); > + tdesc_create_reg (feature, "v28", regnum++, 1, NULL, bitsize, > + "riscv_vector"); > + tdesc_create_reg (feature, "v29", regnum++, 1, NULL, bitsize, > + "riscv_vector"); > + tdesc_create_reg (feature, "v30", regnum++, 1, NULL, bitsize, > + "riscv_vector"); > + tdesc_create_reg (feature, "v31", regnum++, 1, NULL, bitsize, > + "riscv_vector"); > + > + > + return regnum; > +} > + > + > #ifndef GDBSERVER > > /* Wrapper used by std::unordered_map to generate hash for feature set. */ > diff --git a/gdb/nat/riscv-linux-tdesc.c b/gdb/nat/riscv-linux-tdesc.c > index 254a25ccefe..c9a8429d441 100644 > --- a/gdb/nat/riscv-linux-tdesc.c > +++ b/gdb/nat/riscv-linux-tdesc.c > @@ -22,14 +22,18 @@ > #include "elf/common.h" > #include "nat/gdb_ptrace.h" > #include "nat/riscv-linux-tdesc.h" > +#include "gdbsupport/gdb_setjmp.h" > > #include > +#include > > /* Work around glibc header breakage causing ELF_NFPREG not to be usable. */ > #ifndef NFPREG > # define NFPREG 33 > #endif > > +static unsigned long safe_read_vlenb (); > + > /* See nat/riscv-linux-tdesc.h. */ > > struct riscv_gdbarch_features > @@ -78,5 +82,70 @@ riscv_linux_read_features (int tid) > break; > } > > + features.vlen = safe_read_vlenb (); > + > return features; > } > + > +static SIGJMP_BUF sigill_guard_jmp_buf; > + > +static void > +sigill_guard (int sig) > +{ > + /* This will gets us back to caller deeper in the call stack, with an > + * indication that an illegal instruction condition was encountered. */ > + SIGLONGJMP (sigill_guard_jmp_buf, -1); > + > + /* Control won't get here. */ > +} > + > + > + > +static unsigned long > +safe_read_vlenb () > +{ > + /* Surrounding the attempt here to read VLENB CSR to have a signal handler > + * set up to trap illegal instruction condition (SIGILL), and if a trap > + * happens during this call,get control back within this function and > + * return 0 in that case. */ > + unsigned long vlenb = 0; > + struct sigaction our_action = { 0 }; > + struct sigaction original_action; > + int sysresult; > + > + > + our_action.sa_handler = sigill_guard; > + > + sysresult = sigaction (SIGILL, &our_action, &original_action); > + if (sysresult != 0) > + { > + perror > + ("Error installing temporary SIGILL handler in safe_read_vlenb()"); > + } > + > + if (SIGSETJMP (sigill_guard_jmp_buf, 1) == 0) > + { > + asm ("csrr %0, vlenb":"=r" (vlenb)); > + } > + else > + { > + /* Must've generated an illegal instruction condition; we'll figure > + * this means no vector unit is present. */ > + vlenb = 0; > + } > + > + > + if (sysresult == 0) > + { > + /* Re-install former handler. */ > + sysresult = sigaction (SIGILL, &original_action, NULL); > + if (sysresult != 0) > + { > + perror > + ("Error re-installing original SIGILL handler in " > + "safe_read_vlenb()"); > + } > + > + } > + return vlenb; > +} > diff --git a/gdb/nat/riscv-linux-tdesc.h b/gdb/nat/riscv-linux-tdesc.h > index de10d91caae..46001e838bd 100644 > --- a/gdb/nat/riscv-linux-tdesc.h > +++ b/gdb/nat/riscv-linux-tdesc.h > @@ -20,9 +20,37 @@ > #define GDB_NAT_RISCV_LINUX_TDESC_H > > #include "arch/riscv.h" > +#include "asm/ptrace.h" > > /* Determine XLEN and FLEN for the LWP identified by TID, and return a > corresponding features object. */ > struct riscv_gdbarch_features riscv_linux_read_features (int tid); > > +#define RISCV_MAX_VLENB (8192) > + > +/* Some branches and/or commits of linux kernel named this > + * "struct __riscv_v_state", > + * and later it was changed to "struct __riscv_v_ext_state", > + * so using a macro to stand-in for that struct type to make > + * it easier to modify in a single place, if compiling against > + * one of those older Linux kernel commits. */ > +#ifndef RISCV_VECTOR_STATE_T > +#define RISCV_VECTOR_STATE_T struct __riscv_v_ext_state > +#endif > + > +/* Struct for use in ptrace() calls for vector CSRs/registers. */ > +struct __riscv_vregs > +{ > + RISCV_VECTOR_STATE_T vstate; > + gdb_byte data[RISCV_MAX_VLENB * 32]; > + /* Data will arrive packed, VLENB bytes per element, not necessarily > + * RISCV_MAX_VLENB bytes per element. */ > +}; > + > +#define VCSR_MASK_VXSAT 0x1 > +#define VCSR_POS_VXSAT 0 > +#define VCSR_MASK_VXRM 0x3 > +#define VCSR_POS_VXRM 1 > + > + > #endif /* GDB_NAT_RISCV_LINUX_TDESC_H */ > diff --git a/gdb/riscv-linux-nat.c b/gdb/riscv-linux-nat.c > index 89f1ddc1b17..285dacc3943 100644 > --- a/gdb/riscv-linux-nat.c > +++ b/gdb/riscv-linux-nat.c > @@ -21,6 +21,7 @@ > #include "linux-nat.h" > #include "riscv-tdep.h" > #include "inferior.h" > +#include "regset.h" > > #include "elf/common.h" > > @@ -124,6 +125,133 @@ supply_fpregset_regnum (struct regcache *regcache, const prfpregset_t *fpregs, > } > } > > +#define MEMBER_SIZE(type, member) sizeof(((type *) 0)->member) > + > +static const regcache_map_entry riscv_linux_vregmap[] = > +{ > + { 1, RISCV_CSR_VSTART_REGNUM, MEMBER_SIZE(struct __riscv_vregs, > + vstate.vstart) }, > + { 1, RISCV_CSR_VL_REGNUM, MEMBER_SIZE(struct __riscv_vregs, vstate.vl) }, > + { 1, RISCV_CSR_VTYPE_REGNUM, MEMBER_SIZE(struct __riscv_vregs, > + vstate.vtype) }, > + { 1, RISCV_CSR_VCSR_REGNUM, MEMBER_SIZE(struct __riscv_vregs, vstate.vcsr) }, > + /* struct __riscv_vregs member "datap" is a pointer that doesn't correspond > + to a register value. In the context of ptrace(), member is always zero, > + with V0..V31 values inline after that. So, skipping datap */ Looking at struct __riscv_v_regset_state in Linux' arch/riscv/include/uapi/asm/ptrace.h datap is not transferred but vlenb is. > + { 1, REGCACHE_MAP_SKIP, MEMBER_SIZE(struct __riscv_vregs, vstate.datap) }, > + /* Here's V0..V31. Specifying 0 as size leads to a call to register_size() > + for size determination */ > + { 32, RISCV_V0_REGNUM, 0 }, > + { 0 }, /* count==0 represents termination of entries */ > +}; > + > +/* Define the vector register regset. */ > + > +static const struct regset riscv_linux_vregset = > +{ > + riscv_linux_vregmap, > + regcache_supply_regset, > +/* Other RISC-V regsets use riscv_supply_regset here; not sure > + * that'd be correct for this case. */ > + regcache_collect_regset > +}; > + > + > +/* Supply RISC-V vector register values (including inferred CSRs) to the > + * GDB regcache. */ > + > +static void > +supply_vregset_regnum (struct regcache *regcache, > + const struct __riscv_vregs *vregs, int regnum) > +{ > + const gdb_byte *buf; > + int vlenb = register_size (regcache->arch (), RISCV_V0_REGNUM); > + > + regcache_supply_regset (&riscv_linux_vregset, regcache, regnum, vregs, > + sizeof(*vregs)); > + > + if (regnum == -1 || regnum == RISCV_CSR_VLENB_REGNUM) > + { > + /* We already have a local copy above, use that > + * (widened for XLEN padding). */ > + > + uint64_t xlen_safe_vlenb = vlenb; > + buf = (gdb_byte *) & xlen_safe_vlenb; > + regcache->raw_supply (RISCV_CSR_VLENB_REGNUM, buf); > + } > + > + if (regnum == -1 || regnum == RISCV_CSR_VXSAT_REGNUM) > + { > + /* This CSR is not part of vregs->vstate literally, but we can infer > + * a value from vcsr. */ > + uint64_t vxsat = > + ((vregs->vstate.vcsr >> VCSR_POS_VXSAT) & VCSR_MASK_VXSAT); > + buf = (gdb_byte *) & vxsat; > + regcache->raw_supply (RISCV_CSR_VXSAT_REGNUM, buf); > + } > + > + if (regnum == -1 || regnum == RISCV_CSR_VXRM_REGNUM) > + { > + /* This CSR is not part of vregs->vstate literally, but we > + * can infer a value from vcsr. */ > + uint64_t vxrm = ((vregs->vstate.vcsr >> VCSR_POS_VXRM) & VCSR_MASK_VXRM); > + buf = (gdb_byte *) & vxrm; > + regcache->raw_supply (RISCV_CSR_VXRM_REGNUM, buf); > + } > +} > + > +/* Collect RISC-V vector register values (including inferred CSRs) > + * from the GDB regcache. */ > +static void > +fill_vregset (const struct regcache *regcache, struct __riscv_vregs *vregs, > + int regnum) > +{ > + regcache_collect_regset (&riscv_linux_vregset, regcache, regnum, vregs, > + sizeof(*vregs)); > + > + if (regnum == -1 || regnum == RISCV_CSR_VCSR_REGNUM || > + regnum == RISCV_CSR_VXSAT_REGNUM > + || regnum == RISCV_CSR_VXRM_REGNUM) > + { > + uint64_t vxsat_from_regcache; > + uint64_t vxrm_from_regcache; > + > + if ( ! (regnum == -1 || regnum == RISCV_CSR_VCSR_REGNUM) ) > + { > + /* We don't already have the VCSR value, from the > + * earlier regcache_collect_regset call, so let's get it now. */ > + regcache_collect_regset (&riscv_linux_vregset, regcache, > + RISCV_CSR_VCSR_REGNUM, vregs, sizeof(*vregs)); > + } > + > + if (regnum == RISCV_CSR_VXSAT_REGNUM) > + { > + /* Overwrite VCSR with the VXSAT bit here. */ > + gdb_byte *buf = (gdb_byte *) &vxsat_from_regcache; > + regcache->raw_collect (RISCV_CSR_VXSAT_REGNUM, buf); > + vregs->vstate.vcsr &= ~((uint64_t) VCSR_MASK_VXSAT << > + VCSR_POS_VXSAT); > + vregs->vstate.vcsr |= ((vxsat_from_regcache & VCSR_MASK_VXSAT) << > + VCSR_POS_VXSAT); > + } > + > + if (regnum == RISCV_CSR_VXRM_REGNUM) > + { > + /* Overwrite VCSR with the VXRM bit here. */ > + gdb_byte *buf = (gdb_byte *) &vxsat_from_regcache; > + regcache->raw_collect (RISCV_CSR_VXRM_REGNUM, buf); > + vregs->vstate.vcsr &= ~((uint64_t) VCSR_MASK_VXRM << VCSR_POS_VXRM); > + vregs->vstate.vcsr |= ((vxrm_from_regcache & VCSR_MASK_VXRM) > + << VCSR_POS_VXRM); vxrm_from_regcache is never initialized. So you are using a random value from the stack. Can we completely remove the variable? In function \u2018void fill_vregset(const regcache*, __riscv_vregs*, int)\u2019, inlined from \u2018virtual void riscv_linux_nat_target::store_registers(regcache*, int)\u2019 at ../../gdb/riscv-linux-nat.c:498:17: ../../gdb/riscv-linux-nat.c:245:27: warning: \u2018vxrm_from_regcache\u2019 may be used uninitialized [-Wmaybe-uninitialized] 244 | vregs->vstate.vcsr |= ((vxrm_from_regcache & VCSR_MASK_VXRM) | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 245 | << VCSR_POS_VXRM); | ^~~~~~~~~~~~~~~~~ ../../gdb/riscv-linux-nat.c: In member function \u2018virtual void riscv_linux_nat_target::store_registers(regcache*, int)\u2019: ../../gdb/riscv-linux-nat.c:217:16: note: \u2018vxrm_from_regcache\u2019 was declared here 217 | uint64_t vxrm_from_regcache; | ^~~~~~~~~~~~~~~~~~ > + } > + } > + > + /* VLENB register is not writable, so that's why nothing is collected > + * here for that register. */ > + > +} > + > + > /* Copy all floating point registers from regset FPREGS into REGCACHE. */ > > void > @@ -254,6 +382,30 @@ riscv_linux_nat_target::fetch_registers (struct regcache *regcache, int regnum) > supply_fpregset_regnum (regcache, ®s, regnum); > } > > + /* If Linux kernel was not configured to support RISC-V vectors, then > + * the ptrace call will return -1, and we just won't get vector registers, > + * but in that case it wouldn't be an error that needs user attention. */ > + if ((regnum >= RISCV_V0_REGNUM && regnum <= RISCV_V31_REGNUM) > + || (regnum == RISCV_CSR_VSTART_REGNUM) > + || (regnum == RISCV_CSR_VL_REGNUM) > + || (regnum == RISCV_CSR_VTYPE_REGNUM) > + || (regnum == RISCV_CSR_VCSR_REGNUM) > + || (regnum == RISCV_CSR_VLENB_REGNUM) > + || (regnum == RISCV_CSR_VXSAT_REGNUM) > + || (regnum == RISCV_CSR_VXRM_REGNUM) > + || (regnum == -1)) > + { > + struct iovec iov; > + struct __riscv_vregs vregs; > + > + iov.iov_base = &vregs; > + iov.iov_len = sizeof (vregs); > + > + if (ptrace (PTRACE_GETREGSET, tid, NT_RISCV_VECTOR, > + (PTRACE_TYPE_ARG3) & iov) == 0) > + supply_vregset_regnum (regcache, &vregs, regnum); > + } > + > if ((regnum == RISCV_CSR_MISA_REGNUM) > || (regnum == -1)) > { > @@ -323,6 +475,35 @@ riscv_linux_nat_target::store_registers (struct regcache *regcache, int regnum) > } > } > > + /* VLENB isn't writable, so we'll skip considering that one, if it's being > + specified alone. */ > + if ((regnum >= RISCV_V0_REGNUM && regnum <= RISCV_V31_REGNUM) > + || (regnum == RISCV_CSR_VSTART_REGNUM) > + || (regnum == RISCV_CSR_VL_REGNUM) > + || (regnum == RISCV_CSR_VTYPE_REGNUM) > + || (regnum == RISCV_CSR_VCSR_REGNUM) > + || (regnum == RISCV_CSR_VXSAT_REGNUM) > + || (regnum == RISCV_CSR_VXRM_REGNUM) > + || (regnum == -1)) > + { > + struct iovec iov; > + struct __riscv_vregs vregs; > + > + iov.iov_base = &vregs; > + iov.iov_len = sizeof (vregs); > + > + if (ptrace (PTRACE_GETREGSET, tid, NT_RISCV_VECTOR, > + (PTRACE_TYPE_ARG3) & iov) == 0) > + { > + fill_vregset (regcache, &vregs, regnum); > + > + if (ptrace (PTRACE_SETREGSET, tid, NT_RISCV_VECTOR, > + (PTRACE_TYPE_ARG3) & iov) == -1) > + perror_with_name (_("Couldn't set vector registers")); > + } > + } > + > + > /* Access to CSRs has potential security issues, don't support them for > now. */ > } > diff --git a/gdb/riscv-linux-tdep.c b/gdb/riscv-linux-tdep.c > index e5d77e7f208..623a5832241 100644 > --- a/gdb/riscv-linux-tdep.c > +++ b/gdb/riscv-linux-tdep.c > @@ -39,6 +39,11 @@ extern unsigned int record_debug; > > #define RISCV_NR_rt_sigreturn 139 > > +/* Magic number written to the head.magic field of struct __sc_riscv_v_state > + * that kernel places in the reserved area of struct sigcontext. > + * Comes from . */ > +#define RVV_MAGIC 0x53465457 > + > /* Define the general register mapping. The kernel puts the PC at offset 0, > gdb puts it at offset 32. Register x0 is always 0 and can be ignored. > Registers x1 to x31 are in the same place. */ > @@ -127,8 +132,134 @@ static const struct tramp_frame riscv_linux_sigframe = { > mcontext_t uc_mcontext; > }; */ > > + > +/* Read RVV magic and size fields from address REGS_BASE and return true if a > + * valid RISC-V vector context header is found, otherwise return false. > + * THIS_FRAME is used for the architecture and byte-order when > + * reading memory. VLEN and XLEN are the v-register and x-register > + * sizes (in bytes) and are used for validation. */ > + > +static bool > +riscv_linux_vector_sigframe_header_check (frame_info_ptr this_frame, > + int vlen, int xlen, > + CORE_ADDR regs_base) > +{ > + uint32_t rvv_magic; > + uint32_t rvv_size; > + bool info_good = false; > + > + /* If vector information is available, then we should see this > + structure at this address: > + struct __riscv_ctx_hdr { > + __u32 magic; (RVV_MAGIC). > + __u32 size; > + (size of struct __sc_riscv_v_state + vector register data size (32*VLENB)) > + } head; */ > + > + rvv_magic = > + get_frame_memory_unsigned (this_frame, regs_base, sizeof (rvv_magic)); > + regs_base += sizeof (rvv_magic); > + rvv_size = > + get_frame_memory_unsigned (this_frame, regs_base, sizeof (rvv_magic)); > + regs_base += sizeof (rvv_size); > + > + > + info_good = (rvv_magic == RVV_MAGIC); > + if (!info_good) > + { > + /* Not an error, because kernels can be configured without CONFIG_VECTOR, > + * but worth noting if frame debug setting is turned on. */ > + frame_debug_printf > + ("Did not find RISC-V vector information in ucontext" > + "(kernel not built with CONFIG_VECTOR?)"); > + > + return false; > + } > + > + if (frame_debug) > + { > + uint32_t expected_rvv_size; > + > + frame_debug_printf > + ("Located RISC-V vector information in signal frame ucontext" > + "(info size %u)", > + rvv_size); > + > + /* sanity check the reported size; should be sizeof(uint32_t) + > + * sizeof(uint32_t) + 5 * XLENB + 32 * vlen */ > + expected_rvv_size = sizeof (uint32_t) /* magic */ + > + sizeof (uint32_t) /* size */ + > + 5 * xlen /* vstart, vl, vtype, vcsr, and datap */ + > + 32 * vlen; /* v0..v31 values */ > + > + if (rvv_size != expected_rvv_size) > + { > + warning (_("Size in RISC-V vector information header in ucontext" > + "(%u) differs from expected size (%u)."), > + rvv_size, expected_rvv_size); > + > + /* Additional debug details if frame_debug is on. */ > + frame_debug_printf ("Detailed size mismatch: expected %u based on" > + "VLEN=%d and XLEN=%d", > + expected_rvv_size, vlen, xlen); > + } > + } > + > + return info_good; > +} > + > +static CORE_ADDR > +riscv_linux_sigframe_vector_init (frame_info_ptr this_frame, > + struct trad_frame_cache *this_cache, > + CORE_ADDR regs_base, int xlen, int vlen) > +{ > + int vfieldidx; > + CORE_ADDR p_datap; > + CORE_ADDR datap; > + > + /* vstart, vl, vtype, vcsr, and datap are XLEN sized fields (unsigned long) > + * from this point. */ > + vfieldidx = 0; > + trad_frame_set_reg_addr (this_cache, RISCV_CSR_VSTART_REGNUM, > + regs_base + (vfieldidx * xlen)); > + vfieldidx++; > + trad_frame_set_reg_addr (this_cache, RISCV_CSR_VL_REGNUM, > + regs_base + (vfieldidx * xlen)); > + > + vfieldidx++; > + trad_frame_set_reg_addr (this_cache, RISCV_CSR_VTYPE_REGNUM, > + regs_base + (vfieldidx * xlen)); > + > + vfieldidx++; > + trad_frame_set_reg_addr (this_cache, RISCV_CSR_VCSR_REGNUM, > + regs_base + (vfieldidx * xlen)); > + > + /* For the datap member, there is one level of memory indirection > + * to get the address of the block of values for v0..v31. */ > + vfieldidx++; > + p_datap = regs_base + (vfieldidx * xlen); > + datap = get_frame_memory_unsigned (this_frame, p_datap, xlen); > + regs_base = datap; > + for (int i = 0; i < 32; i++) > + { > + trad_frame_set_reg_addr (this_cache, RISCV_V0_REGNUM + i, > + regs_base + (i * vlen)); > + } > + regs_base += 32 * vlen; > + > + return regs_base; > +} > + > + > #define SIGFRAME_SIGINFO_SIZE 128 > #define UCONTEXT_MCONTEXT_OFFSET 176 > +/* offset of struct mcontext's __reserved field, > + * which is where the struct __sc_riscv_v_state is overlaid */ > +#define MCONTEXT_VECTOR_OFFSET 784 > + > +/* size of struct __riscv_ctx_hdr {__u32 magic; __u32 size; } */ > +#define RISCV_CONTEXT_HEADER_SIZE 8 > + > > static void > riscv_linux_sigframe_init (const struct tramp_frame *self, > @@ -139,6 +270,7 @@ riscv_linux_sigframe_init (const struct tramp_frame *self, > struct gdbarch *gdbarch = get_frame_arch (this_frame); > int xlen = riscv_isa_xlen (gdbarch); > int flen = riscv_isa_flen (gdbarch); > + int vlen = riscv_isa_vlen (gdbarch); > CORE_ADDR frame_sp = get_frame_sp (this_frame); > CORE_ADDR mcontext_base; > CORE_ADDR regs_base; > @@ -162,6 +294,19 @@ riscv_linux_sigframe_init (const struct tramp_frame *self, > regs_base += 32 * flen; > trad_frame_set_reg_addr (this_cache, RISCV_CSR_FCSR_REGNUM, regs_base); > > + /* Handle the vector registers, if present. */ > + if (vlen > 0) > + { > + regs_base = mcontext_base + MCONTEXT_VECTOR_OFFSET; > + if (riscv_linux_vector_sigframe_header_check > + (this_frame, vlen, xlen, regs_base)) > + { > + regs_base += RISCV_CONTEXT_HEADER_SIZE;/* advance past the header */ > + riscv_linux_sigframe_vector_init (this_frame, this_cache, regs_base, > + xlen, vlen); > + } > + } > + > /* Choice of the bottom of the sigframe is somewhat arbitrary. */ > trad_frame_set_id (this_cache, frame_id_build (frame_sp, func)); > } > diff --git a/gdb/riscv-tdep.c b/gdb/riscv-tdep.c > index f5b85230e71..8e8f3da7d6d 100644 > --- a/gdb/riscv-tdep.c > +++ b/gdb/riscv-tdep.c > @@ -47,6 +47,7 @@ > #include "remote.h" > #include "target-descriptions.h" > #include "dwarf2/frame.h" > +#include "dwarf2/expr.h" > #include "user-regs.h" > #include "valprint.h" > #include "opcode/riscv-opc.h" > @@ -653,6 +654,14 @@ struct riscv_vector_feature : public riscv_register_feature > { RISCV_V0_REGNUM + 29, { "v29" } }, > { RISCV_V0_REGNUM + 30, { "v30" } }, > { RISCV_V0_REGNUM + 31, { "v31" } }, > + /* vector CSRs */ > + { RISCV_CSR_VSTART_REGNUM, { "vstart" } }, > + { RISCV_CSR_VXSAT_REGNUM, { "vxsat" } }, > + { RISCV_CSR_VXRM_REGNUM, { "vxrm" } }, > + { RISCV_CSR_VL_REGNUM, { "vl" } }, > + { RISCV_CSR_VTYPE_REGNUM, { "vtype" } }, > + { RISCV_CSR_VCSR_REGNUM, { "vcsr" } }, > + { RISCV_CSR_VLENB_REGNUM, { "vlenb" } }, > }; > } > > @@ -684,10 +693,17 @@ struct riscv_vector_feature : public riscv_register_feature > return true; > } > > - /* Check all of the vector registers are present. */ > + /* Check all of the vector registers are present. We also > + check that the vector CSRs are present too, though if these > + are missing this is not fatal. */ > for (const auto ® : m_registers) > { > - if (!reg.check (tdesc_data, feature_vector, aliases)) > + bool found = reg.check (tdesc_data, feature_vector, aliases); > + > + bool is_ctrl_reg_p = !(reg.regnum >= RISCV_V0_REGNUM && > + reg.regnum <= RISCV_V31_REGNUM); > + > + if (!found && !is_ctrl_reg_p) > return false; > } > > @@ -697,6 +713,13 @@ struct riscv_vector_feature : public riscv_register_feature > int vector_bitsize = -1; > for (const auto ® : m_registers) > { > + > + bool is_ctrl_reg_p = !(reg.regnum >= RISCV_V0_REGNUM && > + reg.regnum <= RISCV_V31_REGNUM); > + > + if (is_ctrl_reg_p) > + continue; > + > int reg_bitsize = -1; > for (const char *name : reg.names) > { > @@ -819,6 +842,16 @@ riscv_abi_embedded (struct gdbarch *gdbarch) > return tdep->abi_features.embedded; > } > > +/* See riscv-tdep.h. */ > + > +int > +riscv_isa_vlen (struct gdbarch *gdbarch) > +{ > + riscv_gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); > + return tdep->isa_features.vlen; > +} > + > + > /* Return true if the target for GDBARCH has floating point hardware. */ > > static bool > @@ -1470,7 +1503,19 @@ riscv_register_reggroup_p (struct gdbarch *gdbarch, int regnum, > return 0; gdb now uses false and true. > } > else if (reggroup == vector_reggroup) > - return (regnum >= RISCV_V0_REGNUM && regnum <= RISCV_V31_REGNUM); > + { > + if (regnum >= RISCV_V0_REGNUM && regnum <= RISCV_V31_REGNUM) > + return 1; > + if (regnum == RISCV_CSR_VSTART_REGNUM > + || regnum == RISCV_CSR_VXSAT_REGNUM > + || regnum == RISCV_CSR_VXRM_REGNUM > + || regnum == RISCV_CSR_VL_REGNUM > + || regnum == RISCV_CSR_VTYPE_REGNUM > + || regnum == RISCV_CSR_VCSR_REGNUM > + || regnum == RISCV_CSR_VLENB_REGNUM) > + return 1; > + return 0; > + } > else > return 0; > } > diff --git a/gdb/riscv-tdep.h b/gdb/riscv-tdep.h > index 2903aefd007..82213f820f3 100644 > --- a/gdb/riscv-tdep.h > +++ b/gdb/riscv-tdep.h > @@ -50,6 +50,7 @@ enum > RISCV_LAST_FP_REGNUM = 64, /* Last Floating Point Register */ > > RISCV_FIRST_CSR_REGNUM = 65, /* First CSR */ > + > #define DECLARE_CSR(name, num, class, define_version, abort_version) \ > RISCV_ ## num ## _REGNUM = RISCV_FIRST_CSR_REGNUM + num, > #include "opcode/riscv-opc.h" > @@ -158,6 +159,11 @@ extern int riscv_abi_flen (struct gdbarch *gdbarch); > argument registers. */ > extern bool riscv_abi_embedded (struct gdbarch *gdbarch); > > +/* Return the width in bytes of the hardware vector registers for > + GDBARCH. If this architecture has no vector registers, then > + return 0. */ > +extern int riscv_isa_vlen (struct gdbarch *gdbarch); > + > /* Single step based on where the current instruction will take us. */ > extern std::vector riscv_software_single_step > (struct regcache *regcache); > diff --git a/gdbserver/linux-riscv-low.cc b/gdbserver/linux-riscv-low.cc > index 8c742f406a2..811dfa602e1 100644 > --- a/gdbserver/linux-riscv-low.cc > +++ b/gdbserver/linux-riscv-low.cc > @@ -161,6 +161,118 @@ riscv_store_fpregset (struct regcache *regcache, const void *buf) > supply_register_by_name (regcache, "fcsr", regbuf); > } > > +/* Collect vector registers from REGCACHE into BUF. */ > + > +static void > +riscv_fill_vregset (struct regcache *regcache, void *buf) > +{ > + const struct target_desc *tdesc = regcache->tdesc; > + int regno = find_regno (tdesc, "v0"); > + int vlenb = register_size (regcache->tdesc, regno); > + uint64_t u64_vlenb = vlenb; /* pad to max XLEN for buffer conversion */ > + uint64_t u64_vxsat = 0; > + uint64_t u64_vxrm = 0; > + uint64_t u64_vcsr = 0; > + gdb_byte *regbuf; > + int i; > + > + /* Since vxsat and equivalent bits in vcsr are aliases (and same for vxrm), > + * we have a dilemma. For this gdb -> gdbserver topology, > + * if the aliased pairs have values that disagree, then > + * which value should take precedence? We don't know which alias was most > + * recently assigned. We're just getting a block of register values > + * including vxsat, vxrm, and vcsr. > + * We have to impose some kind of rule for predictable resolution to resolve > + * any inconsistency. For now, let's say that vxsat and vxrm take precedence, > + * and those values will be applied to the corresponding fields in vcsr. > + * Reconcile these 3 interdependent registers now. */ > + regbuf = (gdb_byte *) & u64_vcsr; > + collect_register_by_name (regcache, "vcsr", regbuf); > + regbuf = (gdb_byte *) & u64_vxsat; > + collect_register_by_name (regcache, "vxsat", regbuf); > + regbuf = (gdb_byte *) & u64_vxrm; > + collect_register_by_name (regcache, "vxrm", regbuf); > + > + u64_vcsr &= ~((uint64_t)VCSR_MASK_VXSAT << VCSR_POS_VXSAT); > + u64_vcsr |= ((u64_vxsat & VCSR_MASK_VXSAT) << VCSR_POS_VXSAT); > + u64_vcsr &= ~((uint64_t)VCSR_MASK_VXRM << VCSR_POS_VXRM); > + u64_vcsr |= ((u64_vxrm & VCSR_MASK_VXRM) << VCSR_POS_VXRM); > + > + /* Replace the original vcsr value with the "cooked" value. */ > + regbuf = (gdb_byte *) & u64_vcsr; > + supply_register_by_name (regcache, "vcsr", regbuf); > + > + /* Now stage the ptrace buffer (it'll receive the cooked vcsr value). */ > + > + regbuf = (gdb_byte *) buf + offsetof (struct __riscv_vregs, vstate.vstart); > + collect_register_by_name (regcache, "vstart", regbuf); > + regbuf = (gdb_byte *) buf + offsetof (struct __riscv_vregs, vstate.vl); > + collect_register_by_name (regcache, "vl", regbuf); > + regbuf = (gdb_byte *) buf + offsetof (struct __riscv_vregs, vstate.vtype); > + collect_register_by_name (regcache, "vtype", regbuf); > + regbuf = (gdb_byte *) buf + offsetof (struct __riscv_vregs, vstate.vcsr); > + collect_register_by_name (regcache, "vcsr", regbuf); > + regbuf = (gdb_byte *) & u64_vlenb; > + collect_register_by_name (regcache, "vlenb", regbuf); > + > + > + regbuf = (gdb_byte *) buf + offsetof (struct __riscv_vregs, data); > + for (i = 0; i < 32; i++, regbuf += vlenb) > + collect_register (regcache, regno + i, regbuf); > +} > + > +/* Supply vector registers from BUF into REGCACHE. */ > + > +static void > +riscv_store_vregset (struct regcache *regcache, const void *buf) > +{ > + const struct target_desc *tdesc = regcache->tdesc; > + int regno = find_regno (tdesc, "v0"); > + int vlenb = register_size (regcache->tdesc, regno); > + /* Pad to max XLEN for buffer conversion. */ > + uint64_t u64_vlenb = vlenb; > + uint64_t vcsr; > + uint64_t vxsat; > + uint64_t vxrm; > + const gdb_byte *regbuf; > + int i; > + > + regbuf = > + (const gdb_byte *) buf + offsetof (struct __riscv_vregs, vstate.vstart); > + supply_register_by_name (regcache, "vstart", regbuf); > + regbuf = > + (const gdb_byte *) buf + offsetof (struct __riscv_vregs, vstate.vl); > + supply_register_by_name (regcache, "vl", regbuf); > + regbuf = > + (const gdb_byte *) buf + offsetof (struct __riscv_vregs, vstate.vtype); > + supply_register_by_name (regcache, "vtype", regbuf); > + regbuf = > + (const gdb_byte *) buf + offsetof (struct __riscv_vregs, vstate.vcsr); > + supply_register_by_name (regcache, "vcsr", regbuf); > + /* lso store offga non-byte-wise copy of vcsr, > + * to derive values for vxsat and vxrm. */ > + vcsr = *(uint64_t*)regbuf; > + /* vlenb isn't part of vstate, but we have already inferred its > + * value by running code on this > + hart, and we're assuming homogeneous VLENB if it's an SMP system. */ > + regbuf = (gdb_byte *) & u64_vlenb; > + supply_register_by_name (regcache, "vlenb", regbuf); > + > + /* vxsat and vxrm, are not part of vstate, so we have to extract from VCSR > + value. */ > + vxsat = ((vcsr >> VCSR_POS_VXSAT) & VCSR_MASK_VXSAT); > + regbuf = (gdb_byte *) &vxsat; > + supply_register_by_name (regcache, "vxsat", regbuf); > + vxrm = ((vcsr >> VCSR_POS_VXRM) & VCSR_MASK_VXRM); > + regbuf = (gdb_byte *) &vxrm; > + supply_register_by_name (regcache, "vxrm", regbuf); > + > + /* v0..v31. */ > + regbuf = (const gdb_byte *) buf + offsetof (struct __riscv_vregs, data); > + for (i = 0; i < 32; i++, regbuf += vlenb) > + supply_register (regcache, regno + i, regbuf); > +} > + > /* RISC-V/Linux regsets. FPRs are optional and come in different sizes, > so define multiple regsets for them marking them all as OPTIONAL_REGS > rather than FP_REGS, so that "regsets_fetch_inferior_registers" picks > @@ -178,6 +290,9 @@ static struct regset_info riscv_regsets[] = { > { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_FPREGSET, > sizeof (struct __riscv_mc_f_ext_state), OPTIONAL_REGS, > riscv_fill_fpregset, riscv_store_fpregset }, > + { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_RISCV_VECTOR, > + sizeof (struct __riscv_vregs), OPTIONAL_REGS, > + riscv_fill_vregset, riscv_store_vregset }, > NULL_REGSET > }; > > diff --git a/include/elf/common.h b/include/elf/common.h > index 0d9a7b7a8a9..6e83704e4fa 100644 > --- a/include/elf/common.h > +++ b/include/elf/common.h > @@ -762,6 +762,7 @@ > /* note name must be "LINUX". */ > #define NT_RISCV_CSR 0x900 /* RISC-V Control and Status Registers */ > /* note name must be "LINUX". */ > +#define NT_RISCV_VECTOR 0x901 /* RISC-V Vector Registers. */ This is now in upstream binutils-gdb. Best regards Heinrich > #define NT_SIGINFO 0x53494749 /* Fields of siginfo_t. */ > #define NT_FILE 0x46494c45 /* Description of mapped files. */ >