Re: [PATCH v3 09/24] AArch64: Add target description/feature for MTE registers

Luis Machado via Gdb-patches
2020-12-28T18:28:52Z

On 12/25/20 9:10 PM, Simon Marchi wrote:
> On 2020-11-09 12:04 p.m., Luis Machado via Gdb-patches wrote:
>> This patch adds a target description and feature "mte" for aarch64.
>>
>> It includes one new register, tag_ctl, that can be used to configure the
>> tag generation rules and sync/async modes.
>
> Can you explain this sentence? I especially don't understand "sync/async modes"..
>

Sure. This register is exposed by the kernel as a set of bits that you
can use to control some characteristics of the memory tagging mecanism.

There are 3 modes of operation: ignore, sync and async. From the kernel
documentation:

- *Ignore* - This is the default mode. The CPU (and kernel) ignores the
tag check fault.

- *Synchronous* - The kernel raises a ``SIGSEGV`` synchronously, with
``.si_code = SEGV_MTESERR`` and ``.si_addr = <fault-address>``. The
memory access is not performed. If ``SIGSEGV`` is ignored or blocked
by the offending thread, the containing process is terminated with a
``coredump``.

- *Asynchronous* - The kernel raises a ``SIGSEGV``, in the offending
thread, asynchronously following one or multiple tag check faults,
with ``.si_code = SEGV_MTEAERR`` and ``.si_addr = 0`` (the faulting
address is unknown).

So, basically, we have options to ignore the tag fault, report a tag
fault without extra information (async) and report a tag fault with
precise information (sync).

> The code itself LGTM.
>
> Simon
>