From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from simark.ca by simark.ca with LMTP id wep/G7dF+2QRIBMAWB0awg (envelope-from ) for ; Fri, 08 Sep 2023 12:03:03 -0400 Authentication-Results: simark.ca; dkim=pass (1024-bit key; secure) header.d=sourceware.org header.i=@sourceware.org header.a=rsa-sha256 header.s=default header.b=s1mleTmr; dkim-atps=neutral Received: by simark.ca (Postfix, from userid 112) id 672151E0C3; Fri, 8 Sep 2023 12:03:03 -0400 (EDT) Received: from server2.sourceware.org (server2.sourceware.org [8.43.85.97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (prime256v1) server-digest SHA256) (No client certificate requested) by simark.ca (Postfix) with ESMTPS id 5528B1E092 for ; Fri, 8 Sep 2023 12:03:01 -0400 (EDT) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id DD8BB3857835 for ; Fri, 8 Sep 2023 16:03:00 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org DD8BB3857835 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1694188980; bh=HiBGRDRhJ2CAZ5MPiUwm02Q/tH1TEKz9+seICdBOKR4=; h=Date:Subject:To:Cc:References:In-Reply-To:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From:Reply-To:From; b=s1mleTmrbtua9buresWSyfpP+OxcEglLdo2VENWyurF/9qejkXE8kcPnpubf94q8v 23Gln/DahPaQn/4iH4a4VMcncSKg0/m55k5hSbWd5wrNTDb9c6uwn2wtWHp8RcIw1w hMq67hsO7fZSJRdg1Ky+D0NyWHGBeDFQFPxMdlhA= Received: from smtp.polymtl.ca (smtp.polymtl.ca [132.207.4.11]) by sourceware.org (Postfix) with ESMTPS id 6750C3858C60 for ; Fri, 8 Sep 2023 16:02:41 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 6750C3858C60 Received: from simark.ca (simark.ca [158.69.221.121]) (authenticated bits=0) by smtp.polymtl.ca (8.14.7/8.14.7) with ESMTP id 388G2WRx006918 (version=TLSv1/SSLv3 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 8 Sep 2023 12:02:37 -0400 DKIM-Filter: OpenDKIM Filter v2.11.0 smtp.polymtl.ca 388G2WRx006918 Received: from [172.16.0.192] (192-222-143-198.qc.cable.ebox.net [192.222.143.198]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits) key-exchange X25519 server-signature ECDSA (prime256v1) server-digest SHA256) (No client certificate requested) by simark.ca (Postfix) with ESMTPSA id 5C5431E092; Fri, 8 Sep 2023 12:02:32 -0400 (EDT) Message-ID: Date: Fri, 8 Sep 2023 12:02:31 -0400 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v5 12/16] [gdb/generic] corefile/bug: Use thread-specific gdbarch when dumping register state to core files Content-Language: fr To: Luis Machado , gdb-patches@sourceware.org Cc: thiago.bauermann@linaro.org References: <20230907152018.1031257-1-luis.machado@arm.com> <20230907152018.1031257-13-luis.machado@arm.com> <971a9e69-a802-7354-728e-573d4c85c3f9@arm.com> <680b67cc-4330-4425-9860-02666f7d0e0b@polymtl.ca> In-Reply-To: <680b67cc-4330-4425-9860-02666f7d0e0b@polymtl.ca> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Poly-FromMTA: (simark.ca [158.69.221.121]) at Fri, 8 Sep 2023 16:02:33 +0000 X-Spam-Status: No, score=-3031.9 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, RCVD_IN_DNSWL_LOW, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gdb-patches@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gdb-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , From: Simon Marchi via Gdb-patches Reply-To: Simon Marchi Errors-To: gdb-patches-bounces+public-inbox=simark.ca@sourceware.org Sender: "Gdb-patches" > Please remind me, does an AArch64 core file contain one target > description per thread, to account for the fact that different threads > could have different register layouts? Or right now we just hope that > all threads use the same target description (which might be different > from what the inferior started with)? I think that the commit message on the following patch answers my question: there isn't a full target desc for each thread, but using the process-wide target desc plus by reading some bits from the SVE (and eventually SME) state, you can derive on target desc per thread. That sounds right? Simon