From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 6342 invoked by alias); 10 May 2015 01:04:14 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Received: (qmail 6333 invoked by uid 89); 10 May 2015 01:04:14 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-0.9 required=5.0 tests=AWL,BAYES_00,KAM_LAZY_DOMAIN_SECURITY,T_RP_MATCHES_RCVD,UNPARSEABLE_RELAY autolearn=no version=3.3.2 X-HELO: cvs.linux-mips.org Received: from eddie.linux-mips.org (HELO cvs.linux-mips.org) (148.251.95.138) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Sun, 10 May 2015 01:04:12 +0000 Received: (from localhost user: 'macro', uid#1010) by eddie.linux-mips.org with ESMTP id S27012902AbbEJBEIC0RpA (ORCPT ); Sun, 10 May 2015 03:04:08 +0200 Date: Sun, 10 May 2015 01:04:00 -0000 From: "Maciej W. Rozycki" To: Pedro Alves cc: Yao Qi , gdb-patches@sourceware.org Subject: Re: [PATCH] [gdbserver] Disable conditional breakpoints on no-hardware-single-step targets In-Reply-To: <554A368F.4060309@redhat.com> Message-ID: References: <1430411029-12097-1-git-send-email-qiyaoltc@gmail.com> <554A368F.4060309@redhat.com> User-Agent: Alpine 2.11 (LFD 23 2013-08-11) MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII X-IsSubscribed: yes X-SW-Source: 2015-05/txt/msg00228.txt.bz2 On Wed, 6 May 2015, Pedro Alves wrote: > > It is worse if the arm/thumb interworking is considered. Nowadays, > > GDBserver arm backend unconditionally inserts arm breakpoint, > > > > /* Define an ARM-mode breakpoint; we only set breakpoints in the C > > library, which is most likely to be ARM. If the kernel supports > > clone events, we will never insert a breakpoint, so even a Thumb > > C library will work; so will mixing EABI/non-EABI gdbserver and > > application. */ > > #ifndef __ARM_EABI__ > > (const unsigned char *) &arm_breakpoint, > > #else > > (const unsigned char *) &arm_eabi_breakpoint, > > #endif > > > > note that the comments are no longer valid as C library can be compiled > > in thumb mode. > > > > When GDBserver steps over a breakpoint in arm mode function, which > > returns to thumb mode, GDBserver will insert arm mode breakpoint by > > mistake and the program will crash. GDBserver alone is unable to > > determine the arm/thumb mode given a PC address. See how GDB does > > it in arm-tdep.c:arm_pc_is_thumb. > > Of a random PC address no, but in gdbserver's case, I think that it > would work, because we need it to step over a breakpoint that is > at the current PC. So we could: > > #1 - Get the mode of the current PC from the thread's $cpsr register. > > #2 - Get the mode of the next PC by looking at the instruction that is > about to be executed (at current PC). If bx and blx, which change > modes, check the thumb bit of the destination address. > For all other instructions, same mode as the current PC. A similar issue exists for the three MIPS ISA modes and gdbserver will not have enough data to determine which of the two of the MIPS16 and microMIPS instruction sets to use for the compressed mode. Only GDB knows that, at the last resort having been told by the user. Maciej