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Rozycki" To: Sebastian Huber cc: Andrew Burgess , gdb-patches Subject: Re: [PATCH 4/4] sim/mips: Recognise a software interrupt request In-Reply-To: <1434207978.14132.1787099225217.JavaMail.zimbra@embedded-brains.de> Message-ID: References: <20260816234357.278358-1-sebastian.huber@embedded-brains.de> <20260816234357.278358-5-sebastian.huber@embedded-brains.de> <87qzjv1zh3.fsf@redhat.com> <1434207978.14132.1787099225217.JavaMail.zimbra@embedded-brains.de> User-Agent: Alpine 2.21 (DEB 202 2017-01-01) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII X-BeenThere: gdb-patches@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gdb-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gdb-patches-bounces~public-inbox=simark.ca@sourceware.org On Wed, 19 Aug 2026, Sebastian Huber wrote: > >> Now clearly the `if` block is broken, we're setting PC from the wrong > >> place I think. > > > > Yep, the correct one would be ErrorEPC, unimplemented in sim AFAICT just > > as proper support for status_ERL, which has numerous implications beyond > > just ERET. > > I this something I should address within my patch set or is moving the > check_interrupts() after the if/else block enough? I have glanced over your change and I conclude that the idea here is to call check_interrupts() whenever CP0 Status or Config registers have been changed such as to possibly raise a software interrupt. Given how sim has been structured this seems a reasonable approach to me. For this I think just moving the call past the block is exactly what is needed. Also check_interrupts() needs to be called from DERET emulation, since clearing CP0 Debug.DM (Debug_DM) also re-enables interrupts (subject to CP0 Status conditions), and Debug_DM needs to be checked against in `interrupt_requested'. FWIW I think this would best be called `software_interrupt_requested' or suchlike to avoid the ambiguity. While one can read the comment, there's no need to force them doing so to figure out the intent. Then there's the preexisting issue with `interrupt_event' that does not check any of this beyond just CP0 Status.IE (status_IE). While it seems broken to me anyway, as I fail to see a place where `interrupt_pending' would be set, let's not let breakage accumulate. So I think bits from your `interrupt_requested' need to be factored out and used at both places, possibly as an introductory change. It's not clear to me how the argument to SignalExceptionInterrupt() is supposed to be used, but it's not interpreted anyway AFAICT, so let's just leave it as it is. As to adding proper support for ErrorEPC/status_ERL, you are obviously welcome to if you feel so inclined and in particular have a use for, but I wouldn't consider it a prerequisite for your patchset. In real hardware it's a feature used primarily in the context of handling CPU soft reset, NMI and cache error exceptions, which I think are secondary ISA features when it comes to sim. Maciej