From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 62049 invoked by alias); 3 Oct 2017 18:12:29 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Received: (qmail 61983 invoked by uid 89); 3 Oct 2017 18:12:28 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.2 required=5.0 tests=AWL,BAYES_00,RCVD_IN_DNSWL_NONE,RP_MATCHES_RCVD,SPF_PASS autolearn=ham version=3.3.2 spammy=promising, H*Ad:U*uweigand, Hx-languages-length:1629, regarded X-HELO: mailapp01.imgtec.com Received: from mailapp01.imgtec.com (HELO mailapp01.imgtec.com) (195.59.15.196) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Tue, 03 Oct 2017 18:12:27 +0000 Received: from HHMAIL01.hh.imgtec.org (unknown [10.100.10.19]) by Forcepoint Email with ESMTPS id 8761DBC3DCEBB; Tue, 3 Oct 2017 19:12:20 +0100 (IST) Received: from [10.20.78.131] (10.20.78.131) by HHMAIL01.hh.imgtec.org (10.100.10.21) with Microsoft SMTP Server id 14.3.361.1; Tue, 3 Oct 2017 19:12:23 +0100 Date: Tue, 03 Oct 2017 18:12:00 -0000 From: "Maciej W. Rozycki" To: Yao Qi CC: Ulrich Weigand , Bhushan Attarde , "gdb-patches@sourceware.org" Subject: Re: [RFC 2/3] Record function descriptor address instead of function address in value In-Reply-To: Message-ID: References: <20161017155133.A9B8711C257@oc8523832656.ibm.com> User-Agent: Alpine 2.00 (DEB 1167 2008-08-23) MIME-Version: 1.0 Content-Type: text/plain; charset="US-ASCII" X-SW-Source: 2017-10/txt/msg00062.txt.bz2 Hi Yao, On Fri, 28 Oct 2016, Yao Qi wrote: > > Overall I like the proposal and if this goes forward I will see if we can > > adapt the MIPS backend to use this approach as well, addressing the issues > > we still have remaining, such as confusing instruction addresses and wrong > > instruction data shown with `disass /r'. We have a little complication in > > that we have the ISA bit set in line information, so that would have to be > > stripped in DWARF record processing, but it should be much easier to do > > with a single hook in place than the complicated processing now required > > to copy ISA bit annotation from the symbol table (msymbols), the hooks to > > handle which we'll then be able to drop from our DWARF machinery. > > At the very beginning, I wanted to follow the MIPS approach in ARM, > but I realized some issues when writing the patch. Then, I switched to > the approach I am proposing in this thread. If the ISA bit plus function > address is regarded as a function descriptor, this approach should be > able to handle all of them (ppc64, arm and mips) correctly (and > cleanly, I hope). Have you made any progress with your solution? I saw Ulrich had concerns and it's been a while, silent, since we discussed it. Meanwhile we have started discovering corner case issues with compressed code disassembly, which I believe your change would fix. So we'd rather avoid creating more hooks (hacks) addressing these issues, only to remove them again once your obviously more promising solution has gone in. Maciej