From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 92513 invoked by alias); 27 Apr 2017 00:49:50 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Received: (qmail 92499 invoked by uid 89); 27 Apr 2017 00:49:48 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.1 required=5.0 tests=AWL,BAYES_00,RCVD_IN_DNSWL_NONE,RP_MATCHES_RCVD,SPF_PASS autolearn=ham version=3.3.2 spammy=rush, We'll, accessible, our X-HELO: mailapp01.imgtec.com Received: from mailapp01.imgtec.com (HELO mailapp01.imgtec.com) (195.59.15.196) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Thu, 27 Apr 2017 00:49:47 +0000 Received: from HHMAIL01.hh.imgtec.org (unknown [10.100.10.19]) by Forcepoint Email with ESMTPS id 8540331179039; Thu, 27 Apr 2017 01:49:46 +0100 (IST) Received: from [10.20.78.155] (10.20.78.155) by HHMAIL01.hh.imgtec.org (10.100.10.21) with Microsoft SMTP Server id 14.3.294.0; Thu, 27 Apr 2017 01:49:46 +0100 Date: Thu, 27 Apr 2017 00:49:00 -0000 From: "Maciej W. Rozycki" To: John Baldwin CC: , Luis Machado Subject: Re: [PATCH 4/4] Don't throw an error in 'info registers' for unavailable MIPS GP registers. In-Reply-To: <3860196.vBEQgn8TUC@ralph.baldwin.cx> Message-ID: References: <20170412183727.22483-1-jhb@FreeBSD.org> <17215390.QnBQOcfjcL@ralph.baldwin.cx> <3860196.vBEQgn8TUC@ralph.baldwin.cx> User-Agent: Alpine 2.00 (DEB 1167 2008-08-23) MIME-Version: 1.0 Content-Type: text/plain; charset="US-ASCII" X-SW-Source: 2017-04/txt/msg00725.txt.bz2 On Tue, 18 Apr 2017, John Baldwin wrote: > > Minimising changes is not our goal though, unlike making them correct. > > And I think we need to tell apart a situation where a register (FIR) is > > invalid according to the OS ABI and where a subset of registers may not > > always be accessible. > > For FreeBSD/mips in particular I will probably fix the FIR issue by fixing > FreeBSD to export FIR. We'll still have to handle old kernel versions that do not have the fix. > That said, 'info registers' on other architectures > is consistent in that they do not throw an error for an unavailable register > but annotate it as such. The goal of this patch was to align MIPS with > other architectures in terms of that behavior. Other architectures also > permit registers to be unavailable without requiring a custom target > description FWIW (e.g. the segment registers on x86 are effectively > "optional" and not always supplied by a target). Agreed, however you need to be clear in your patch description which of the two bugs present here it is intended to fix. > > Thanks for checking that. NB I find output above quite messy, especially > > the lack of column alignment, e.g. `r14' vs `r15'. It makes it hard to > > read for me. > > I don't disagree with the note on alignment. That is probably worth fixing > in a separate change. Sure, I haven't asked you or indeed anybody to rush fixing it (although obviously I won't mind either). I'll look through v2 of your changes and see if I have any further concerns. Maciej