From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 29943 invoked by alias); 15 Jan 2014 08:27:45 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Received: (qmail 29930 invoked by uid 89); 15 Jan 2014 08:27:43 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.0 required=5.0 tests=AWL,BAYES_00 autolearn=ham version=3.3.2 X-HELO: relay1.mentorg.com Received: from relay1.mentorg.com (HELO relay1.mentorg.com) (192.94.38.131) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Wed, 15 Jan 2014 08:27:43 +0000 Received: from svr-orw-fem-01.mgc.mentorg.com ([147.34.98.93]) by relay1.mentorg.com with esmtp id 1W3Lp5-0003RR-EJ from Maciej_Rozycki@mentor.com ; Wed, 15 Jan 2014 00:27:39 -0800 Received: from SVR-IES-FEM-01.mgc.mentorg.com ([137.202.0.104]) by svr-orw-fem-01.mgc.mentorg.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.4675); Wed, 15 Jan 2014 00:27:39 -0800 Received: from [172.30.6.97] (137.202.0.76) by SVR-IES-FEM-01.mgc.mentorg.com (137.202.0.104) with Microsoft SMTP Server id 14.2.247.3; Wed, 15 Jan 2014 08:27:36 +0000 Date: Wed, 15 Jan 2014 08:27:00 -0000 From: "Maciej W. Rozycki" To: Joel Brobecker CC: Subject: Re: [PATCH] AArch64: gdb.base/float.exp: Fix `info float' test In-Reply-To: <20140115034527.GH4762@adacore.com> Message-ID: References: <20140115034527.GH4762@adacore.com> User-Agent: Alpine 1.10 (DEB 962 2008-03-14) MIME-Version: 1.0 Content-Type: text/plain; charset="US-ASCII" X-SW-Source: 2014-01/txt/msg00491.txt.bz2 On Wed, 15 Jan 2014, Joel Brobecker wrote: > > gdb/testsuite/ > > * gdb.base/float.exp: Handle "aarch64*-*-*" targets. > > FWIW, no problem with the patch. But I don't know AArch64. > Does it always have an FPU? Otherwise, we perhaps should look at > what is being done for arm-*? Hard to tell, this popped up in testing, but I have no experience with AArch64 and with reasonable effort I couldn't track down an architecture manual that would clarify that. However there's a single features/aarch64.xml register description only, that includes FP registers unconditionally so my guess would be an FPU is implied, at least as far as GDB is concerned at this stage. I could be wrong though, e.g. for MIPS we have a couple of register descriptions, all of which include FP registers, but they only cover Linux targets where the FPU is a part of the OS ABI even where hardware has none and software emulation is used. And bare-iron MIPS targets certainly expose the lack of an FPU to GDB. Anyone can confirm one way or another? Maciej