diff --git a/sim/aarch64/memory.c b/sim/aarch64/memory.c
index 50f4837..f7eea22 100644
--- a/sim/aarch64/memory.c
+++ b/sim/aarch64/memory.c
@@ -78,6 +78,20 @@ FETCH_FUNC32 (int32_t,   int16_t, s16, 2)
 FETCH_FUNC32 (uint32_t,  uint8_t, u8, 1)
 FETCH_FUNC32 (int32_t,    int8_t, s8, 1)
 
+/* Specialized version of aarch64_get_mem_u32 for fetching instructions
+   which are always held in little endian order even on big-endian
+   configured targets.  */
+
+uint32_t
+aarch64_get_instruction (sim_cpu *cpu, uint64_t address)
+{
+  uint32_t val = aarch64_get_mem_u32 (cpu, address);
+
+  if (CURRENT_TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
+    val = _SWAP_4 (val);
+  return val;
+}
+
 void
 aarch64_get_mem_long_double (sim_cpu *cpu, uint64_t address, FRegister *a)
 {
diff --git a/sim/aarch64/memory.h b/sim/aarch64/memory.h
index 3f63973..3559245 100644
--- a/sim/aarch64/memory.h
+++ b/sim/aarch64/memory.h
@@ -37,6 +37,7 @@ extern uint32_t     aarch64_get_mem_u8  (sim_cpu *, uint64_t);
 extern int32_t      aarch64_get_mem_s8  (sim_cpu *, uint64_t);
 extern void         aarch64_get_mem_blk (sim_cpu *, uint64_t, char *, unsigned);
 extern const char * aarch64_get_mem_ptr (sim_cpu *, uint64_t);
+extern uint32_t     aarch64_get_instruction (sim_cpu *, uint64_t);
 
 extern void         aarch64_set_mem_long_double (sim_cpu *, uint64_t, FRegister);
 extern void         aarch64_set_mem_u64 (sim_cpu *, uint64_t, uint64_t);
diff --git a/sim/aarch64/simulator.c b/sim/aarch64/simulator.c
index 88cb03d..c70fd96 100644
--- a/sim/aarch64/simulator.c
+++ b/sim/aarch64/simulator.c
@@ -14083,7 +14083,7 @@ aarch64_step (sim_cpu *cpu)
     return FALSE;
 
   aarch64_set_next_PC (cpu, pc + 4);
-  aarch64_get_instr (cpu) = aarch64_get_mem_u32 (cpu, pc);
+  aarch64_get_instr (cpu) = aarch64_get_instruction (cpu, pc);
 
   TRACE_INSN (cpu, " pc = %" PRIx64 " instr = %08x", pc,
 	      aarch64_get_instr (cpu));