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Sun, 09 Nov 2025 12:15:05 -0800 (PST) Message-ID: Date: Sun, 9 Nov 2025 20:15:04 +0000 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4 6/6] gdb/doc: Document AArch64 FPMR support Content-Language: en-US To: Ezra.Sitorus@arm.com, gdb-patches@sourceware.org, Eli Zaretskii References: <20251031151641.83369-1-Ezra.Sitorus@arm.com> <20251031151641.83369-7-Ezra.Sitorus@arm.com> From: Luis In-Reply-To: <20251031151641.83369-7-Ezra.Sitorus@arm.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-BeenThere: gdb-patches@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gdb-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gdb-patches-bounces~public-inbox=simark.ca@sourceware.org Hi, On 31/10/2025 15:16, Ezra.Sitorus@arm.com wrote: > From: Ezra Sitorus > > Add NEWS entry and document new feature in gdb.texinfo. > --- > Changes from v3->v4: > * Removed unrelated changes in NEWS > * Fixup of index entry > * Formatting > > Ezra > > gdb/NEWS | 2 ++ > gdb/doc/gdb.texinfo | 71 +++++++++++++++++++++++++++++++++++++++++++++ > 2 files changed, 73 insertions(+) > > diff --git a/gdb/NEWS b/gdb/NEWS > index 01bd1524c7a..30683e7c3c7 100644 > --- a/gdb/NEWS > +++ b/gdb/NEWS > @@ -14,6 +14,8 @@ > this flag is used gdbserver will not escape special shell characters > within the inferior arguments. > > +* Support for Floating Point Mode Register (FPMR) in AArch64. > + > * New targets > > GNU/Linux/MicroBlaze (gdbserver) microblazeel-*linux* > diff --git a/gdb/doc/gdb.texinfo b/gdb/doc/gdb.texinfo > index 676143be416..6574eff9390 100644 > --- a/gdb/doc/gdb.texinfo > +++ b/gdb/doc/gdb.texinfo > @@ -27080,6 +27080,26 @@ Program received signal SIGSEGV, Segmentation fault > Guarded Control Stack error. > @end smallexample > > +@subsubsection AArch64 Floating Point Mode Register > +@cindex floating point mode register, AArch64 > +@cindex FPMR, AArch64 > + > +When @value{GDBN} is debugging the AArch64 architecture and the Floating Point > +Mode Register (FPMR) is available, then @value{GDBN} will make the @code{fpmr} > +available. This register determines the behaviour of FP8 instructions. > + > +To aid debugging, @value{GDBN} interprets the mode or value of each field in > +@code{fpmr}. > + > +@smallexample > +p $fpmr > +$1 = [ F8S1=E5M2 F8S2=E5M2 F8D=E5M2 OSM=Inf OSC=Inf/NaN LSCALE=0 NSCALE=0 LSCALE2=0 ] > +@end smallexample > + > +For more information about FPMR, please refer to the official > +@uref{https://developer.arm.com/documentation/ddi0601/latest,ignored, > +architecture registers documentation}. > + > @node x86 > @subsection x86 > > @@ -49770,6 +49790,57 @@ documentation} in the Linux kernel. > Extra registers are allowed in these features, but they will not affect > @value{GDBN}. > > +@subsubsection AArch64 FPMR feature > + > +The @samp{org.gnu.gdb.aarch64.fpmr} optional feature was introduced so > +@value{GDBN} could detect support for the Floating Point Mode Register > +extension. If present, this feature must have the following register: > + > +@itemize @minus > +@item > +@samp{fpmr}, the floating point mode register. It is represented as > +if it were a 64-bit register with a custom flags type. > +@end itemize > + > +The custom flags type allows @value{GDBN} to print a human-friendly > +representation of the contents of @code{fpmr} should contain: > + > +@itemize @minus > + > +@item > +@code{F8S1}, which is either @code{E5M2} or @code{E4M3} > + > +@item > +@code{F8S2}, which is either @code{E5M2} or @code{E4M3} > + > +@item > +@code{F8D}, which is either @code{E5M2} or @code{E4M3} > + > +@item > +@code{OSM}, which is either @code{Inf} or @code{MaxNormal} > + > +@item > +@code{OSC}, which is either @code{Inf/NaN} or @code{MaxNormal} > + > +@item > +@code{LSCALE}, which is a 7-bit unsigned value > + > +@item > +@code{NSCALE}, which is actually an 8-bit signed value but represented as an > +8-bit unsigned value > + > +@item > +@code{LSCALE2}, which is a 6-bit unsigned value > + > +@end itemize > + > +Extra registers are allowed in this feature, but they will not affect > +@value{GDBN}. > + > +For more information about FPMR, please refer to the official > +@uref{https://developer.arm.com/documentation/ddi0601/latest,ignored, > +architecture registers documentation}. > + > @node Alpha Features > @subsection Alpha Features > @cindex target descriptions, Alpha Features I have no further comments on this one. Once Eli is happy with the documentation changes, please push the series. If you don´t have commit access yet, I can do that for you. Thanks!