Re: [PATCH v3 2/3] [sim/riscv] Add support for compressed integer instruction set simulation

Mike Frysinger
2023-12-18T16:29:54Z

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On 17 Dec 2023 06:52, jaydeep.patil@imgtec.com wrote:
> Added support for compressed integer instruction set ("c").

you haven't responded to feedback in previous patches. please do that
before posting new ones, or clearly document in the patch the feedback
you've addressed as is standard git behavior.

> --- a/sim/riscv/sim-main.c
> +++ b/sim/riscv/sim-main.c
>
> +/* Return address register. */
> +#define REG_RA 1
> +
> +/* Stack pointer register. */
> +#define REG_SP 2

we already have SIM_RISCV_xxx_REGNUM. don't invent new ones.
-mike

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