[PATCH v3 0/3] sim: riscv: Compressed instruction simulation and semi-hosting support

jaydeep.patil
2023-12-17T06:52:55Z

From: Jaydeep Patil <jaydeep.patil@imgtec.com>

Hi Andrew,

Addressed review comments.

The compressed instructions can be tested without the need for GDB test
and semi-hosting support. Simulator specific tests are added in
sim/testsuite/riscv/c-ext.s file.

I have now combined the semi-hosting support in one patch (v3-0003-*). This is
based on semi-hosting calls generated by newlib (--specs=semihost.specs option)
and picolibc libraries.

Jaydeep Patil (3):
[sim/riscv] Fix crash during instruction decoding
[sim/riscv] Add support for compressed integer instruction set simulation
[sim/riscv] Add semi-hosting support

gdb/testsuite/gdb.arch/riscv-exit-getcmd.c | 26 +
gdb/testsuite/gdb.arch/riscv-exit-getcmd.exp | 27 +
.../gdb.arch/riscv-insn-simulation.c | 1542 +++++++++++++++++
.../gdb.arch/riscv-insn-simulation.exp | 31 +
sim/riscv/sim-main.c | 1131 +++++++++++-
sim/testsuite/riscv/c-ext.s | 110 ++
6 files changed, 2853 insertions(+), 14 deletions(-)
create mode 100644 gdb/testsuite/gdb.arch/riscv-exit-getcmd.c
create mode 100755 gdb/testsuite/gdb.arch/riscv-exit-getcmd.exp
create mode 100755 gdb/testsuite/gdb.arch/riscv-insn-simulation.c
create mode 100755 gdb/testsuite/gdb.arch/riscv-insn-simulation.exp
create mode 100755 sim/testsuite/riscv/c-ext.s

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2.25.1