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From: Mike Frysinger via Gdb-patches <gdb-patches@sourceware.org>
To: Dragan Mladjenovic <Dragan.Mladjenovic@syrmia.com>
Cc: Chao-ying Fu <cfu@wavecomp.com>,
	Faraz Shahbazker <fshahbazker@wavecomp.com>,
	gdb-patches@sourceware.org,
	"Maciej W . Rozycki" <macro@orcam.me.uk>
Subject: Re: [PATCH v4 4/4] sim: mips: Add simulator support for mips32r6/mips64r6
Date: Tue, 1 Feb 2022 22:47:23 -0500	[thread overview]
Message-ID: <Yfn+y8btspdFxNRe@vapier> (raw)
In-Reply-To: <20220201125302.30137-5-Dragan.Mladjenovic@syrmia.com>

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On 01 Feb 2022 13:53, Dragan Mladjenovic wrote:
> +static void update_fcsr (sim_cpu *, address_word , sim_fpu_status);

no space before the ,

> +static const int sim_fpu_class_mips_mapping[] = {
> +	FP_R6CLASS_SNAN, /* SIM_FPU_IS_SNAN = 1, Noisy not-a-number */
> +	FP_R6CLASS_QNAN, /* SIM_FPU_IS_QNAN = 2, Quiet not-a-number */
> +	FP_R6CLASS_NEGINF, /* SIM_FPU_IS_NINF = 3, -infinity */
> +	FP_R6CLASS_POSINF, /* SIM_FPU_IS_PINF = 4, +infinity */
> +	FP_R6CLASS_NEGNORM, /* SIM_FPU_IS_NNUMBER = 5, -num - [-MAX .. -MIN] */
> +	FP_R6CLASS_POSNORM, /* SIM_FPU_IS_PNUMBER = 6, +num - [+MIN .. +MAX] */
> +	FP_R6CLASS_NEGSUB, /* SIM_FPU_IS_NDENORM = 7, -denorm - (MIN .. 0) */
> +	FP_R6CLASS_POSSUB, /* SIM_FPU_IS_PDENORM = 8, +denorm - (0 .. MIN) */
> +	FP_R6CLASS_NEGZERO, /* SIM_FPU_IS_NZERO = 9, -0 */
> +	FP_R6CLASS_POSZERO /* SIM_FPU_IS_PZERO = 10, +0 */
> +};

2 space indent, not tab

> +uint64_t
> +fp_classify (sim_cpu *cpu,
> +	     address_word cia,
> +	     uint64_t op,
> +	     FP_formats fmt)
> +{
> +  sim_fpu wop;
> +
> +  /* The format type has already been checked:  */
> +  switch (fmt)
> +    {
> +    case fmt_single:
> +      sim_fpu_32to (&wop, op);
> +      break;
> +    case fmt_double:
> +      sim_fpu_64to (&wop, op);
> +      break;
> +    default:
> +      sim_io_error (SD, "Bad switch\n");
> +    }

i don't understand what the comment is trying to say

> +/* Common FMAC code for .s, .d. Defers setting FCSR to caller. */

2 spaces after . at end of sentences

> +static sim_fpu_status
> +inner_fmac (int (*sim_fpu_op) (sim_fpu *, const sim_fpu *, const sim_fpu *),
> +	    uint64_t op1,
> +	    uint64_t op2,
> +	    uint64_t op3,
> +	    sim_fpu_round round,
> +	    sim_fpu_denorm denorm,
> +	    FP_formats fmt,
> +	    uint64_t *result)
> +{
> ...
> +    default:
> +      fprintf (stderr, "Bad switch\n");
>        abort ();
> +      break;
> +    }
> +
> +  *result = t64;
> +  return status;
> +}
> +
> +static uint64_t
> +fp_fmac (sim_cpu *cpu,
> +	 address_word cia,
> +	 int (*sim_fpu_op) (sim_fpu *, const sim_fpu *, const sim_fpu *),
> +	 uint64_t op1,
> +	 uint64_t op2,
> +	 uint64_t op3,
> +	 FP_formats fmt)
> +{
> ...
> +  switch (fmt)
> +    {
> +    case fmt_single:
> +    case fmt_double:
> +      status = inner_fmac (sim_fpu_op, op1, op2, op3, round,
> +			   denorm, fmt, &result);

pass |cpu| to inner_mac so it can use sim_io_error
-mike

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      reply	other threads:[~2022-02-02  3:47 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-02-01 12:52 [PATCH v4 0/4] sim: Add support for MIPS32/64 revision 6 Dragan Mladjenovic
2022-02-01 12:52 ` [PATCH v4 1/4] sim: Allow toggling of quiet NaN-bit semantics Dragan Mladjenovic
2022-02-02  3:39   ` Mike Frysinger via Gdb-patches
2022-02-01 12:53 ` [PATCH v4 2/4] sim: Factor out NaN handling in floating point operations Dragan Mladjenovic
2022-02-01 12:53 ` [PATCH v4 3/4] sim: Add partial support for IEEE 754-2008 Dragan Mladjenovic
2022-02-02  3:42   ` Mike Frysinger via Gdb-patches
2022-02-01 12:53 ` [PATCH v4 4/4] sim: mips: Add simulator support for mips32r6/mips64r6 Dragan Mladjenovic
2022-02-02  3:47   ` Mike Frysinger via Gdb-patches [this message]

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