From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from simark.ca by simark.ca with LMTP id UGPlGxFX0WBeTgAAWB0awg (envelope-from ) for ; Mon, 21 Jun 2021 23:20:49 -0400 Received: by simark.ca (Postfix, from userid 112) id 6F7A31F1F2; Mon, 21 Jun 2021 23:20:49 -0400 (EDT) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on simark.ca X-Spam-Level: X-Spam-Status: No, score=-0.7 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,MAILING_LIST_MULTI,RDNS_DYNAMIC,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.2 Received: from sourceware.org (ip-8-43-85-97.sourceware.org [8.43.85.97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by simark.ca (Postfix) with ESMTPS id E0E7D1EE14 for ; Mon, 21 Jun 2021 23:20:48 -0400 (EDT) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 8B3493840029 for ; Tue, 22 Jun 2021 03:20:48 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 8B3493840029 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1624332048; bh=1wXeaqBQA9WILwpx+8S7lNHWOuZ3nSCYTX5JXKCVPyA=; h=Date:To:Subject:References:In-Reply-To:List-Id:List-Unsubscribe: List-Archive:List-Post:List-Help:List-Subscribe:From:Reply-To:Cc: From; b=tuUCeECzgOWAuvoJtnUp2JWjviav/b0ICC5YvJT0NIMWX03/5xC2VGFkTpRej4lEh 9QDj9Dauj5iP+kkYFAz0ghY1Vp28w95RK731e4BwdmL1G0htHlqzFCOAKkSRSp7HqR 5aZBphK6sk1J2HoSAO3EfCI+1sfxmzd7RnRmOI9Q= Received: from smtp.gentoo.org (dev.gentoo.org [IPv6:2001:470:ea4a:1:5054:ff:fec7:86e4]) by sourceware.org (Postfix) with ESMTP id 3A65638515D4 for ; Tue, 22 Jun 2021 03:20:28 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 3A65638515D4 Received: from vapier (localhost [127.0.0.1]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.gentoo.org (Postfix) with ESMTPS id 94BF8340806; Tue, 22 Jun 2021 03:20:26 +0000 (UTC) Date: Mon, 21 Jun 2021 23:20:25 -0400 To: Fredrik Hederstierna Subject: Re: [PATCH] sim: arm: add support for handling core dumps Message-ID: Mail-Followup-To: Fredrik Hederstierna , Luis Machado , Andrew Burgess , Simon Marchi , "gdb-patches@sourceware.org" , Paul Mathieu References: <20210118110922.GT265215@embecosm.com> <0327e6b6-2a4e-cf4f-333c-5f3cde18c49c@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline In-Reply-To: X-BeenThere: gdb-patches@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gdb-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , From: Mike Frysinger via Gdb-patches Reply-To: Mike Frysinger Cc: Simon Marchi , "gdb-patches@sourceware.org" , Paul Mathieu Errors-To: gdb-patches-bounces+public-inbox=simark.ca@sourceware.org Sender: "Gdb-patches" On 21 Jun 2021 06:30, Fredrik Hederstierna via Gdb-patches wrote: > The ARM simulator does not support all registers, and also crash in case of entering zero length when fetching registers. > This patch allow gcore to also work in ARM simulator, though by default it seems to dump full memory space 4GB, so core files get very large, though seems to work ok anyhow. dumping the entire address space doesn't sound unreasonable for bare metal env. you have an ELF which will tell you the memory regions it occupies directly, but there's no API i'm aware of to communicate things like stack & heap. that said, the arm sim has some non-ideal behavior. it allocates 2MiB by default, but after that, access to anywhere in the 4GiB address space will automatically allocate a page if one hasn't yet. if someone gets around to gutting arm's custom memory implementation and switching it to the common sim memory core, this would get fixed in the process ... > --- a/gdb/arm-tdep.c > +++ b/gdb/arm-tdep.c > @@ -4246,6 +4246,10 @@ arm_register_sim_regno (struct gdbarch *gdbarch, int regnum) > if (regnum >= ARM_WCGR0_REGNUM && regnum <= ARM_WCGR7_REGNUM) > return regnum - ARM_WCGR0_REGNUM + SIM_ARM_IWMMXT_COP1R8_REGNUM; > > + /* The current GDB ARM simulator does not support D0-D31 nor FPSCR. */ > + if (regnum >= ARM_D0_REGNUM && regnum <= ARM_FPSCR_REGNUM) > + return -1; > + > if (reg < NUM_GREGS) > return SIM_ARM_R0_REGNUM + reg; > reg -= NUM_GREGS; shouldn't this check be at the end of arm_register_sim_regno instead of calling internal error ? > --- a/sim/arm/wrapper.c > +++ b/sim/arm/wrapper.c > @@ -526,6 +526,10 @@ arm_reg_fetch (SIM_CPU *cpu, int rn, unsigned char *memory, int length) > > init (); > > + /* Check that memory and length are valid before fetching the register. */ > + if ((memory == NULL) || (length == 0)) > + return 0; why is the caller passing NULL to the sim ? -mike