From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from simark.ca by simark.ca with LMTP id nfRkD0UGfWCwZgAAWB0awg (envelope-from ) for ; Mon, 19 Apr 2021 00:25:41 -0400 Received: by simark.ca (Postfix, from userid 112) id 327BD1F104; Mon, 19 Apr 2021 00:25:41 -0400 (EDT) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on simark.ca X-Spam-Level: X-Spam-Status: No, score=-1.1 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,MAILING_LIST_MULTI,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.2 Received: from sourceware.org (server2.sourceware.org [8.43.85.97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by simark.ca (Postfix) with ESMTPS id 8839C1E813 for ; Mon, 19 Apr 2021 00:25:40 -0400 (EDT) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 2D3053953D36; Mon, 19 Apr 2021 04:25:40 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 2D3053953D36 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1618806340; bh=Hv0dqkrUfwAsWimmy/nDmMnUkMVCnGhW5fyz1z/uUsQ=; h=Date:To:Subject:References:In-Reply-To:List-Id:List-Unsubscribe: List-Archive:List-Post:List-Help:List-Subscribe:From:Reply-To:Cc: From; b=I9lb4uek786hf0whZ/Qt/ZxQRa+65wRDbqdhEgBp3cqS4vpX0gN96/nrcMkdTFOSH Rctthy7uAq0UuWtRzE6jsnOaUjKtrDOpQ2392fMfzIC9gyBYm40+InvtxkSpOyPVo3 hc+IRUFGQznZdYuTMN4w8MtWCPSZFd0q8X93XTFk= Received: from smtp.gentoo.org (smtp.gentoo.org [140.211.166.183]) by sourceware.org (Postfix) with ESMTP id A74853953CE6 for ; Mon, 19 Apr 2021 04:25:35 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.3.2 sourceware.org A74853953CE6 Received: from vapier (localhost [127.0.0.1]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.gentoo.org (Postfix) with ESMTPS id CD9AE335D0A; Mon, 19 Apr 2021 04:25:34 +0000 (UTC) Date: Mon, 19 Apr 2021 00:25:34 -0400 To: Jim Wilson Subject: Re: [PATCH 15/24] RISC-V sim: Improve cycle and instret counts. Message-ID: Mail-Followup-To: Jim Wilson , gdb-patches@sourceware.org, Kito Cheng References: <20210417175831.16413-1-jimw@sifive.com> <20210417175831.16413-16-jimw@sifive.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline In-Reply-To: <20210417175831.16413-16-jimw@sifive.com> X-BeenThere: gdb-patches@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gdb-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , From: Mike Frysinger via Gdb-patches Reply-To: Mike Frysinger Cc: Kito Cheng , gdb-patches@sourceware.org Errors-To: gdb-patches-bounces@sourceware.org Sender: "Gdb-patches" On 17 Apr 2021 10:58, Jim Wilson wrote: > @@ -2398,6 +2408,10 @@ initialize_cpu (SIM_DESC sd, SIM_CPU *cpu, int mhartid) > > cpu->csr.mimpid = 0x8000; > cpu->csr.mhartid = mhartid; > + cpu->csr.cycle = 0; > + cpu->csr.cycleh = 0; > + cpu->csr.instret = 0; > + cpu->csr.instreth = 0; if this is done so we can re-initialize the CPU and have all the CSR's be reset, we should do this with a single memset across all of cpu->csr right ? are there any that should be preserved ? if there were, i'd argue that cycle falls into that bucket too. -mike