From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from simark.ca by simark.ca with LMTP id UhsxLgXSpmM8XQgAWB0awg (envelope-from ) for ; Sat, 24 Dec 2022 05:18:45 -0500 Received: by simark.ca (Postfix, from userid 112) id AD9B01E222; Sat, 24 Dec 2022 05:18:45 -0500 (EST) Authentication-Results: simark.ca; dkim=pass (1024-bit key; secure) header.d=sourceware.org header.i=@sourceware.org header.a=rsa-sha256 header.s=default header.b=AiHBmXa8; dkim-atps=neutral X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on simark.ca X-Spam-Level: X-Spam-Status: No, score=-5.3 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED, URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 Received: from sourceware.org (server2.sourceware.org [8.43.85.97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by simark.ca (Postfix) with ESMTPS id A7BA91E110 for ; Sat, 24 Dec 2022 05:18:44 -0500 (EST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id A9DEF38493FF for ; Sat, 24 Dec 2022 10:18:43 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org A9DEF38493FF DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1671877123; bh=n25N51VRcE8caYaYHhCazRgKtg0dZp0lDkyfQjnkv7U=; h=Date:To:Cc:Subject:References:In-Reply-To:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From:Reply-To:From; b=AiHBmXa8Qw2Ubu+GsVwFsCiSl1sNab7o+Bg49Cfl9eDDcq/AO1pm2PW1bzSWUP6DW EU8syS9mnMMrQZ1l08/EOhWKwrq8dV2ujHgf6iiYZI0CjmkYIxeIt/z/j45h463R7a +Wibm2yIUYHjApKYsyCXFpjS4V/r28UxV8ljjJWk= Received: from mail-wm1-x32f.google.com (mail-wm1-x32f.google.com [IPv6:2a00:1450:4864:20::32f]) by sourceware.org (Postfix) with ESMTPS id 59A3138493DA for ; Sat, 24 Dec 2022 10:18:22 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 59A3138493DA Received: by mail-wm1-x32f.google.com with SMTP id bi26-20020a05600c3d9a00b003d3404a89faso6140180wmb.1 for ; Sat, 24 Dec 2022 02:18:22 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=in-reply-to:content-disposition:mime-version:references:message-id :subject:cc:to:from:date:x-gm-message-state:from:to:cc:subject:date :message-id:reply-to; bh=n25N51VRcE8caYaYHhCazRgKtg0dZp0lDkyfQjnkv7U=; b=Foa1z7v9NfS4LTGBX7lIBpJtfaU3aHTUSptjIOLw34GVW8tqvEP+z5n8HsmG7VTLYY tTtObZU9ffops1xnjIW+q6G7JlMXQIwpjM0VNy0dM2pvWbSGEtPbSkp+AN12jk++UTbL J4EiteH/JVL7JNs7wLPbXKKOovYwHKp8xErotqE1+1h1aRHSNEUU8JAs46XPkdA+id75 DBZgn3by8RNwHOXe2oINRkT1/ANhGQ3yrOmWKlwzNhRbLZ9CNCVuZ6lU3BeftEMPo52/ gJeWtx+viM1hGRVAyY5AwIKSakz2S8kQihw3OWPp+MjXx9lNwkep0Dh/Zk0l+HCZW3lG dUng== X-Gm-Message-State: AFqh2korEgDCPFRXdDctq02fuOm6YxEVr70Z73rwXvoDEIvvOHV9LSIG SVh3OWC+38ccqHfiCbNlB/Q= X-Google-Smtp-Source: AMrXdXsVDZU/E5v+ay5MYwxgdgoWEiar0Rf5Ed96S5cwwQUNK1Avvs4y0/CVPLmoF/E3iCyRR5KrCQ== X-Received: by 2002:a05:600c:3b93:b0:3d2:1bf6:5796 with SMTP id n19-20020a05600c3b9300b003d21bf65796mr9263449wms.35.1671877101018; Sat, 24 Dec 2022 02:18:21 -0800 (PST) Received: from localhost ([2a03:b0c0:1:d0::dee:c001]) by smtp.gmail.com with ESMTPSA id c10-20020a05600c0a4a00b003c6b70a4d69sm7304322wmq.42.2022.12.24.02.18.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 24 Dec 2022 02:18:20 -0800 (PST) Date: Sat, 24 Dec 2022 10:18:20 +0000 To: Mike Frysinger Cc: gdb-patches@sourceware.org Subject: Re: [PATCH] sim: or1k: move arch-specific settings to internal header Message-ID: References: <20221223060713.28821-1-vapier@gentoo.org> <20221224015539.8804-1-vapier@gentoo.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20221224015539.8804-1-vapier@gentoo.org> X-BeenThere: gdb-patches@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gdb-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , From: Stafford Horne via Gdb-patches Reply-To: Stafford Horne Errors-To: gdb-patches-bounces+public-inbox=simark.ca@sourceware.org Sender: "Gdb-patches" On Fri, Dec 23, 2022 at 08:55:39PM -0500, Mike Frysinger via Gdb-patches wrote: > There's no need for these settings to be in sim-main.h which is shared > with common/ sim code, so move it all out to the existing or1k-sim.h. > Unfortunately, we can't yet drop the or1k-sim.h include from sim-main.h > as many of the generated CGEN files refer only to sim-main.h. We'll > have to improve the CGEN interface before we can make more progress, > but this is at least a minor improvement. > --- > sim/or1k/or1k-sim.h | 27 +++++++++++++++++++++++++++ > sim/or1k/sim-main.h | 32 ++------------------------------ > sim/or1k/traps.c | 1 + > 3 files changed, 30 insertions(+), 30 deletions(-) > > diff --git a/sim/or1k/or1k-sim.h b/sim/or1k/or1k-sim.h > index 417272033cd1..61d542fcf7c8 100644 > --- a/sim/or1k/or1k-sim.h > +++ b/sim/or1k/or1k-sim.h > @@ -89,4 +89,31 @@ USI or1k32bf_make_load_store_addr (sim_cpu *current_cpu, USI base, SI offset, > USI or1k32bf_ff1 (sim_cpu *current_cpu, USI val); > USI or1k32bf_fl1 (sim_cpu *current_cpu, USI val); > > +#define OR1K_DEFAULT_MEM_SIZE 0x800000 /* 8M */ > + > +struct or1k_sim_cpu > +{ > + OR1K_MISC_PROFILE or1k_misc_profile; > +#define CPU_OR1K_MISC_PROFILE(cpu) (& OR1K_SIM_CPU (cpu)->or1k_misc_profile) > + > + /* CPU specific parts go here. > + Note that in files that don't need to access these pieces WANT_CPU_FOO > + won't be defined and thus these parts won't appear. This is ok in the > + sense that things work. It is a source of bugs though. > + One has to of course be careful to not take the size of this > + struct and no structure members accessed in non-cpu specific files can > + go after here. Oh for a better language. */ > + UWI spr[NUM_SPR]; > + > + /* Next instruction will be in delay slot. */ > + BI next_delay_slot; > + /* Currently in delay slot. */ > + BI delay_slot; > + > +#ifdef WANT_CPU_OR1K32BF > + OR1K32BF_CPU_DATA cpu_data; > +#endif > +}; > +#define OR1K_SIM_CPU(cpu) ((struct or1k_sim_cpu *) CPU_ARCH_DATA (cpu)) > + > #endif /* OR1K_SIM_H */ > diff --git a/sim/or1k/sim-main.h b/sim/or1k/sim-main.h > index 24c8ddb0e31a..7dd3e9a66550 100644 > --- a/sim/or1k/sim-main.h > +++ b/sim/or1k/sim-main.h > @@ -21,42 +21,14 @@ > > #define WITH_SCACHE_PBB 1 > > -#include "ansidecl.h" > #include "or1k-desc.h" > #include "or1k-opc.h" > #include "sim-basics.h" > #include "arch.h" > #include "sim-base.h" > -#include "sim-fpu.h" > - > #include "cgen-sim.h" > -#include "or1k-sim.h" > > -#define OR1K_DEFAULT_MEM_SIZE 0x800000 /* 8M */ > - > -struct or1k_sim_cpu > -{ > - OR1K_MISC_PROFILE or1k_misc_profile; > -#define CPU_OR1K_MISC_PROFILE(cpu) (& OR1K_SIM_CPU (cpu)->or1k_misc_profile) > - > - /* CPU specific parts go here. > - Note that in files that don't need to access these pieces WANT_CPU_FOO > - won't be defined and thus these parts won't appear. This is ok in the > - sense that things work. It is a source of bugs though. > - One has to of course be careful to not take the size of this > - struct and no structure members accessed in non-cpu specific files can > - go after here. Oh for a better language. */ > - UWI spr[NUM_SPR]; > - > - /* Next instruction will be in delay slot. */ > - BI next_delay_slot; > - /* Currently in delay slot. */ > - BI delay_slot; > - > -#ifdef WANT_CPU_OR1K32BF > - OR1K32BF_CPU_DATA cpu_data; > -#endif > -}; > -#define OR1K_SIM_CPU(cpu) ((struct or1k_sim_cpu *) CPU_ARCH_DATA (cpu)) > +/* TODO: Move this to the CGEN generated files instead. */ > +#include "or1k-sim.h" > > #endif /* SIM_MAIN_H */ > diff --git a/sim/or1k/traps.c b/sim/or1k/traps.c > index 97e81f41e7da..6fe94d88abd6 100644 > --- a/sim/or1k/traps.c > +++ b/sim/or1k/traps.c > @@ -23,6 +23,7 @@ > #define WANT_CPU > > #include "sim-main.h" > +#include "sim-fpu.h" > #include "sim-signal.h" > #include "cgen-ops.h" > > -- > 2.39.0 This all looks good to me. Please commit, -Stafford