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Thread-Topic: [PATCH 08/12] gdb: Handle shadow stack pointer register unwinding for amd64 linux. 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charset="us-ascii" MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: SN7PR11MB7638.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 5f777788-e5f2-4693-3672-08dd46bc2f45 X-MS-Exchange-CrossTenant-originalarrivaltime: 06 Feb 2025 14:40:21.6752 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: AE6Wm1kCs3L9OZIlLZ4MD8orecN2PZZewv4rXGVVBJZ6rrTBglB9rimAZ0ccf/jJVCzsnxoYEASOHN5iGaQAHGj0DuBRc12gBYGGQd+bIHc= X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN9PR11MB5259 X-OriginatorOrg: intel.com Content-Transfer-Encoding: quoted-printable X-BeenThere: gdb-patches@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gdb-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gdb-patches-bounces~public-inbox=simark.ca@sourceware.org > -----Original Message----- > From: Thiago Jung Bauermann > Sent: Thursday, February 6, 2025 4:30 AM > To: Schimpe, Christina > Cc: gdb-patches@sourceware.org > Subject: Re: [PATCH 08/12] gdb: Handle shadow stack pointer register unwi= nding > for amd64 linux. > = > = > "Schimpe, Christina" writes: > = > > Unwind the $pl3_ssp register. > > We now have an updated value for the shadow stack pointer when moving > > up or down the frame level. Note that $pl3_ssp can become unavailable > > when moving to a frame before the shadow stack enablement. In the > > example below, shadow stack is enabled in the function 'call1'. Thus, > > when moving to a frame level above the function, $pl3_ssp will become > > unavaiable. > > Following the restriction of the linux kernel, implement the unwinding > > for amd64 linux only. > > > > Before this patch: > > ~~~ > > Breakpoint 1, call2 (j=3D3) at sample.c:44 > > 44 return 42; > > (gdb) p $pl3_ssp > > $1 =3D (void *) 0x7ffff79ffff8 > > (gdb) up > > 55 call2 (3); > > (gdb) p $pl3_ssp > > $2 =3D (void *) 0x7ffff79ffff8 > > (gdb) up > > 68 call1 (43); > > (gdb) p $pl3_ssp > > $3 =3D (void *) 0x7ffff79ffff8 > > ~~~ > > > > After this patch: > > ~~~ > > Breakpoint 1, call2 (j=3D3) at sample.c:44 > > 44 return 42; > > (gdb) p $pl3_ssp > > $1 =3D (void *) 0x7ffff79ffff8 > > (gdb) up > > 55 call2 (3); > > (gdb) p $pl3_ssp > > $2 =3D (void *) 0x7ffff7a00000 > > (gdb) up > > 68 call1 (43i); > > (gdb) p $pl3_ssp > > $3 =3D > > ~~~ > > > > As we now have an updated value for each selected frame, the return > > command is now enabled for shadow stack enabled programs, too. > > > > We therefore add a test for the return command and shadow stack > > support, and for an updated shadow stack pointer after a frame level ch= ange. > > --- > > gdb/amd64-linux-tdep.c | 69 +++++++++++++++ > > gdb/linux-tdep.c | 47 ++++++++++ > > gdb/linux-tdep.h | 7 ++ > > .../gdb.arch/amd64-shadow-stack-cmds.exp | 88 +++++++++++++++++++ > > gdb/testsuite/gdb.arch/amd64-shadow-stack.c | 13 +++ > > 5 files changed, 224 insertions(+) > > create mode 100644 gdb/testsuite/gdb.arch/amd64-shadow-stack-cmds.exp > = > Just some minor comments. > = > Reviewed-by: Thiago Jung Bauermann > = > > diff --git a/gdb/amd64-linux-tdep.c b/gdb/amd64-linux-tdep.c index > > 95f643b1217..895feac85e8 100644 > > --- a/gdb/amd64-linux-tdep.c > > +++ b/gdb/amd64-linux-tdep.c > > @@ -45,6 +45,8 @@ > > #include "arch/amd64-linux-tdesc.h" > > #include "inferior.h" > > #include "x86-tdep.h" > > +#include "dwarf2/frame.h" > > +#include "frame-unwind.h" > > > > /* The syscall's XML filename for i386. */ #define > > XML_SYSCALL_FILENAME_AMD64 "syscalls/amd64-linux.xml" > > @@ -1873,6 +1875,72 @@ > amd64_linux_remove_non_address_bits_watchpoint (gdbarch *gdbarch, > > return (addr & amd64_linux_lam_untag_mask ()); } > > > > +static value * > > +amd64_linux_dwarf2_prev_ssp (const frame_info_ptr &this_frame, > > + void **this_cache, int regnum) { > = > Add documentation comment to this function. > = > > + value *v =3D frame_unwind_got_register (this_frame, regnum, regnum); > > + gdb_assert (v !=3D nullptr); > > + > > + gdbarch *gdbarch =3D get_frame_arch (this_frame); > > + > > + if (v->entirely_available () && !v->optimized_out ()) > > + { > > + int size =3D register_size (gdbarch, regnum); > > + bfd_endian byte_order =3D gdbarch_byte_order (gdbarch); > > + CORE_ADDR ssp =3D extract_unsigned_integer (v->contents_all ().d= ata (), > > + size, byte_order); > > + > > + /* Starting with v6.6., the Linux kernel supports CET shadow sta= ck. > > + Using /proc/PID/smaps we can only check if the current shadow > > + stack pointer SSP points to shadow stack memory. Only if this is > > + the case a valid previous shadow stack pointer can be > > + calculated. */ > > + std::pair range; > > + if (linux_address_in_shadow_stack_mem_range (ssp, &range)) > > + { > > + /* The shadow stack grows downwards. To compute the previous > > + shadow stack pointer, we need to increment SSP. > > + For x32 the shadow stack elements are still 64-bit aligned. > > + Thus, we cannot use gdbarch_addr_bit to compute the new stack > > + pointer. */ > > + const bfd_arch_info *binfo =3D gdbarch_bfd_arch_info (gdbarch); > > + const int bytes_per_word > > + =3D (binfo->bits_per_word / binfo->bits_per_byte); > > + CORE_ADDR new_ssp =3D ssp + bytes_per_word; > = > I agree with Guinevere's comment about introducing > amd64_linux_shadow_stack_element_size_aligned in this patch. > = > > + /* If NEW_SSP points to the end of or before (<=3D) the current > > + shadow stack memory range we consider NEW_SSP as valid (but > > + empty). */ > > + if (new_ssp <=3D range.second) > > + return frame_unwind_got_address (this_frame, regnum, new_ssp); > > + } > > + } > > + > > + /* Return a value which is marked as unavailable in case we could not > > + calculate a valid previous shadow stack pointer. */ > > + value *retval > > + =3D value::allocate_register (get_next_frame_sentinel_okay (this_f= rame), > > + regnum, register_type (gdbarch, regnum)); > > + retval->mark_bytes_unavailable (0, retval->type ()->length ()); > > + return retval; > > +} > > + > > +static void > > +amd64_init_reg (gdbarch *gdbarch, int regnum, dwarf2_frame_state_reg > *reg, > > + const frame_info_ptr &this_frame) > > +{ > > + if (regnum =3D=3D gdbarch_pc_regnum (gdbarch)) > > + reg->how =3D DWARF2_FRAME_REG_RA; > > + else if (regnum =3D=3D gdbarch_sp_regnum (gdbarch)) > > + reg->how =3D DWARF2_FRAME_REG_CFA; > > + else if (regnum =3D=3D AMD64_PL3_SSP_REGNUM) > > + { > > + reg->how =3D DWARF2_FRAME_REG_FN; > > + reg->loc.fn =3D amd64_linux_dwarf2_prev_ssp; > > + } > > +} > = > Add documentation comment to this function. > = > -- > Thiago Thank you for the review. I'll apply all your comments in the next version. Christina Intel Deutschland GmbH Registered Address: Am Campeon 10, 85579 Neubiberg, Germany Tel: +49 89 99 8853-0, www.intel.de Managing Directors: Sean Fennelly, Jeffrey Schneiderman, Tiffany Doon Silva Chairperson of the Supervisory Board: Nicole Lau Registered Office: Munich Commercial Register: Amtsgericht Muenchen HRB 186928