RE: [PATCH v5 00/12] Add CET shadow stack support

Schimpe, Christina
2025-07-13T14:02:54Z

Hi Luis,

Thanks for sharing that info.
I tried to reproduces with the same ubuntu & kernel versions and a very similar system but am not successful so far...
Just to be sure, I assume you test with gcc compiler (which version?) and compiled GDB with latest upstream master + my cet shadow stack patches?

Do you see this for target_board=native-gdbserver and target_board=unix?

Thanks,
Christina

> -----Original Message-----
> From: Luis Machado <luis.machado@arm.com>
> Sent: Friday, July 11, 2025 5:55 PM
> To: Schimpe, Christina <christina.schimpe@intel.com>; gdb-
> patches@sourceware.org
> Cc: thiago.bauermann@linaro.org
> Subject: Re: [PATCH v5 00/12] Add CET shadow stack support
>
> Hi Christina,
>
> On 7/11/25 14:54, Schimpe, Christina wrote:
> > Hi Luis,
> >
> > Thanks a lot for your testing efforts and spotting this.
> > That's interesting, I just double checked and am not able to reproduce.
> Would you mind sharing a couple of details, e.g the kernel version? I assume
> that your cpu has CET shadow stack support since the register appears as
> "unavailable".
>
> I'm running Ubuntu 24.04 on 6.8.0-63-generic.
>
> CPU is Intel(R) Core(TM) Ultra 7 165U, with these features:
>
> Flags: fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge m
> ca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 s
> s ht tm pbe syscall nx pdpe1gb rdtscp lm constant_tsc
> art arch_perfmon pebs bts rep_good nopl xtopology nons
> top_tsc cpuid aperfmperf tsc_known_freq pni pclmulqdq
> dtes64 monitor ds_cpl vmx smx est tm2 ssse3 sdbg fma c
> x16 xtpr pdcm pcid sse4_1 sse4_2 x2apic movbe popcnt t
> sc_deadline_timer aes xsave avx f16c rdrand lahf_lm ab
> m 3dnowprefetch cpuid_fault epb intel_ppin ssbd ibrs i
> bpb stibp ibrs_enhanced tpr_shadow flexpriority ept vp
> id ept_ad fsgsbase tsc_adjust bmi1 avx2 smep bmi2 erms
> invpcid rdseed adx smap clflushopt clwb intel_pt sha_
> ni xsaveopt xsavec xgetbv1 xsaves split_lock_detect us
> er_shstk avx_vnni dtherm ida arat pln pts hwp hwp_noti
> fy hwp_act_window hwp_epp hwp_pkg_req hfi vnmi umip pk
> u ospke waitpkg gfni vaes vpclmulqdq tme rdpid bus_loc
> k_detect movdiri movdir64b fsrm md_clear serialize pco
> nfig arch_lbr ibt flush_l1d arch_capabilities
>
>
> So slightly older than yours. Anything else I can share that would help?
>
> >
> > For me the shadow stack register is available in the corefile (ubuntu with
> linux kernel 6.13).
> >
> > (gdb) PASS: gdb.base/gcore.exp: where in corefile info registers^M
> > rax 0x0 0^M
> > [...]
> > k7 0x0 0^M
> > pl3_ssp <unavailable>^M
> > fs_base 0x7ffff7fae740 140737353803584^M
> > gs_base 0x0 0^M
> > (gdb) PASS: gdb.base/gcore.exp: corefile restored general registers
> >
> > Christina
> >
> >> -----Original Message-----
> >> From: Luis Machado <luis.machado@arm.com>
> >> Sent: Friday, July 11, 2025 12:37 PM
> >> To: Schimpe, Christina <christina.schimpe@intel.com>; gdb-
> >> patches@sourceware.org
> >> Cc: thiago.bauermann@linaro.org
> >> Subject: Re: [PATCH v5 00/12] Add CET shadow stack support
> >>
> >> Hi Christina,
> >>
> >> I went through v5 and I have no further comments.
> >>
> >> I did try running the testsuite on my local x86-64 machine and
> >> noticed a couple additional failures for native gdb testing.
> >>
> >> FAIL: gdb.base/gcore.exp: corefile restored general registers
> >> FAIL: gdb.base/gcore.exp: corefile restored all registers
> >>
> >> Have you seen those? The problem seems to be that the pl3_ssp
> >> register is showing up in a live session, but not in the core file.
> >>
> >> pl3_ssp <unavailable>
> >>
> >> On 6/28/25 09:27, Christina Schimpe wrote:
> >>> Hi all,
> >>>
> >>> this is my v5 of the series to add amd64 shadow stack support to GDB
> >>> on
> >> linux.
> >>> It addresses the feedback of Luis.
> >>>
> >>> v4 can be found here:
> >>> https://sourceware.org/pipermail/gdb-patches/2025-June/218744.html
> >>>
> >>> Changes since v4:
> >>> - Improve some comments.
> >>> - Change the test in "gdb: amd64 linux coredump support with shadow
> >>> stack." to also test core file generated by the linux kernel. This
> >>> requires changes for the core_find procedure to save program output,
> >>> that have been implemented by Thiago already, so we include this part
> >>> of the patch in this series: "gdb, testsuite: Extend core_find procedure
> >>> to save program output.". The test is now very similar to the test
> >>> implemented for Guarded Control Stack corefiles. Thanks to Thiago for
> >>> providing the input here!
> >>>
> >>> I am looking forward to your feedback!
> >>>
> >>> Regards,
> >>>
> >>> Christina
> >>>
> >>> Christina Schimpe (12):
> >>> gdb, testsuite: Extend core_find procedure to save program output.
> >>> gdbserver: Add optional runtime register set type.
> >>> gdbserver: Add assert in x86_linux_read_description.
> >>> gdb: Sync up x86-gcc-cpuid.h with cpuid.h from gcc 14 branch.
> >>> gdb, gdbserver: Use xstate_bv for target description creation on x86.
> >>> gdb, gdbserver: Add support of Intel shadow stack pointer register.
> >>> gdb: amd64 linux coredump support with shadow stack.
> >>> gdb: Handle shadow stack pointer register unwinding for amd64 linux.
> >>> gdb, gdbarch: Enable inferior calls for shadow stack support.
> >>> gdb: Implement amd64 linux shadow stack support for inferior calls.
> >>> gdb, gdbarch: Introduce gdbarch method to get the shadow stack
> >>> pointer.
> >>> gdb: Enable displaced stepping with shadow stack on amd64 linux.
> >>>
> >>> gdb/NEWS | 6 +
> >>> gdb/amd64-linux-nat.c | 17 ++
> >>> gdb/amd64-linux-tdep.c | 218 +++++++++++++++++-
> >>> gdb/amd64-tdep.c | 35 ++-
> >>> gdb/amd64-tdep.h | 9 +-
> >>> gdb/arch-utils.c | 10 +
> >>> gdb/arch-utils.h | 5 +
> >>> gdb/arch/amd64-linux-tdesc.c | 33 +--
> >>> gdb/arch/amd64-linux-tdesc.h | 7 +-
> >>> gdb/arch/amd64.c | 25 +-
> >>> gdb/arch/amd64.h | 10 +-
> >>> gdb/arch/i386-linux-tdesc.c | 29 +--
> >>> gdb/arch/i386-linux-tdesc.h | 5 +-
> >>> gdb/arch/i386.c | 19 +-
> >>> gdb/arch/i386.h | 8 +-
> >>> gdb/arch/x86-linux-tdesc-features.c | 60 ++---
> >>> gdb/arch/x86-linux-tdesc-features.h | 25 +-
> >>> gdb/doc/gdb.texinfo | 42 ++++
> >>> gdb/features/Makefile | 2 +
> >>> gdb/features/i386/32bit-ssp.c | 14 ++
> >>> gdb/features/i386/32bit-ssp.xml | 11 +
> >>> gdb/features/i386/64bit-ssp.c | 14 ++
> >>> gdb/features/i386/64bit-ssp.xml | 11 +
> >>> gdb/gdbarch-gen.c | 54 +++++
> >>> gdb/gdbarch-gen.h | 24 ++
> >>> gdb/gdbarch_components.py | 31 +++
> >>> gdb/i386-tdep.c | 51 +++-
> >>> gdb/i386-tdep.h | 11 +-
> >>> gdb/infcall.c | 14 +-
> >>> gdb/linux-tdep.c | 47 ++++
> >>> gdb/linux-tdep.h | 7 +
> >>> gdb/nat/x86-gcc-cpuid.h | 153 +++++++++---
> >>> gdb/nat/x86-linux-tdesc.c | 20 +-
> >>> gdb/nat/x86-linux-tdesc.h | 7 +-
> >>> gdb/nat/x86-linux.c | 57 +++++
> >>> gdb/nat/x86-linux.h | 4 +
> >>> .../gdb.arch/amd64-shadow-stack-cmds.exp | 141 +++++++++++
> >>> .../gdb.arch/amd64-shadow-stack-corefile.c | 42 ++++
> >>> .../gdb.arch/amd64-shadow-stack-corefile.exp | 110 +++++++++
> >>> .../gdb.arch/amd64-shadow-stack-disp-step.exp | 92 ++++++++
> >>> gdb/testsuite/gdb.arch/amd64-shadow-stack.c | 35 +++
> >>> gdb/testsuite/gdb.arch/amd64-ssp.exp | 50 ++++
> >>> .../gdb.base/inline-frame-cycle-unwind.py | 4 +
> >>> gdb/testsuite/lib/gdb.exp | 80 ++++++-
> >>> gdb/x86-linux-nat.c | 50 +++-
> >>> gdb/x86-linux-nat.h | 11 +
> >>> gdb/x86-tdep.c | 21 ++
> >>> gdb/x86-tdep.h | 9 +
> >>> gdbserver/i387-fp.cc | 40 ++--
> >>> gdbserver/linux-amd64-ipa.cc | 10 +-
> >>> gdbserver/linux-i386-ipa.cc | 6 +-
> >>> gdbserver/linux-low.cc | 50 ++--
> >>> gdbserver/linux-low.h | 7 +-
> >>> gdbserver/linux-x86-low.cc | 44 +++-
> >>> gdbsupport/x86-xstate.h | 7 +-
> >>> 55 files changed, 1687 insertions(+), 217 deletions(-) create mode
> >>> 100644 gdb/features/i386/32bit-ssp.c create mode 100644
> >>> gdb/features/i386/32bit-ssp.xml create mode 100644
> >>> gdb/features/i386/64bit-ssp.c create mode 100644
> >>> gdb/features/i386/64bit-ssp.xml create mode 100644
> >>> gdb/testsuite/gdb.arch/amd64-shadow-stack-cmds.exp
> >>> create mode 100644
> >>> gdb/testsuite/gdb.arch/amd64-shadow-stack-corefile.c
> >>> create mode 100644
> >>> gdb/testsuite/gdb.arch/amd64-shadow-stack-corefile.exp
> >>> create mode 100644
> >>> gdb/testsuite/gdb.arch/amd64-shadow-stack-disp-step.exp
> >>> create mode 100644 gdb/testsuite/gdb.arch/amd64-shadow-stack.c
> >>> create mode 100644 gdb/testsuite/gdb.arch/amd64-ssp.exp
> >>>
> >
> > Intel Deutschland GmbH
> > Registered Address: Am Campeon 10, 85579 Neubiberg, Germany
> > Tel: +49 89 99 8853-0, www.intel.de
> > Managing Directors: Sean Fennelly, Jeffrey Schneiderman, Tiffany Doon
> > Silva Chairperson of the Supervisory Board: Nicole Lau Registered
> > Office: Munich Commercial Register: Amtsgericht Muenchen HRB 186928

Intel Deutschland GmbH
Registered Address: Am Campeon 10, 85579 Neubiberg, Germany
Tel: +49 89 99 8853-0, www.intel.de
Managing Directors: Sean Fennelly, Jeffrey Schneiderman, Tiffany Doon Silva
Chairperson of the Supervisory Board: Nicole Lau
Registered Office: Munich
Commercial Register: Amtsgericht Muenchen HRB 186928